KR900007079A - 경사진 게이트전극을 갖는 박막트랜지스터의 제조방법 - Google Patents

경사진 게이트전극을 갖는 박막트랜지스터의 제조방법 Download PDF

Info

Publication number
KR900007079A
KR900007079A KR1019880014301A KR880014301A KR900007079A KR 900007079 A KR900007079 A KR 900007079A KR 1019880014301 A KR1019880014301 A KR 1019880014301A KR 880014301 A KR880014301 A KR 880014301A KR 900007079 A KR900007079 A KR 900007079A
Authority
KR
South Korea
Prior art keywords
thin film
gate electrode
film transistor
deposited
manufacturing thin
Prior art date
Application number
KR1019880014301A
Other languages
English (en)
Other versions
KR970000461B1 (ko
Inventor
박원규
소회섭
Original Assignee
최근선
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 최근선, 주식회사 금성사 filed Critical 최근선
Priority to KR1019880014301A priority Critical patent/KR970000461B1/ko
Publication of KR900007079A publication Critical patent/KR900007079A/ko
Application granted granted Critical
Publication of KR970000461B1 publication Critical patent/KR970000461B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Abstract

내용 없음

Description

경사진 게이트전극을 갖는 박막트랜지스터의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 박막트랜지스터의 제조공정을 차례로 나타낸 단면도이고,
제2도는 본 발명에 따른 전해에칭 구조를 나타낸 개략도이다.

Claims (2)

  1. 유리기판상에 게이트전극, 절연막, 비정질실리콘막 및 n+형 비정질실리콘막이 차례로 적층되고, 그 위에 소스전극과 드레인전극이 형성되어 있는 박막트랜지스터에 있어서, 게이트전극이 먼저 알루미늄을 증착하고, 그 위에 크롬을 증착하여 전해에칭함으로써 경사지게 형성되는 것을 특징으로 하는 박막트랜지스터의 제조방법.
  2. 제1항에 있어서, 게이트전극이 티타늄, 니켈, 황동, 청동, 코발트, 구리, 알루미늄 합금, 주석, 아연, 철 및 이들의 합금중에서 1종을 선택하여 증착하고, 그 위에 크롬을 증착하여 전해에칭하는 것을 특징으로 하는 박막트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880014301A 1988-10-31 1988-10-31 경사진 게이트전극을 갖는 박막트랜지스터의 제조방법 KR970000461B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880014301A KR970000461B1 (ko) 1988-10-31 1988-10-31 경사진 게이트전극을 갖는 박막트랜지스터의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880014301A KR970000461B1 (ko) 1988-10-31 1988-10-31 경사진 게이트전극을 갖는 박막트랜지스터의 제조방법

Publications (2)

Publication Number Publication Date
KR900007079A true KR900007079A (ko) 1990-05-09
KR970000461B1 KR970000461B1 (ko) 1997-01-11

Family

ID=19278937

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880014301A KR970000461B1 (ko) 1988-10-31 1988-10-31 경사진 게이트전극을 갖는 박막트랜지스터의 제조방법

Country Status (1)

Country Link
KR (1) KR970000461B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459801B1 (ko) * 1996-06-14 2005-01-17 엠비티홀딩에이.지 콘크리트 분사 첨가제

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6501094B1 (en) * 1997-06-11 2002-12-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising a bottom gate type thin film transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459801B1 (ko) * 1996-06-14 2005-01-17 엠비티홀딩에이.지 콘크리트 분사 첨가제

Also Published As

Publication number Publication date
KR970000461B1 (ko) 1997-01-11

Similar Documents

Publication Publication Date Title
KR940015562A (ko) 액정표시소자 제조방법
KR970052543A (ko) 바이어스 전압이 인가된 Cu 박막 형성방법
KR900007079A (ko) 경사진 게이트전극을 갖는 박막트랜지스터의 제조방법
KR950034766A (ko) 절연게이트형 전계효과 트랜지스터와 그 제법
KR920003534A (ko) 박막트랜지스터의 제조방법
KR930005253A (ko) 박막 트랜지스터의 제조방법
KR910013488A (ko) Difet에 의해 구동되는 박막 트랜지스터
KR930015068A (ko) 단차를 가진 게이트 절연막을 사용한 tft 제조방법
KR960006080A (ko) 박막트랜지스터 제조방법
KR960035876A (ko) 반도체 장치의 커패시터 유전체막 형성방법
KR900015359A (ko) 이중게이트 구조를 갖는 tft
KR900015350A (ko) 비정질 규소 박막 트랜지스터
KR920013770A (ko) 박막 트랜지스터 제조방법
KR960015049A (ko) 티에프티의 액티브 레이어 및 제조방법
KR940022706A (ko) 비아콘택 제조방법
KR910001932A (ko) Tft 제조방법
KR930011117A (ko) 블랭킷 cvd텅스텐 형성방법
KR930014974A (ko) TiN층으로 된 전하저장전극 형성방법
KR900017150A (ko) 다중 게이트 박막 트랜지스터 제조방법
KR910001933A (ko) Tft 제조방법
KR930015095A (ko) 박막트랜지스터
KR870011700A (ko) 박막 트랜지스터
KR940016499A (ko) 반도체소자의 배리어금속층 형성방법
KR950004594A (ko) 게이트 단차를 개선한 박막트랜지스터
KR860008608A (ko) 박막 트랜지스터의 제조 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20071231

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee