KR870002664A - 집적회로내의 mos 전계효과 트랜지스터 제조방법 - Google Patents
집적회로내의 mos 전계효과 트랜지스터 제조방법 Download PDFInfo
- Publication number
- KR870002664A KR870002664A KR1019860006624A KR860006624A KR870002664A KR 870002664 A KR870002664 A KR 870002664A KR 1019860006624 A KR1019860006624 A KR 1019860006624A KR 860006624 A KR860006624 A KR 860006624A KR 870002664 A KR870002664 A KR 870002664A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- silicon
- gate
- oxide
- forming
- Prior art date
Links
- 230000005669 field effect Effects 0.000 title claims description 4
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 8
- 229910052710 silicon Inorganic materials 0.000 claims 8
- 239000010703 silicon Substances 0.000 claims 8
- 229910052751 metal Inorganic materials 0.000 claims 5
- 239000002184 metal Substances 0.000 claims 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/147—Silicides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/966—Selective oxidation of ion-amorphousized layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제8도는 본 발명의 기술을 이용한 MOS 전계효과 트랜지스터의 여러가지 제조단계를 보인 집적회로 구조물의 횡단부에 대한 도해도.
* 도면의 주요 부분에 대한 부호 설명
10 : 집적회로 구조물 12 : P형 기판 14 : 에피텍셜층
18 : 게이트 산화물층 22,60 : 플리실리콘층 또는 비결정 실리콘층
24 : 실리콘 질화물층 30 : 게이트 31 : 측벽
32 : 실리콘 질화물 캡 40 : 이격 산화물 42, 44 : 소오스 영역
44,48 : 드레인 영역 56 : 굴절급속층 또는 텅스텐층 62 : 실리콘 산화물층
Claims (5)
- 표면과 이 표면상에 배치되는 산화물 게이트층을 가진 반도체 구조물내의 집적회로의 MOS 전계효과 트랜지스터를 제조하는 방법에 있어서, 상기 방법이 (a) 상부면고 한쌍의 측벽을 가진 상기 게이트 산화물 상에 비도우프된 실리콘 게이트를 형성하고, (b) 상기 측벽의 한 부분에 인접한 구조물과 상기 측벽의 다른부에 인접한 구조물내에 소오스 영역을 형성하며, (c) 상기 측벽을 포함하는 상기 실리콘 게이트상에 실리콘 산화물층을 형성하고, (d) 상기 각각의 소오스 및 드레인 영역과 상기 비도우프된 실리콘 게이트상에 노출된 실리콘 표면을 남기도록 상기 측벽상에만 실리콘 산화물을 남기는 상기 실리콘 산화물층을 부분을제거하며, (e) 상기 노출된 표면에만 굴절금속층을 형성하고, (f) 상기 굴절금속층에 폴리실리콘층을 형성하며,(g) 상기 각각의 노출된 표면에서 금속 규소화를 형성하도록 산소 대기압내에서 상기 굴절금속층 및 상기 폴리실리콘층과 상기 구조물을 가열하는 단계들로 이루어지는 것을 특징으로 하는 집적회로내의 MOS 전계효과 트랜지스터 제조방법.
- 제1항에 있어서, 상기 단계(d)로 상기 리콘산화물층 부분을 제거하는 것이 비등방성 식각을 이용하여 수행되는 것을 특징으로 하는 집적회로내의 MOS 전계효과 트랜지스터 제조방법.
- 제1항에 있어서, 단계(g)가 상기 폴리실리콘층을 완전히 산화시키는 것을 포함하는 것을 특징으로 하는 집적회로내의 전계효과 트랜지스터 제조방법.
- 제2항에 있어서, 상기 굴절금속이 텅스텐이 것을 특징으로 하는 집적 회로내의 MOS 전게효과 트랜지스터 제조방법.
- 제3항에 있어서, 단계(a) 및 (b)가 (i) 상기 게이트 산화물상에 비도우프된 실리콘층을 형성하고, (ii)상기 비도우프된 실리콘층상에 실리콘 질소화층을 형성하며, (iii) 상기 한쌍의 측벽과 실리콘 질화물 캡을 가진 비도우프된 실리콘 게이트를 형성하기 위하여 상기 실리콘 질화물층 및 비도우프된 실리콘층 부분을 제거하고, (iv) 상기 소오스 및 드레인 영역을 형성하며,(v) 상기 실리콘 질화물 캡을 제거하는 절차를 포함하는 것을 특징으로 하는 집적회로내의 MOS 전계효과 트랜지스터 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US764,551 | 1977-02-01 | ||
US06/764,551 US4660276A (en) | 1985-08-12 | 1985-08-12 | Method of making a MOS field effect transistor in an integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR870002664A true KR870002664A (ko) | 1987-04-06 |
KR950001950B1 KR950001950B1 (ko) | 1995-03-07 |
Family
ID=25071041
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019860006624A KR950001950B1 (ko) | 1985-08-12 | 1986-08-12 | 집적회로내의 mos전계효과 트랜지스터 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4660276A (ko) |
JP (1) | JP2615016B2 (ko) |
KR (1) | KR950001950B1 (ko) |
DE (1) | DE3626598C2 (ko) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4822749A (en) * | 1987-08-27 | 1989-04-18 | North American Philips Corporation, Signetics Division | Self-aligned metallization for semiconductor device and process using selectively deposited tungsten |
JPS6471526A (en) * | 1987-09-11 | 1989-03-16 | Masashi Ose | Coil winder |
US5288666A (en) * | 1990-03-21 | 1994-02-22 | Ncr Corporation | Process for forming self-aligned titanium silicide by heating in an oxygen rich environment |
JP2699839B2 (ja) * | 1993-12-03 | 1998-01-19 | 日本電気株式会社 | 半導体装置の製造方法 |
KR100190757B1 (ko) * | 1995-06-30 | 1999-06-01 | 김영환 | 모스 전계 효과 트랜지스터 형성방법 |
US6066555A (en) | 1995-12-22 | 2000-05-23 | Cypress Semiconductor Corporation | Method for eliminating lateral spacer erosion on enclosed contact topographies during RF sputter cleaning |
US5962904A (en) * | 1997-09-16 | 1999-10-05 | Micron Technology, Inc. | Gate electrode stack with diffusion barrier |
US6284633B1 (en) * | 1997-11-24 | 2001-09-04 | Motorola Inc. | Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode |
TW377461B (en) * | 1998-06-19 | 1999-12-21 | Promos Technologies Inc | Method of manufacturing gates |
US6509221B1 (en) * | 2001-11-15 | 2003-01-21 | International Business Machines Corporation | Method for forming high performance CMOS devices with elevated sidewall spacers |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3777364A (en) * | 1972-07-31 | 1973-12-11 | Fairchild Camera Instr Co | Methods for forming metal/metal silicide semiconductor device interconnect system |
US4128670A (en) * | 1977-11-11 | 1978-12-05 | International Business Machines Corporation | Fabrication method for integrated circuits with polysilicon lines having low sheet resistance |
US4227944A (en) * | 1979-06-11 | 1980-10-14 | General Electric Company | Methods of making composite conductive structures in integrated circuits |
US4384301A (en) * | 1979-11-07 | 1983-05-17 | Texas Instruments Incorporated | High performance submicron metal-oxide-semiconductor field effect transistor device structure |
US4356040A (en) * | 1980-05-02 | 1982-10-26 | Texas Instruments Incorporated | Semiconductor device having improved interlevel conductor insulation |
US4285761A (en) * | 1980-06-30 | 1981-08-25 | International Business Machines Corporation | Process for selectively forming refractory metal silicide layers on semiconductor devices |
US4330931A (en) * | 1981-02-03 | 1982-05-25 | Intel Corporation | Process for forming metal plated regions and lines in MOS circuits |
US4441247A (en) * | 1981-06-29 | 1984-04-10 | Intel Corporation | Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate |
US4389257A (en) * | 1981-07-30 | 1983-06-21 | International Business Machines Corporation | Fabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodes |
US4378628A (en) * | 1981-08-27 | 1983-04-05 | Bell Telephone Laboratories, Incorporated | Cobalt silicide metallization for semiconductor integrated circuits |
US4398341A (en) * | 1981-09-21 | 1983-08-16 | International Business Machines Corp. | Method of fabricating a highly conductive structure |
DE3211752C2 (de) * | 1982-03-30 | 1985-09-26 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum selektiven Abscheiden von aus Siliziden hochschmelzender Metalle bestehenden Schichtstrukturen auf im wesentlichen aus Silizium bestehenden Substraten und deren Verwendung |
DE3211761A1 (de) * | 1982-03-30 | 1983-10-06 | Siemens Ag | Verfahren zum herstellen von integrierten mos-feldeffekttransistorschaltungen in siliziumgate-technologie mit silizid beschichteten diffusionsgebieten als niederohmige leiterbahnen |
US4521952A (en) * | 1982-12-02 | 1985-06-11 | International Business Machines Corporation | Method of making integrated circuits using metal silicide contacts |
US4503601A (en) * | 1983-04-18 | 1985-03-12 | Ncr Corporation | Oxide trench structure for polysilicon gates and interconnects |
US4477310A (en) * | 1983-08-12 | 1984-10-16 | Tektronix, Inc. | Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas |
US4587710A (en) * | 1984-06-15 | 1986-05-13 | Gould Inc. | Method of fabricating a Schottky barrier field effect transistor |
-
1985
- 1985-08-12 US US06/764,551 patent/US4660276A/en not_active Expired - Lifetime
-
1986
- 1986-08-06 DE DE3626598A patent/DE3626598C2/de not_active Expired - Fee Related
- 1986-08-11 JP JP61189475A patent/JP2615016B2/ja not_active Expired - Lifetime
- 1986-08-12 KR KR1019860006624A patent/KR950001950B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950001950B1 (ko) | 1995-03-07 |
DE3626598C2 (de) | 1995-06-22 |
US4660276A (en) | 1987-04-28 |
JPS6239048A (ja) | 1987-02-20 |
JP2615016B2 (ja) | 1997-05-28 |
DE3626598A1 (de) | 1987-02-19 |
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