KR850700087A - 반도체 집적회로 - Google Patents

반도체 집적회로

Info

Publication number
KR850700087A
KR850700087A KR1019850700081A KR850700081A KR850700087A KR 850700087 A KR850700087 A KR 850700087A KR 1019850700081 A KR1019850700081 A KR 1019850700081A KR 850700081 A KR850700081 A KR 850700081A KR 850700087 A KR850700087 A KR 850700087A
Authority
KR
South Korea
Prior art keywords
region
groove
regions
integrated circuit
semiconductor
Prior art date
Application number
KR1019850700081A
Other languages
English (en)
Inventor
알랜 코퀸 제럴드
Original Assignee
아메리칸 텔리폰 앤드 텔레그라프 캄파니
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=27066485&utm_source=***_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR850700087(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 아메리칸 텔리폰 앤드 텔레그라프 캄파니 filed Critical 아메리칸 텔리폰 앤드 텔레그라프 캄파니
Publication of KR850700087A publication Critical patent/KR850700087A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

내용 없음

Description

반도체 집적회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 CMOS장치의 제1 실시예에 대한 횡단면도이고

Claims (3)

  1. 반도체 기판의 표면에서부터 연장되는 제1영역(30)과 제2영역(40)을 포함하고 상기 제2 영역의 전도형이 제1 영역의 전도형과 반대인 반도체 기판(20)과, 제1전계 효과 트랜지스터(130)와 제2전계 효과 트랜지스터(90)을 각각 포함하고, 상기 표면에서 부터 상기 제1영역과 상기 제2영역사이의 상기 기판으로 연장되는 유전체 채움물질(160)을 포함하는 홈(140)을 포함하며, 상기 제1트래지스터와 상기 제2트랜지스터의 채널 전도형이 상기 제1영역과 상기 제2영역의 전도형과 각각 반대인 상기 제1 및 제2영역을 포함하는 반도체 집적 회로로서, 상기 측벽의 홈은 홈 바닥에서 상향으로 발산하고, 수직에 대한 상기 벽의 각도는 약 5°에서 약 10°까지 범위에 있으며, 상기 채움 물질은 상기 홈을 완전히 채우고 기본적으로 공간을 제거하는 것을 특징으로 하는 반도체 집적회로.
  2. 제1항에 있어서, 상기 반도체 기판은 실리콘으로 구성되고 상기 채움 물질은 포리실리콘으로 구성된 것을 특징으로하는 반도체 집적회로.
  3. 제1항에 있어서, 상기 제1 및 제2 영역은 상기 제1 및 제2영역보다 강하게 도핑된 상기 기판의 제3영역(제3도의 영역(32)위에 있고, 제1실시예 (제2도)에서, 상기홈은 상기 제3영역으로 연장되며, 제2실시예.(제3도)에서, 상기 홈의 바닥은 상기 제3영역의 연장부(190)와 연속되며, 이에 의해 상기 두 실시예에서, 상기 제3영역은 상기 두 트랜지스터의 의도되지 않은 래치업을 방지하기 위하여 상기 홈과 협력하는 것을 특징으로 하는 반도체 집적회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019850700081A 1983-10-11 1984-10-04 반도체 집적회로 KR850700087A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US54062383A 1983-10-11 1983-10-11
US54062483A 1983-10-11 1983-10-11
US540.623 1983-10-11
US540.624 1983-10-11
PCT/US1984/001583 WO1985001836A1 (en) 1983-10-11 1984-10-04 Semiconductor integrated circuits containing complementary metal oxide semiconductor devices

Publications (1)

Publication Number Publication Date
KR850700087A true KR850700087A (ko) 1985-10-21

Family

ID=27066485

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850700081A KR850700087A (ko) 1983-10-11 1984-10-04 반도체 집적회로

Country Status (4)

Country Link
EP (2) EP0158670A1 (ko)
KR (1) KR850700087A (ko)
DE (1) DE3472604D1 (ko)
WO (1) WO1985001836A1 (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656730A (en) * 1984-11-23 1987-04-14 American Telephone And Telegraph Company, At&T Bell Laboratories Method for fabricating CMOS devices
SE8603126L (sv) * 1985-08-05 1987-02-06 Rca Corp Cmos-integrerad krets och metod att tillverka en sadan
GB2183907B (en) * 1985-11-27 1989-10-04 Raytheon Co Semiconductor device
US4936928A (en) * 1985-11-27 1990-06-26 Raytheon Company Semiconductor device
US4826781A (en) * 1986-03-04 1989-05-02 Seiko Epson Corporation Semiconductor device and method of preparation
US4729006A (en) * 1986-03-17 1988-03-01 International Business Machines Corporation Sidewall spacers for CMOS circuit stress relief/isolation and method for making
US5223731A (en) * 1988-06-30 1993-06-29 Goldstar Electron Co., Ltd. EPROM cell using trench isolation to provide leak current immunity
KR970000652B1 (ko) * 1988-06-30 1997-01-16 엘지반도체 주식회사 트랜치 분리를 이용한 eprom 셀 및 이의 제조방법
EP0382865A1 (de) * 1989-02-14 1990-08-22 Siemens Aktiengesellschaft Anordnung zur Verminderung von Latch-up-Störanfälligkeit bei CMOS-Halbleiterschaltungen
EP1195260A3 (en) 2000-10-03 2002-08-14 Fuji Photo Film Co., Ltd. Heat-sensitive recording material

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048175B1 (en) * 1980-09-17 1986-04-23 Hitachi, Ltd. Semiconductor device and method of manufacturing the same
US4486266A (en) * 1983-08-12 1984-12-04 Tektronix, Inc. Integrated circuit method

Also Published As

Publication number Publication date
DE3472604D1 (en) 1988-08-11
EP0138517A1 (en) 1985-04-24
EP0158670A1 (en) 1985-10-23
WO1985001836A1 (en) 1985-04-25
EP0138517B1 (en) 1988-07-06

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E601 Decision to refuse application