KR850005131A - 에피택셜 성장 기술에 의한 메사 트랜지스터의 제작방법 - Google Patents

에피택셜 성장 기술에 의한 메사 트랜지스터의 제작방법 Download PDF

Info

Publication number
KR850005131A
KR850005131A KR1019830005887A KR830005887A KR850005131A KR 850005131 A KR850005131 A KR 850005131A KR 1019830005887 A KR1019830005887 A KR 1019830005887A KR 830005887 A KR830005887 A KR 830005887A KR 850005131 A KR850005131 A KR 850005131A
Authority
KR
South Korea
Prior art keywords
epitaxial growth
mesa transistor
growth technology
manufacturing
transistor
Prior art date
Application number
KR1019830005887A
Other languages
English (en)
Other versions
KR850001439B1 (ko
Inventor
김도식
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019830005887A priority Critical patent/KR850001439B1/ko
Publication of KR850005131A publication Critical patent/KR850005131A/ko
Application granted granted Critical
Publication of KR850001439B1 publication Critical patent/KR850001439B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804Emitter regions of bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821Collector regions of bipolar transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Weting (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음

Description

에피택셜 성장기술에 의한 메사트랜지스터의 제작방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1(a)도~제1(i)도는 종래의 메사트랜지스터의 제작공정도.
제2(a)도~제2(h)도는 본 발명에 따른 메사트랜지스터의 제작공정도.

Claims (1)

  1. 메사 트랜지스터의 제작방법에 있어서, 소자형성 부분만 선택 에피택셜 성장을 시켜 베이스층(14)으로 하고 에미터(17)를 확산시켜 웨트 에칭방법을 제거함을 특징으로 하는 에피택셜 성장 기술에 의한 메사트랜지스터의 제작방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019830005887A 1983-12-08 1983-12-08 에피택셜 성장기술에 의한 메사트랜지스터의 제작방법 KR850001439B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019830005887A KR850001439B1 (ko) 1983-12-08 1983-12-08 에피택셜 성장기술에 의한 메사트랜지스터의 제작방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019830005887A KR850001439B1 (ko) 1983-12-08 1983-12-08 에피택셜 성장기술에 의한 메사트랜지스터의 제작방법

Publications (2)

Publication Number Publication Date
KR850005131A true KR850005131A (ko) 1985-08-21
KR850001439B1 KR850001439B1 (ko) 1985-10-02

Family

ID=19230593

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830005887A KR850001439B1 (ko) 1983-12-08 1983-12-08 에피택셜 성장기술에 의한 메사트랜지스터의 제작방법

Country Status (1)

Country Link
KR (1) KR850001439B1 (ko)

Also Published As

Publication number Publication date
KR850001439B1 (ko) 1985-10-02

Similar Documents

Publication Publication Date Title
KR890007434A (ko) 반도체 장치 제조방법
KR880001058A (ko) 헤테로 접합형 바이폴러트랜지스터의 제조방법
KR850005131A (ko) 에피택셜 성장 기술에 의한 메사 트랜지스터의 제작방법
KR890001168A (ko) 반도체 장치에서의 절연산화물 형성방법 및 그 방법에 따라 제조된 반도체 장치
KR880010495A (ko) 반도체장치의 제조방법
KR880013256A (ko) 헤테로접합형 바이폴라트랜지스터 및 그 제조방법
KR860001488A (ko) 바이폴러 트랜지스터와 iil이 있는 반도체 장치
KR880008479A (ko) 반도체레이저장치의 제조방법
KR910008853A (ko) 반도체장치와 그 제조방법
KR910013568A (ko) 화합물 반도체 장치 및 그 제조방법
KR900005615A (ko) 보톰콜렉터를 이용한 바이폴러 반도체소자 및 그 제조방법
KR910017664A (ko) 바이폴라 트랜지스터 제조방법
KR860000704A (ko) 반도 체장치의 제법
KR910002002A (ko) 셀프 얼라인을 이용한 고집적 바이폴라 트랜지스터의 제조방법
KR920015615A (ko) 바이폴라 트랜지스터의 제조방법
KR880009445A (ko) 반도체 장치의 제조방법
KR920001747A (ko) 바이폴라 트랜지스터의 디프콜렉터 제조방법
KR890004386A (ko) 화합물 반도체 제조방법
KR920007286A (ko) 반도체 레이저 다이오드
KR900007076A (ko) 바이플라 소자의 분리층 형성방법
KR870005475A (ko) 정전압 다이오드의 제작방법
KR910010663A (ko) 콘택 제조방법
KR840004307A (ko) 선형소자와 공존하는 종방향 전류 주임형 집적주임논리 소자 및 그 제조방법
KR900017143A (ko) 바이-씨모스 반도체소자 제조방법
KR890016681A (ko) I^2l디지탈 소자 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
O035 Opposition [patent]: request for opposition
E701 Decision to grant or registration of patent right
O073 Decision to grant registration after opposition [patent]: decision to grant registration
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20020906

Year of fee payment: 18

LAPS Lapse due to unpaid annual fee