KR850002696A - 유전체 격리 구조를 가진 보상 반도체 장치를 제조 하는 방법 - Google Patents
유전체 격리 구조를 가진 보상 반도체 장치를 제조 하는 방법 Download PDFInfo
- Publication number
- KR850002696A KR850002696A KR1019840005729A KR840005729A KR850002696A KR 850002696 A KR850002696 A KR 850002696A KR 1019840005729 A KR1019840005729 A KR 1019840005729A KR 840005729 A KR840005729 A KR 840005729A KR 850002696 A KR850002696 A KR 850002696A
- Authority
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- South Korea
- Prior art keywords
- layer
- forming
- semiconductor
- mesa portion
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000002955 isolation Methods 0.000 title claims description 3
- 239000010410 layer Substances 0.000 claims 21
- 230000000873 masking effect Effects 0.000 claims 7
- 238000000034 method Methods 0.000 claims 7
- 239000013078 crystal Substances 0.000 claims 6
- 238000004519 manufacturing process Methods 0.000 claims 6
- 239000011241 protective layer Substances 0.000 claims 5
- 239000000758 substrate Substances 0.000 claims 5
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
- H01L21/82285—Complementary vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/928—Front and rear surface processing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/969—Simultaneous formation of monocrystalline and polycrystalline regions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Weting (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 4, 6, 7도는 본 발명에 따르는 제품의 여러 스테이지에서 유전체 격리구조를 가진 보상 반도체 장치의 객략적인 부분 단면도.
Claims (10)
- 유전체 격리 구조에서 적어도 하나의 p형 아일런드(island)와 적어도 하나의 n형 아일런드를 가지며 제1전도형을 가지는 단결정 반도체 기판의 제1메사 부분을 형성하는 단계와, 상기 제1메사 부분을 절연층으로만 덮는 단계와, 상기 절연층상에 다결정 반도체층을 형성하기 위해서 및 상기 기판의 노출면에 상기 제1전도형과 반대인 제2전도형의 결정반 도체층을 형성하기 위해서 반도체층을 애피택셜하게 성장시키는 단계와, 상기 다결정 반도체층과 단결정 반도체층상에 보호층을 형성하는 단계와, 상기 제1메사 부분의 상부에 있는 상기 보호층을 선택적으로 제거시키는 단계, 및 상기 보호층을 마스크로 사용함으로써 상기 제1메사 부분의 상기 노출된 다결정 반도체층을 제거시키는 단계로 구성되는 것을 특징으로 하는 보상 반도체장치를 제조 하는 방법.
- 제1항에 있어서, 상기 제거하는 단계후에, 상기 단결정 반도체층상에 마스킹층을 선택적으로 형성하는 단계와, 남아 있는 다결정 반도체층을 제거시키는 단계와, 상기 마스킹층을 이용하여 선택적으로 그것을 애칭시킴으로써 상기 단결정층의 제2메사 부분을 형성하는 단계와, 상기 마스킹층을 제거시키는 단계와, 상기 제2메사 부분 및 다른 절연층과 함께 상기 제1메사 부분을 포함하는 상기 기판의 노출면을 덮는 단계와, 상기 다른 절연층상에 지지층을 형성하는 단계 및 상기 제1 및 제2메사 부분을 아일런드로 고립시키고 상기 다른 절연층의 부분을 노출시키기 위해 상기 기판을 백래프(backlap)시키는 단계로 구성되는 것을 특징으로 하는 보상 반도체 장치를 제조하는 방법.
- 제1항에 있어서, 상기 보호층을 선택적으로 제거시키는 상기 단계가 래핑(lapping)방법에 의해 실행되는 것을 특징으로 하는 보상 반도체 장치를 제조하는 방법.
- 제1항에 있어서, 제1메사 부분의 상기 형성 단계에서 비등방성 애칭액이 사용되는 것을 특징으로 하는 보상 반도체 장치를 제조하는 방법.
- 제1항에 있어서, 마스킹층의 선택적으로 형성한 상기 단계에 앞서, 상기 보호층을 제거시키는 단계와 전노출면 상에 또ㄷ른 마스킹층을 형성하는 단계가 추가로 구성되는 것을 특징으로 하는 보상 반도체 장치를 제조하는 방법.
- 제5항에 있어서, 상기 제거에 앞서, 상기 잔존하는 다결정 반도체층의 제거를 위한 마스크를 형성하기 위해 상기 다른 마스킹층을 선택적으로 애칭시키는 단계가 추가로 구성되는 것을 특징으로 하는 보상 반도체 장치를 제조하는 방법.
- 제2항에 있어서, 제2메사 부분의 상기 형성 단계에서, 비등방성 에칭액이 사용되는 것을 특징으로 하는 보상 반도체 장치를 제조하는 방법.
- 제1항에 있어서, 상기 단결정 반도체 기판이 실리콘인 것을 특징으로 하는 보상 반도체 장치를 제조하는 방법.
- 제1항에 있어서, 상기 반도체 재료가 실리콘인 것을 특징으로 하는 보상 반도체 장치를 제조하는 방법.
- 제2항에 있어서, 상기 지지층이 다결정 실리콘인 것을 특징으로 하는 보상 반도체 장치를 제조하는 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58-182006 | 1983-09-30 | ||
JP???58-182006 | 1983-09-30 | ||
JP58182006A JPS6074635A (ja) | 1983-09-30 | 1983-09-30 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR850002696A true KR850002696A (ko) | 1985-05-15 |
KR890003146B1 KR890003146B1 (ko) | 1989-08-23 |
Family
ID=16110672
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019840005729A KR890003146B1 (ko) | 1983-09-30 | 1984-09-19 | 유전체 격리구조를 가진 보상 반도체장치를 제조하는 방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4579625A (ko) |
EP (1) | EP0140749B1 (ko) |
JP (1) | JPS6074635A (ko) |
KR (1) | KR890003146B1 (ko) |
DE (1) | DE3473690D1 (ko) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6081839A (ja) * | 1983-10-12 | 1985-05-09 | Fujitsu Ltd | 半導体装置の製造方法 |
US4961097A (en) * | 1985-03-11 | 1990-10-02 | Motorola Inc. | High frequency photo detector and method for the manufacture thereof |
US4839711A (en) * | 1986-10-16 | 1989-06-13 | Harris Corporation | Dielectric for laser trimming |
US4870029A (en) * | 1987-10-09 | 1989-09-26 | American Telephone And Telegraph Company, At&T-Technologies, Inc. | Method of forming complementary device structures in partially processed dielectrically isolated wafers |
US4820653A (en) * | 1988-02-12 | 1989-04-11 | American Telephone And Telegraph Company | Technique for fabricating complementary dielectrically isolated wafer |
US6228750B1 (en) | 1994-12-30 | 2001-05-08 | Lucent Technologies | Method of doping a semiconductor surface |
KR20100013649A (ko) * | 2008-07-31 | 2010-02-10 | 삼성전자주식회사 | 광전소자 및 이의 제조 방법 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5642352A (en) * | 1979-09-17 | 1981-04-20 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of composite semiconductor device |
US4408386A (en) * | 1980-12-12 | 1983-10-11 | Oki Electric Industry Co., Ltd. | Method of manufacturing semiconductor integrated circuit devices |
JPS57204133A (en) * | 1981-06-10 | 1982-12-14 | Hitachi Ltd | Manufacture of semiconductor integrated circuit |
JPS59202647A (ja) * | 1983-05-02 | 1984-11-16 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
-
1983
- 1983-09-30 JP JP58182006A patent/JPS6074635A/ja active Granted
-
1984
- 1984-09-19 KR KR1019840005729A patent/KR890003146B1/ko not_active IP Right Cessation
- 1984-09-19 US US06/652,075 patent/US4579625A/en not_active Expired - Fee Related
- 1984-09-21 DE DE8484401871T patent/DE3473690D1/de not_active Expired
- 1984-09-21 EP EP84401871A patent/EP0140749B1/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPH0338741B2 (ko) | 1991-06-11 |
DE3473690D1 (en) | 1988-09-29 |
JPS6074635A (ja) | 1985-04-26 |
EP0140749A1 (en) | 1985-05-08 |
KR890003146B1 (ko) | 1989-08-23 |
US4579625A (en) | 1986-04-01 |
EP0140749B1 (en) | 1988-08-24 |
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