KR840000134A - Code conversion and interpolation system for digital television - Google Patents

Code conversion and interpolation system for digital television Download PDF

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Publication number
KR840000134A
KR840000134A KR1019820002073A KR820002073A KR840000134A KR 840000134 A KR840000134 A KR 840000134A KR 1019820002073 A KR1019820002073 A KR 1019820002073A KR 820002073 A KR820002073 A KR 820002073A KR 840000134 A KR840000134 A KR 840000134A
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South Korea
Prior art keywords
signal
coupled
samples
signals
sample
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KR1019820002073A
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Korean (ko)
Inventor
하링톤 파우어즈 컴스
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글렌 에이취.브르스틀
알.씨.에이.코포레이션
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Application filed by 글렌 에이취.브르스틀, 알.씨.에이.코포레이션 filed Critical 글렌 에이취.브르스틀
Publication of KR840000134A publication Critical patent/KR840000134A/en

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00Television systems
    • H04N7/01Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0135Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Color Television Systems (AREA)
  • Processing Of Color Television Signals (AREA)
  • Complex Calculations (AREA)

Abstract

내용 없음No content

Description

디지탈 텔레비젼용 코드변환 및 보간시스템Code conversion and interpolation system for digital television

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 한 특성에 따른 디지탈 부분을 포함하는 텔레비젼 시스템에 대한 블록선도, 제2도는 제1도 배열의 어떤 특성을 이해하는데 유용한 타이밍 신호, 제3도는 NTSC합성 칼라텔레비젼 신호를 제1도배열의 표준규격에 따른 신호로 트랜스코딩할 때의 상대 샘플링시간을 이해하는데 유용한 타이밍선도, 제4도는 원래 샘플된 신호값에 대한 신 샘플점에서의 보간을 통해 트랜스코딩으로부터 야기된 에러를 이해하는데 도움이 되는 일반화된 파형도, 제5도는 트랜스코딩과 관련된 본 발명의 실시예에 대한 블록선도.1 is a block diagram of a television system including a digital portion in accordance with an aspect of the present invention, FIG. 2 is a timing signal useful for understanding certain characteristics of the FIG. 1 arrangement, and FIG. 3 is an NTSC composite color television signal. A timing diagram useful for understanding the relative sampling time when transcoding into a signal conforming to the standard of the array. FIG. 4 illustrates the error resulting from transcoding through interpolation at the new sample point for the original sampled signal value. A generalized waveform diagram that is helpful, FIG. 5 is a block diagram of an embodiment of the invention with respect to transcoding.

Claims (1)

제2신호를 형성하도록 보간되어야 하는 그러한 제1신호 샘플들의 근사값에 의해 제1주파수(F1)에서 샘플된 제1텔레비젼 신호를 제2샘플된 신호로 코드변환 하기 위한 트랜스코더에 있어서, 상기 제1신호원에 결합되어 상기 제1 및 제2주파수비가 실질적으로 정수의 몫과 같도록 선택된 제2주파수에서 제2신호샘플링 클록신호를 발생하며, 이에 의해 상기 샘플점이 블록들내에서 순환되는데, 여기에서 각각의 상기 블록들내에 있는 상기 제1 및 제2신호의 제1샘플이 실질적으로 동시에 발생하고 각각의 상기 블록들내에 있는 상기 제1 및 제2신호중 최종 샘플점이 실질적으로 동시에 발생하며 또 각각의 상기 블록내에 있는 상기 제1 및 제2신호중 어느하나의 샘플수가 상기 제1 및 제2신호중 다른것의 샘플수를 초과하므로 상기 제2신호 샘플의 발생시간이 상기 블록들중 하나의 지속시간에 걸쳐 인접 제1샘플점의 샘플발생시간 사이에서 이동하는 클록신호 발생기(512,502)와 상기 제1신호를 수신하도록 결합되어 상기 제1신호로부터 지연된 적어도 제2 및 제3의 지연된 신호를 형성하도록 상기 제1신호를 지연시키는 지연수단(504,506,1107,508)과 상기 클록신호 발생기에 결합되어 상기 제1신호의 연속 샘플 사이에서 각 신샘플의 시간위치에 관계된 주행변수를 발생시키는 주행가변신호 발생기(510,1104)와 상기 지연수단 및 상기 주행 가변신호에 결합되어 상기 지연된 신호를 수신하고 웨이트된 피지연 신호를 형성하도록 상기 주행변수에 의해 상기 지연된 신호를 체배하는 체배수단(516,518,520,522), 그리고, 상기 체배수단에 결합되어 상기 웨이트된 피지연신호를 함께 합산하는 합산수단(522)을 특징으로 하는 디지탈 텔레비젼 시스템.A transcoder for transcoding a first television signal sampled at a first frequency F 1 into a second sampled signal by an approximation of such first signal samples that should be interpolated to form a second signal, wherein Coupled to one signal source to generate a second signal sampling clock signal at a second frequency selected such that the first and second frequency ratios are substantially equal to the quotient of the integer, whereby the sample points are circulated within the blocks, wherein Wherein first samples of the first and second signals in each of the blocks occur substantially simultaneously and a final sample point of the first and second signals in each of the blocks occurs substantially simultaneously; Since the number of samples of any one of the first and second signals in the block exceeds the number of samples of the other of the first and second signals, the generation time of the second signal sample is At least a second and a second coupled to receive the first signal with a clock signal generator 512,502 moving between the sample generation times of an adjacent first sample point over a duration of one of the blocks; Traveling parameters related to the time position of each new sample between successive samples of the first signal coupled to the clock signal generator and delay means 504,506, 1107,508 for delaying the first signal to form a delayed signal of three. A multiplication multiplying the delayed signal by the traveling variable to be coupled to the traveling variable signal generators 510 and 1104 and the delay means and the traveling variable signal to receive the delayed signal and form a weighted delayed signal; Means (516, 518, 520, 522) and a summation means (522) coupled to the multiplication means for summing the weighted delayed signals together; TV system. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019820002073A 1981-05-11 1982-05-11 Code conversion and interpolation system for digital television KR840000134A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US26261981A 1981-05-11 1981-05-11
US262,619 1981-05-11

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KR840000134A true KR840000134A (en) 1984-01-30

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JP (1) JPS581378A (en)
KR (1) KR840000134A (en)
AU (1) AU8327682A (en)
DE (1) DE3217681A1 (en)
ES (1) ES511906A0 (en)
FI (1) FI821562L (en)
FR (1) FR2506102B1 (en)
GB (2) GB2100092B (en)
IT (1) IT1151396B (en)
NL (1) NL8201914A (en)
PT (1) PT74839B (en)
SE (1) SE8202741L (en)
ZA (1) ZA823237B (en)

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US4605962A (en) * 1984-11-30 1986-08-12 Rca Corporation Progressive scan television system with video compression exceeding display line rate
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JPS63245569A (en) * 1987-03-31 1988-10-12 Yokogawa Medical Syst Ltd Picture display processor
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JP3013808B2 (en) * 1997-05-19 2000-02-28 日本電気株式会社 Resolution conversion method and display control device using the same
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AU8327682A (en) 1982-11-18
NL8201914A (en) 1982-12-01
IT1151396B (en) 1986-12-17
FI821562A0 (en) 1982-05-04
FR2506102B1 (en) 1988-03-04
PT74839A (en) 1982-06-01
DE3217681C2 (en) 1988-03-31
GB2100092A (en) 1982-12-15
JPS581378A (en) 1983-01-06
GB2100092B (en) 1986-05-29
IT8221180A0 (en) 1982-05-10
PT74839B (en) 1983-12-23
SE8202741L (en) 1982-11-12
ES8308465A1 (en) 1983-08-16
GB2149538A (en) 1985-06-12
GB8427953D0 (en) 1984-12-12
FI821562L (en) 1982-11-12
DE3217681A1 (en) 1982-11-25
FR2506102A1 (en) 1982-11-19
ES511906A0 (en) 1983-08-16
ZA823237B (en) 1983-05-25

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