GB945149A - Apparatus for performing arithmetic operations - Google Patents

Abstract

945,149. Electric digital calculators. UNITED AIRCRAFT CORPORATION. April 12, 1960, No. 12951/60. Heading G4A. Calculating apparatus is arranged to multiply a binary number by a binary coded decimal number and the arrangement may be modified to effect code conversion in both directions between binary and binary coded decimal form. First embodiment, Fig. 1. This is for forming the product of a binary fraction X in a register 126 with a binary coded decimal number Y in a register 10, the product, in binary coded decimal form, being produced in an accumulator 80. In each cycle of the multiplication the binary fraction X is left shifted, i.e. doubled, and the decimal number Y is right shifted and halved by a halver 36 (Fig. 2, not shown) comprising AND and OR gates employing transistors (Fig. 3, not shown); the halver being supplied with the four bits Y 1 -Y 4 in the lowest order stage 14 and the lowest bit Y 5 from the next higher stage 16 in the Y register 10, since the value of the digit halved is dependent on whether the next higher digit is odd or even. In each cycle, the contents of Y register 10 is added to the contents of the accumulator 80 in an adder 112 if the bit in the highest position of the X register 126 is a "1". If this bit is an "0" the accumulator is recirculated without modification via gate 156. Second embodiment, Fig. 4. This for converting a binary fraction to binary coded decimal form and includes the halver 36, X register 126 and Y register 10 as in Fig. 1. The X register 126 stores the binary fraction to be converted and is right shifted, the value in the least significant stage being applied via a gate 257 to the halver 36 and being effective to control the halver as if it were the least significant bit of a digit preceding the most significant decimal digit in the Y register. Third embodiment, Fig. 9 (not shown). This is for converting a binary coded decimal integer to binary form and includes the halver, X register and Y register as in Fig. 4, the decimal number in the Y register being repeatedly halved and a "1" entered in the X register each time the result is odd. Fourth embodiment, Fig. 5 (not shown). This is for multiplying a binary integer by a binary coded decimal number to give a product in binary coded decimal form. The circuit is generally similar to that of Fig. 1, but the halver 36 is replaced by a doubler (Fig. 6, not shown), the successive doubled values of the decimal number being multiplied by the respective bits of the binary integer. Fifth embodiment, Fig. 8. This is for converting a binary integer X to binary coded decimal form Y. The binary integer X is placed in the X register 126 and the Y register 10 is cycled, most significant digit first,through a doubler 260 (Fig. 7, not shown), the highest significant bit position in the X register being applied via a gate 275 to the doubler and being effective according as its value is "0" or "1" to cause the doubler 260 to regard the lowest order digit of the Y register as less than or greater than "5". Sixth embodiment, Fig. 10 (not shown). This is for converting a binary coded decimal fraction to a binary fraction, the general arrangement being similar to that of Fig. 8, with the binary fraction being built up bit-by-bit in the X register 126 which is shifted to the right.