KR20210028872A - Method for producing wafer - Google Patents

Method for producing wafer Download PDF

Info

Publication number
KR20210028872A
KR20210028872A KR1020190109951A KR20190109951A KR20210028872A KR 20210028872 A KR20210028872 A KR 20210028872A KR 1020190109951 A KR1020190109951 A KR 1020190109951A KR 20190109951 A KR20190109951 A KR 20190109951A KR 20210028872 A KR20210028872 A KR 20210028872A
Authority
KR
South Korea
Prior art keywords
wafer
present
powder
conductive material
forming
Prior art date
Application number
KR1020190109951A
Other languages
Korean (ko)
Other versions
KR102267023B1 (en
Inventor
김용화
김효중
Original Assignee
김효중
김용화
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김효중, 김용화 filed Critical 김효중
Priority to KR1020190109951A priority Critical patent/KR102267023B1/en
Publication of KR20210028872A publication Critical patent/KR20210028872A/en
Application granted granted Critical
Publication of KR102267023B1 publication Critical patent/KR102267023B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]

Abstract

The present invention relates to a wafer manufacturing method which comprises: an inserting step of inserting a conductive material into an inner space of a mold; an injection step of injecting a powder body into the inner space; a sintering step of forming a powder sintered body by sintering the powder body by applying thermal energy to the inner space; and a forming step of forming a plurality of wafers by processing the powder sintered body to a predetermined thickness. Therefore, since a process of forming a through-hole in order to fill the wafer with the conductive material is not required, the process can be greatly simplified.

Description

웨이퍼 제조 방법{METHOD FOR PRODUCING WAFER}Wafer manufacturing method {METHOD FOR PRODUCING WAFER}

본 발명은 웨이퍼 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a wafer.

TSV 기술은 실리콘 웨이퍼(Silicon Wafer)를 관통하는 미세한 관통홀(Via)을 형성한 후, 관통홀 내부에 전도성 물질(Conductive Materials)을 충전시켜 칩 내부에 직접적인 전기적 연결 통로를 확보하는 기술로, 칩 내부에 직접 연결 통로가 확보되기 때문에 다수의 칩을 수직으로 적층할 때 와이어 본딩을 이용한 3차원 패키징에서의 I/O(input/output unit) 수의 제한, 단락 접촉 불량과 같은 문제점을 해결할 수 있어, CMOS 센서, MEMS(Micro Electro-Mechanical Systems), HB-LED 모듈, Stacked Memories, Power and Analog, SIP(System In Package) 등 고밀도 첨단 전자 패키징 분야에 이용되고 있다.TSV technology is a technology to secure a direct electrical connection path inside the chip by forming a fine through hole (Via) penetrating the silicon wafer and then filling the conductive material inside the through hole. Since a direct connection path is secured inside, problems such as limitation of the number of input/output units (I/O) in 3D packaging using wire bonding and poor short-circuit contact can be solved when multiple chips are stacked vertically. , CMOS sensor, MEMS (Micro Electro-Mechanical Systems), HB-LED module, Stacked Memories, Power and Analog, and SIP (System In Package) are used in high-density advanced electronic packaging fields.

TSV 기술을 적용하여 반도체 3차원 패키징을 실시하기 위해서는 크게 웨이퍼에 관통홀(Via hole)을 형성하는 기술, 범핑(bumping) 기술, 기능성 박막층을 형성하는 기술, 전도성 물질을 충전하는 기술(Via Filling), 웨이퍼 연마 기술, 칩 적층 기술, TSV 신뢰성 해석 등 다양한 기술이 요구된다.In order to carry out semiconductor 3D packaging by applying TSV technology, the technology of forming a through hole in the wafer, bumping technology, a technology for forming a functional thin film layer, a technology for filling a conductive material (Via Filling) , Wafer polishing technology, chip stacking technology, TSV reliability analysis, etc. are required.

상술한 기술 중 전도성 물질을 충전하는 기술(Via Filling)을 실시할 때에는 여러 조건들의 설정이 필요한데, 상기 조건들 중 어느 하나 이상의 조건이 만족되지 않는 경우, 관통홀 내부에 충진되는 전도성 물질(예를 들면, Cu)의 형상에 불량이 발생하게 된다.Among the above-described techniques, when performing the technique of filling a conductive material (Via Filling), it is necessary to set various conditions. If any one or more of the above conditions are not satisfied, a conductive material filled in the through hole (e.g. For example, a defect occurs in the shape of Cu).

도 1은 종래의 TSV 기술에 따른 불량 웨이퍼의 단면을 도시한 것이고, 도 1의 (a)는 Cu 시드(Seed) 불량에 따른 웨이퍼의 단면을 도시한 것이다. 도 1의 (a)에 도시된 바와 같이, 관통홀 측면벽과 저면벽에 적절한 두께의 Cu 시드(Seed)가 형성되지 않는 경우 않을 경우, 관통홀 내부에서 Cu가 정상적으로 성장되지 않는다.FIG. 1 is a cross-sectional view of a defective wafer according to a conventional TSV technology, and FIG. 1A is a cross-sectional view of a wafer according to a Cu seed defect. As shown in (a) of FIG. 1, if Cu seeds having an appropriate thickness are not formed on the sidewalls and the bottom walls of the through-holes, Cu is not normally grown inside the through-holes.

도 1의 (b)는 전류밀도의 불충분에 따른 웨이퍼의 단면을 도시한 것이다. 도 1의 (b)에 도시된 바와 같이, 전류밀도의 조건이 불충분 한경우, 관통홀 입구부분이 충진되지 않거나, 관통홀 내부에서 Cu가 불충분하게 충진되어 내부에 보이드(Void)가 형성되는 등의 문제가 발생할 수 있다.1B shows a cross section of a wafer according to insufficient current density. As shown in (b) of FIG. 1, when the condition of the current density is insufficient, the entrance portion of the through hole is not filled, or the inside of the through hole is insufficiently filled with Cu to form a void. Problems can arise.

본 발명의 목적은 상술한 종래의 문제점을 해결하기 위한 것으로서, 관통홀의 형성 및 전도성 물질의 충진 과정 없이, 전도성 물질이 포함된 상태로 분말체를 소결하여 웨이퍼를 제조하는 방법을 제공함에 있다.An object of the present invention is to solve the above-described conventional problem, and to provide a method of manufacturing a wafer by sintering a powder body in a state containing a conductive material without forming a through hole and filling a conductive material.

상기 목적은, 본 발명에 따라, 금형의 내부공간으로 전도성 물질을 삽입하는 삽입단계; 상기 내부공간에 분말체를 주입하는 주입단계; 상기 내부공간에 열에너지를 인가하여 상기 분말체를 소결시킴으로써 분말소결체를 형성하는 소결단계; 및 상기 분말소결체를 기설정된 두께로 가공하여 복수개의 웨이퍼를 형성하는 가공단계를 포함하는 웨이퍼 제조 방법에 의해 달성된다.The object is, according to the present invention, inserting a conductive material into the inner space of the mold; An injection step of injecting a powder body into the inner space; A sintering step of forming a powder sintered body by sintering the powder body by applying thermal energy to the inner space; And a processing step of forming a plurality of wafers by processing the powder sintered body to a predetermined thickness.

또한, 상기 분말체는, 유리(Glass) 분말일 수 있다.In addition, the powder body may be a glass (Glass) powder.

또한, 상기 전도성 물질은, 구리(Cu)로 마련될 수 있다.In addition, the conductive material may be made of copper (Cu).

또한, 상기 금형은, 복수개의 상기 전도성 물질이 상기 내부공간으로 인입될 수 있도록 일측면에 복수개의 인입홀을 형성할 수 있다.In addition, the mold may have a plurality of lead-in holes formed on one side of the mold so that the plurality of conductive materials can be introduced into the inner space.

상기 목적은, 본 발명에 따라, 상기 웨이퍼 제조 방법으로 제조되는 웨이퍼에 의해 달성된다.The above object is achieved, according to the present invention, by a wafer manufactured by the above wafer manufacturing method.

본 발명에 따르면, 웨이퍼에 전도성 물질을 충진하기 위해 관통홀을 형성하는 과정이 필요없게 되어 공정이 대폭적으로 간소화될 수 있다.According to the present invention, a process of forming a through hole in order to fill a wafer with a conductive material is not required, so that the process can be greatly simplified.

또한, 본 발명에 따르면, 종래에 관통홀 내부에 전도성 물질을 충진하는 과정이 필요없게 되어 공정이 대폭적으로 간소화 될 수 있을 뿐만 아니라, 전도성 물질이 관통홀에 불완전하게 충진되는 문제점이 원천적으로 차단되므로 웨이퍼의 불량율이 크게 감소될 수 있다.In addition, according to the present invention, the conventional process of filling the conductive material inside the through hole is not required, so that the process can be greatly simplified, and the problem of incompletely filling the through hole with the conductive material is fundamentally blocked. The defect rate of the wafer can be greatly reduced.

또한, 본 발명에 따르면, 유리를 이용하여 웨이퍼를 용이하게 제조 할 수 있다. 유리로 웨이퍼를 제조하는 경우, 열전도율이 크게 개선될 수 있고, 이에 따르면, 웨이퍼를 이용하여 제조된 칩 내부에서 발생되는 열이 효과적으로 배출되어 칩 성능이 개선되고 수명이 향상될 수 있다.Further, according to the present invention, a wafer can be easily manufactured using glass. In the case of manufacturing a wafer with glass, thermal conductivity can be greatly improved, and accordingly, heat generated inside a chip manufactured using the wafer can be effectively discharged, thereby improving chip performance and improving lifespan.

한편, 본 발명의 효과는 이상에서 언급한 효과들로 제한되지 않으며, 이하에서 설명할 내용으로부터 통상의 기술자에게 자명한 범위 내에서 다양한 효과들이 포함될 수 있다.Meanwhile, the effects of the present invention are not limited to the above-mentioned effects, and various effects may be included within a range that is apparent to a person skilled in the art from the contents to be described below.

도 1은 종래의 TSV 기술에 따른 불량 웨이퍼의 단면을 도시한 것이고,
도 2는 본 발명의 일실시예에 따른 웨이퍼 제조 방법의 순서도 이고,
도 3은 본 발명의 일실시예에 따른 웨이퍼 제조 방법의 삽입단계를 도시한 것이고,
도 4는 본 발명의 일실시예에 따른 웨이퍼 제조 방법의 주입단계를 도시한 것이고,
도 5는 본 발명의 일실시예에 따른 웨이퍼 제조 방법의 소결단계 이후, 금형을 분리하는 것을 도시한 것이고,
도 6은 본 발명의 일실시예에 따른 웨이퍼 제조 방법의 가공단계를 도시한 것이고,
도 7은 본 발명의 일실시예에 따른 웨이퍼 제조 방법에 따른 웨이퍼의 단면을 도시한 것이다.1 is a cross-sectional view of a defective wafer according to a conventional TSV technology,
2 is a flow chart of a wafer manufacturing method according to an embodiment of the present invention,
3 is a diagram showing the insertion step of the wafer manufacturing method according to an embodiment of the present invention,
4 is a diagram showing an implantation step of a method for manufacturing a wafer according to an embodiment of the present invention,
5 is a diagram showing separation of the mold after the sintering step of the wafer manufacturing method according to an embodiment of the present invention,
6 shows a processing step of the wafer manufacturing method according to an embodiment of the present invention,
7 is a cross-sectional view of a wafer according to a method of manufacturing a wafer according to an embodiment of the present invention.

이하, 본 발명의 일부 실시 예들이 예시적인 도면을 통해 상세하게 설명한다. 각 도면의 구성요소들에 참조부호를 부가함에 있어서, 동일한 구성요소들에 대해서는 비록 다른 도면상에 표시되더라도 가능한 한 동일한 부호를 가지도록 하고 있음에 유의해야한다.Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to elements of each drawing, it should be noted that the same elements are assigned the same numerals as possible, even if they are indicated on different drawings.

그리고 본 발명의 실시 예를 설명함에 있어, 관련된 공지 구성 또는 기능에 대한 구체적인 설명이 본 발명의 실시예에 대한 이해를 방해한다고 판단되는 경우에는 그 상세한 설명은 생략한다.Further, in describing an embodiment of the present invention, if it is determined that a detailed description of a related known configuration or function interferes with the understanding of the embodiment of the present invention, a detailed description thereof will be omitted.

또한, 본 발명의 실시 예의 구성요소를 설명하는 데 있어서, 제1, 제2, A, B, (a), (b) 등의 용어를 사용할 수 있다. 이러한 용어는 그 구성 요소를 다른 구성 요소와 구별하기 위한 것일 뿐, 그 용어에 의해 해당 구성 요소의 본질이나 차례 또는 순서 등이 한정되지 않는다.In addition, terms such as first, second, A, B, (a), (b) may be used in describing the constituent elements of the embodiment of the present invention. These terms are for distinguishing the constituent element from other constituent elements, and the nature, order, or order of the constituent element is not limited by the term.

지금부터 첨부한 도면을 참조하여 본 발명의 일실시예에 따른 웨이퍼 제조 방법에 대해서 상세히 설명한다.Hereinafter, a method of manufacturing a wafer according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 일실시예에 따른 웨이퍼 제조 방법의 순서도 이고, 도 3은 본 발명의 일실시예에 따른 웨이퍼 제조 방법의 삽입단계를 도시한 것이고, 도 4는 본 발명의 일실시예에 따른 웨이퍼 제조 방법의 주입단계를 도시한 것이고, 도 5는 본 발명의 일실시예에 따른 웨이퍼 제조 방법의 소결단계 이후, 금형을 분리하는 것을 도시한 것이고, 도 6은 본 발명의 일실시예에 따른 웨이퍼 제조 방법의 가공단계를 도시한 것이고, 도 7은 본 발명의 일실시예에 따른 웨이퍼 제조 방법에 따른 웨이퍼의 단면을 도시한 것이다.Figure 2 is a flow chart of a wafer manufacturing method according to an embodiment of the present invention, Figure 3 is a diagram showing the insertion step of the wafer manufacturing method according to an embodiment of the present invention, Figure 4 is an embodiment of the present invention. Figure 5 shows the separation of the mold after the sintering step of the wafer manufacturing method according to an embodiment of the present invention, and Figure 6 shows an embodiment of the present invention. It shows the processing steps of the wafer manufacturing method according to this, and Figure 7 shows a cross-section of a wafer according to the wafer manufacturing method according to an embodiment of the present invention.

도 2에 도시된 바와 같이, 본 발명의 일실시예에 따른 웨이퍼 제조 방법(S100)은 삽입단계(S110)와, 주입단계(S120)와, 소결단계(S130)와, 가공단계(S140)를 포함한다.As shown in Figure 2, the wafer manufacturing method (S100) according to an embodiment of the present invention includes an insertion step (S110), an implantation step (S120), a sintering step (S130), and a processing step (S140). Includes.

삽입단계(S110)는 도 3에 도시된 바와 같이, 금형(20)의 내부공간(s)으로 전도성 물질(c)을 삽입하는 단계이다. 여기서, 금형(20)은 각면이 분리가능한 육면체 형태로 마련될 수 있는데, 일측면 및 타측면에는 기둥형상의 전도성 물질(c)이 금형(20)의 내부공간(s)으로 삽입된 이후, 관통될 수 있도록 복수개의 인입홀(h)이 형성된다.The inserting step (S110) is a step of inserting the conductive material (c) into the inner space (s) of the mold 20, as shown in FIG. 3. Here, the mold 20 may be provided in the form of a hexahedron that can be separated on each side. After the columnar conductive material (c) is inserted into the inner space (s) of the mold 20 on one side and the other side, through A plurality of inlet holes (h) are formed to be able to be.

한편, 전도성 물질(c, Conductive Materials)은 구리(Cu), 주석(Sn), 은(Ag) 등으로 마련될 수 있고, 원형 기둥 또는 사각형 기둥 등의 형상으로 마련될 수 있다.Meanwhile, the conductive material (c) may be made of copper (Cu), tin (Sn), silver (Ag), or the like, and may be provided in a shape such as a circular pillar or a square pillar.

주입단계(S120)는 도 4에 도시된 바와 같이, 상술한 삽입단계(S110) 이후, 금형(20)의 내부공간(s)에 분말체를 주입하는 단계이다. 여기서, 분말체는 유리(Glass) 분말, 실리콘(Si) 분말 등으로 마련될 수 있다. 분말체가 유리 분말로 마련되는 경우, 유리 기반의 웨이퍼가 형성되며, 실리콘 분말로 마련되는 경우, 실리콘 기반의 웨이퍼가 형성된다.The injection step (S120) is a step of injecting the powder into the inner space (s) of the mold 20, after the above-described insertion step (S110), as shown in FIG. 4. Here, the powder body may be formed of glass powder, silicon (Si) powder, or the like. When the powder is formed of glass powder, a glass-based wafer is formed, and when the powder is formed of silicon powder, a silicon-based wafer is formed.

소결단계(S130)는 상술한 주입단계(S120) 이후, 금형(20)의 내부공간(s)에 열에너지를 인가하여 분말체를 소결시킴으로써 분말소결체(m)를 형성하는 단계이다.The sintering step (S130) is a step of forming a powder sintered body (m) by sintering the powder body by applying thermal energy to the inner space (s) of the mold 20 after the injection step (S120) described above.

열에너지 인가를 위한 가열 온도는 분말체가 소결될 수 있는 온도 인데, 이 온도는 전도성 물질(c)의 녹는점 보다 더 낮은 온도로 설정되는 것이 바람직하다.The heating temperature for applying thermal energy is a temperature at which the powder can be sintered, and this temperature is preferably set to a temperature lower than the melting point of the conductive material (c).

소결단계(S130)에 따라 형성된 분말소결체(m)는 후술하는 가공단계(S140)에 의해서 가공되는데, 분말소결체(m)를 가공하기 위해서는 소결단계(S130) 이후, 도 5에 도시된 바와 같이, 금형(20)의 각면을 분리하는 과정이 수반되어야 한다.The powder sintered body (m) formed according to the sintering step (S130) is processed by the processing step (S140) to be described later.In order to process the powder sintered body (m), after the sintering step (S130), as shown in FIG.5, The process of separating each surface of the mold 20 must be accompanied.

가공단계(S140)는 도 6에 도시된 바와 같이, 소결단계(S130)에 따라 형성된 분말소결체(m)를 기설정된 두께로 가공하여 복수개의 웨이퍼를 형성하는 단계이다.The processing step (S140) is a step of forming a plurality of wafers by processing the sintered powder (m) formed according to the sintering step (S130) to a predetermined thickness, as shown in FIG. 6.

한편, 가공단계(S140) 이후, 생성된 웨이퍼(w)는 별도의 연마과정을 통해 두께가 조절될 수 있다. Meanwhile, after the processing step S140, the thickness of the generated wafer w may be adjusted through a separate polishing process.

상술한 바와 같은 가공단계(S140)에 따르면, 도 7에 도시된 바와 같이, 내부에 전도성 물질(c)이 균일한 간격으로 개재되는 형태의 웨이퍼(w)가 형성된다.According to the processing step S140 as described above, as shown in FIG. 7, a wafer w having a conductive material c interposed therein at uniform intervals is formed.

상술한 바와 같은 삽입단계(S110)와, 주입단계(S120)와, 소결단계(S130)와, 가공단계(S140)를 포함하는 본 발명의 일실시예에 따른 웨이퍼 제조 방법(S100)에 따르면, 웨이퍼에 관통홀을 형성하는 과정 및 관통홀에 전도성 물질(c)을 충진하는 과정이 필요없게 되어 공정이 대폭적으로 간소화될 수 있다.According to the wafer manufacturing method (S100) according to an embodiment of the present invention including the insertion step (S110), implantation step (S120), sintering step (S130), and processing step (S140) as described above, The process of forming the through hole in the wafer and the process of filling the through hole with the conductive material c are not required, so that the process can be greatly simplified.

또한, 본 발명의 일실시예에 따른 웨이퍼 제조 방법(S100)에 따르면, 전도성 물질(c)이 관통홀에 불완전하게 충진되는 문제점이 원천적으로 차단되므로 웨이퍼의 불량율이 크게 감소될 수 있다.In addition, according to the wafer manufacturing method S100 according to an embodiment of the present invention, since the problem that the conductive material c is incompletely filled in the through hole is fundamentally blocked, the defect rate of the wafer can be greatly reduced.

또한, 본 발명의 일실시예에 따른 웨이퍼 제조 방법(S100)에 따르면, 유리를 이용하여 웨이퍼를 용이하게 제조 할 수 있다. 유리로 웨이퍼를 제조하는 경우, 열전도율이 크게 개선될 수 있고, 이에 따르면, 웨이퍼를 이용하여 제조된 칩 내부에서 발생되는 열이 효과적으로 배출되어 칩 성능이 개선되고 수명이 향상될 수 있다.In addition, according to the wafer manufacturing method (S100) according to an embodiment of the present invention, it is possible to easily manufacture a wafer using glass. In the case of manufacturing a wafer with glass, thermal conductivity can be greatly improved, and accordingly, heat generated inside a chip manufactured using the wafer can be effectively discharged, thereby improving chip performance and improving lifespan.

이상에서, 본 발명의 실시 예를 구성하는 모든 구성 요소들이 하나로 결합하거나 결합하여 동작하는 것으로 설명되었다고 해서, 본 발명이 반드시 이러한 실시 예에 한정되는 것은 아니다. 즉, 본 발명의 목적 범위 안에서라면, 그 모든 구성요소들이 하나 이상으로 선택적으로 결합하여 동작할 수도 있다.In the above, even if all the constituent elements constituting the embodiments of the present invention have been described as being combined into one or operating in combination, the present invention is not necessarily limited to these embodiments. That is, as long as it is within the scope of the object of the present invention, one or more of the components may be selectively combined and operated.

또한, 이상에서 기재된 "포함하다", "구성하다" 또는 "가지다" 등의 용어는, 특별히 반대되는 기재가 없는 한, 해당 구성 요소가 내재할 수 있음을 의미하는 것이므로, 다른 구성 요소를 제외하는 것이 아니라 다른 구성 요소를 더 포함할 수 있는 것으로 해석되어야 한다. 기술적이거나 과학적인 용어를 포함한 모든 용어들은, 다르게 정의되지 않는 한, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미가 있다. 사전에 정의된 용어와 같이 일반적으로 사용되는 용어들은 관련 기술의 문맥상의 의미와 일치하는 것으로 해석 되어야 하며, 본 발명에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않는다.In addition, terms such as "include", "consist of" or "have" described above mean that the corresponding component may be present unless otherwise stated, excluding other components. It should not be construed as being able to further include other components. All terms, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art, unless otherwise defined. Terms generally used, such as terms defined in the dictionary, should be interpreted as being consistent with the meaning of the context of the related technology, and are not interpreted as ideal or excessively formal meanings unless explicitly defined in the present invention.

그리고 이상의 설명은 본 발명의 기술 사상을 예시적으로 설명한 것에 불과한 것으로서, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자라면 본 발명의 본질적인 특성에서 벗어나지 않는 범위에서 다양한 수정 및 변형이 가능할 것이다.In addition, the above description is merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains will be able to make various modifications and variations without departing from the essential characteristics of the present invention.

따라서, 본 발명에 개시된 실시예들은 본 발명의 기술 사상을 한정하기 위한 것이 아니라 설명하기 위한 것이고, 이러한 실시예에 의하여 본 발명의 기술 사상의 범위가 한정되는 것은 아니다. 본 발명의 보호 범위는 아래의 청구범위에 의하여 해석되어야 하며, 그와 동등한 범위 내에 있는 모든 기술 사상은 본 발명의 권리범위에 포함되는 것으로 해석되어야 할 것이다.Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the claims below, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

10 : 종래의 실리콘 웨이퍼
S100 : 본 발명의 일실시예에 따른 웨이퍼 제조 방법
S110 : 삽입단계
S120 : 주입단계
S130 : 소결단계
S140 : 가공단계
20 : 금형
c : 전도성 물질
s : 내부공간
h : 인입홀
m : 분말소결체
w : 본 발명의 일실시예에 따른 웨이퍼 제조 방법에 따라 제조되는 웨이퍼10: conventional silicon wafer
S100: Wafer manufacturing method according to an embodiment of the present invention
S110: Insertion step
S120: injection step
S130: Sintering step
S140: processing step
20: mold
c: conductive material
s: internal space
h: entry hole
m: powder sintered body
w: Wafer manufactured according to the wafer manufacturing method according to an embodiment of the present invention

Claims (5)

금형의 내부공간으로 전도성 물질을 삽입하는 삽입단계;
상기 내부공간에 분말체를 주입하는 주입단계;
상기 내부공간에 열에너지를 인가하여 상기 분말체를 소결시킴으로써 분말소결체를 형성하는 소결단계; 및
상기 분말소결체를 기설정된 두께로 가공하여 복수개의 웨이퍼를 형성하는 가공단계를 포함하는 웨이퍼 제조 방법.Inserting a conductive material into the inner space of the mold;
An injection step of injecting a powder body into the inner space;
A sintering step of forming a powder sintered body by sintering the powder body by applying thermal energy to the inner space; And
A wafer manufacturing method comprising a processing step of forming a plurality of wafers by processing the powder sintered body to a predetermined thickness. 청구항 1에 있어서,
상기 분말체는,
유리(Glass) 분말인 것을 특징으로 하는 웨이퍼 제조 방법.The method according to claim 1,
The powder body,
Wafer manufacturing method, characterized in that the glass (Glass) powder. 청구항 1에 있어서,
상기 전도성 물질은,
구리(Cu)로 마련되는 것을 특징으로 하는 웨이퍼 제조 방법.The method according to claim 1,
The conductive material,
Wafer manufacturing method, characterized in that provided with copper (Cu). 청구항 1에 있어서,
상기 금형은,
복수개의 상기 전도성 물질이 상기 내부공간으로 인입될 수 있도록 일측면에 복수개의 인입홀을 형성하는 것을 특징으로 하는 웨이퍼 제조 방법.The method according to claim 1,
The mold is
A method of manufacturing a wafer, comprising forming a plurality of lead holes on one side of the conductive material so that the plurality of conductive materials can be introduced into the inner space. 청구항 1 내지 청구항 4 중 어느 하나의 청구항에 따른 웨이퍼 제조 방법으로 제조되는 웨이퍼.A wafer manufactured by the wafer manufacturing method according to any one of claims 1 to 4.
KR1020190109951A 2019-09-05 2019-09-05 Method for producing wafer KR102267023B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020190109951A KR102267023B1 (en) 2019-09-05 2019-09-05 Method for producing wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190109951A KR102267023B1 (en) 2019-09-05 2019-09-05 Method for producing wafer

Publications (2)

Publication Number Publication Date
KR20210028872A true KR20210028872A (en) 2021-03-15
KR102267023B1 KR102267023B1 (en) 2021-06-18

Family

ID=75134639

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020190109951A KR102267023B1 (en) 2019-09-05 2019-09-05 Method for producing wafer

Country Status (1)

Country Link
KR (1) KR102267023B1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0185462B1 (en) * 1994-07-01 1999-03-20 이노우에 사다오 Sintered body for and manufacture of ceramic substrates
KR100770168B1 (en) * 2006-09-20 2007-10-26 삼성전기주식회사 Fabricating method for circuit board
KR20180130192A (en) * 2017-05-29 2018-12-07 주식회사 월덱스 Silicon nitride substrate without planarization and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0185462B1 (en) * 1994-07-01 1999-03-20 이노우에 사다오 Sintered body for and manufacture of ceramic substrates
KR100770168B1 (en) * 2006-09-20 2007-10-26 삼성전기주식회사 Fabricating method for circuit board
KR20180130192A (en) * 2017-05-29 2018-12-07 주식회사 월덱스 Silicon nitride substrate without planarization and method of manufacturing the same

Also Published As

Publication number Publication date
KR102267023B1 (en) 2021-06-18

Similar Documents

Publication Publication Date Title
CN106057756B (en) Semiconductor structure and its manufacturing method
US20150311188A1 (en) Methods of Fabrication and Testing of Three-Dimensional Stacked Integrated Circuit System-In-Package
KR101996153B1 (en) Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
KR101963984B1 (en) Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems
JP5621155B2 (en) Method for vertically interconnecting 3D electronic modules by vias
US8729711B2 (en) Semiconductor device
KR101996154B1 (en) Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems
KR101996161B1 (en) Semiconductor device assembly with underfill containment cavity
US9620433B2 (en) Packaged microelectronic elements having blind vias for heat dissipation
US9543245B2 (en) Semiconductor sensor device and method of producing a semiconductor sensor device
TWI546927B (en) Reconstitution techniques for semiconductor packages
KR20150012626A (en) Stack package and method of fabricating the same
US8633572B2 (en) Low ohmic through substrate interconnection for semiconductor carriers
EP3089211A1 (en) Moisture-resistant electronic component and method for packaging an electronic circuit for manufacturing such a component
US9003654B2 (en) Method for metalizing blind vias
KR102267023B1 (en) Method for producing wafer
CN107924977A (en) For manufacturing the method and device of device
KR100608611B1 (en) Wafer level chip scale package using via hole and manufacturing method for the same
JP2006201158A (en) Sensor
US9237650B2 (en) Forming of an electric connection of the via type
JP7354513B2 (en) Electronic circuit device and its manufacturing method
KR102397140B1 (en) A method of fabricating a semiconductor structure comprising an interposer without any through-vias
TWI802932B (en) Semiconductor structure and manufacturing method thereof
CN112470269B (en) Semiconductor device with through substrate via
JP2011151138A (en) Manufacturing method for semiconductor device

Legal Events

Date Code Title Description
E701 Decision to grant or registration of patent right
GRNT Written decision to grant