KR20130123268A - Chuck spacing mask for reducing contacting area to wafer and manufacturing method thereof - Google Patents

Chuck spacing mask for reducing contacting area to wafer and manufacturing method thereof Download PDF

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Publication number
KR20130123268A
KR20130123268A KR1020120046587A KR20120046587A KR20130123268A KR 20130123268 A KR20130123268 A KR 20130123268A KR 1020120046587 A KR1020120046587 A KR 1020120046587A KR 20120046587 A KR20120046587 A KR 20120046587A KR 20130123268 A KR20130123268 A KR 20130123268A
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KR
South Korea
Prior art keywords
wafer
support
chuck
mask
present
Prior art date
Application number
KR1020120046587A
Other languages
Korean (ko)
Inventor
강승동
Original Assignee
(주)씨엠코리아
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Application filed by (주)씨엠코리아 filed Critical (주)씨엠코리아
Priority to KR1020120046587A priority Critical patent/KR20130123268A/en
Publication of KR20130123268A publication Critical patent/KR20130123268A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02N—ELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
    • H02N13/00—Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect

Abstract

The present invention relates to a spacing mask of a support chuck for reducing the contact area to a wafer and a manufacturing method thereof. The spacing mask formed using TiC or ZrN, on which support members are formed, maintains a wafer or different parts while being separated from the support surface of a chuck. According to the spacing mask, the spacing mask prevents contaminated particles from touching the bottom of the wafer during a process, easily washes the surfaces of the support members which touch the wafer, and binds most of the particles to the space between the support members.

Description

Chuck spacing mask for reducing contacting area to wafer and manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spaced-apart mask having a reduced contact area with respect to a wafer of a support chuck and a method of manufacturing the same. It is about.

In the semiconductor manufacturing apparatus, an electrostatic chuck is a device for supporting and fixing a wafer in a semiconductor manufacturing process, a glass in an LCD manufacturing process, and the like. A vacuum chuck or the like for fixing the same was used.

However, in the low pressure process, the vacuum chuck using the pressure difference cannot be used. Recently, an electrostatic chuck is used to fix the substrate using electrostatic force. Such an electrostatic chuck is also advantageous in high temperature processes such as plasma deposition and etching.

Many techniques related to such electrostatic chucks have been disclosed.

Patent registration No. 10-1115527 is a structure and material related technology of the electrostatic chuck, an aluminum body layer having an oxide film layer formed on the surface; An electrode layer made of aluminum coupled on the body layer and having an oxide film layer formed on a surface thereof; And a dielectric layer formed by thermally spraying aluminum oxide on the electrode layer.

In addition, Patent Registration No. 10-1071248 relates to a method for manufacturing an electrostatic chuck, the step of forming a nickel-aluminum layer on one surface of the base; Forming a first ceramic layer by aerosol deposition on the nickel-aluminum layer; Forming a second ceramic layer on the first ceramic layer by an air spray method; Forming a tungsten layer over the second ceramic layer; And forming a third ceramic layer on the tungsten layer by the thermal spraying method in the air.

In electrostatic chucks used in semiconductor manufacturing processes, in particular substrate support electrostatic chucks used in low temperature processes generate contaminating particles that interfere with wafer processing. These low temperature chucks are made of non-electrical materials such as alumina to form electrostatic chucks and mechanical clamping chucks with wafer support surfaces. It can be seen that chucks of this type also generate contaminating particles that can adhere to the bottom of the wafer during the process.

Therefore, the electrostatic chuck of the semiconductor manufacturing apparatus is required in terms of improving the semiconductor manufacturing efficiency to reduce the amount of contaminant particles that adhere to the bottom of the wafer while being supported by the chuck.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and an object of the present invention is to provide an electrostatic chuck having a wafer minimum contact area mask for supporting a wafer in a spaced space relative to the support chuck.

Another object of the present invention is to provide a wafer minimum contact area mask formed in the form of a plurality of support members on the support surface of the chuck is made of a material different from the material of the chuck, so that the mask material is less worn, but excellent contact characteristics with respect to the wafer compared to the chuck surface material. It is to provide an electrostatic chuck to have.

Mask manufacturing method that reduces the wafer contact area for the support chuck of the present invention for achieving the above object. A spacing mask deposited on the support surface is formed to support the wafer in the spaced apart state from the support surface, and the spacing mask is made of a metallic material.

The metallic material of the wafer spacing mask of the present invention is characterized by being TiC or ZrN.

The support surface of the electrostatic chuck on which the wafer spacing mask of the present invention is formed is made of a ceramic material.

The spacing mask of the present invention is characterized in that a supporting member for forming a pattern is formed.

The support chuck on which the wafer spacing mask of the present invention is formed includes a plurality of electrodes formed under the support surface, and the support member is formed between the support surface and the plurality of electrodes, and the plurality of electrodes do not overlap. .

The pattern formed on the wafer spacing mask of the present invention is characterized by being formed in a plurality of pads.

The spacing mask, i.e., the support members, formed of the TiC or ZrN material of the present invention serves to hold the wafer or other component away from the support surface of the chuck. Thus, the distance between the lower surface of the wafer and the chuck is determined by the thickness of the support member. This distance should be greater than the diameter of the contaminants that may be on the surface of the chuck. According to the wafer spacing mask made of the material of the present invention, contaminants do not stick to the bottom of the wafer during the process. It is also easy to clean the surface of the support member that the wafer contacts, and most of the particles are removed from these surfaces and bound to the space between the support members.

In an embodiment of the invention, the wafer spacing mask is manufactured by a method of forming a metallic support member in a ceramic chuck, for example, by a PVD process. The spacing mask may also be deposited via CVD, such as plasma spray precipitation, brazing, flame spray precipitation, or the like. The support members are deposited in a predetermined pattern such as a plurality of spaced pads, radial strips, concentric rings, or a combination of radial strips and concentric rings.

The mask, which reduces the wafer contact area for the support chuck of the present invention, can significantly reduce the number of contaminant particles adhered to the bottom of the wafer during the semiconductor wafer process, thereby improving semiconductor manufacturing efficiency.

The mask with reduced wafer contact area for the support chuck according to the present invention can significantly reduce wafer defects that may occur during the semiconductor manufacturing process while preventing a decrease in the wafer clamping force holding the wafer on the support chuck.

1 shows a mask layout with a plurality of co-centered rings and a strip extending radially internally connected to the ring, showing a mask pattern formed as a plurality of spaced spaced pads of deposited material.
FIG. 2 is an overall longitudinal cross-sectional view of a ceramic electrostatic chuck in accordance with an embodiment of the present invention and a spacing mask formed on a support surface thereof to support a semiconductor wafer; FIG.
3 illustrates various examples of the electrostatic chuck of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 shows a mask layout with a plurality of co-centered rings and a strip extending radially internally connected to the ring, illustrating a mask pattern formed as a plurality of spaced spaced pads of deposited material.

FIG. 2 is an overall longitudinal cross-sectional view including a ceramic electrostatic chuck 10 and a spacing mask 50 formed on a support surface 11 to support a semiconductor wafer 30 according to an embodiment of the present invention.

In a preferred embodiment of the present invention, for example, the electrostatic chuck 10 made of ceramic material consists of one or more electrodes 90 coupled to the electrostatic chuck body 100. The support chuck made of ceramic material is made of aluminum nitride or boron nitride, for example.

The spacing mask 50 having reduced wafer contact area of the present invention is formed on the support surface 11 of the support chuck body 100 through a PVD process with a metallic material such as TiC or ZrN.

This material may also be precipitated by a CVD process such as plasma spray precipitation brazing or flame spray precipitation.

The mask material made of a metallic material such as TiC or ZrN according to the present invention has excellent contact characteristics with respect to the wafer compared to the surface material of the chuck, that is, the ceramic material. In addition, the mask material of the present invention has less wear compared to the surface material of the ceramic support chuck, thereby reducing particle generation while having good durability. Titanium alloys have high strength / specific gravity, high corrosion resistance and relatively high temperature characteristics compared to other metals.

In the present invention, the physical vapor deposition method has the possibility of interfacial separation or interfacial fracture between the base material and the coating layer, and the ion implantation method is complicated and expensive. Precipitates by the same CVD process. The present invention, for example, by reacting at a temperature range of 800 ~ 950 ℃ of a hydrocarbon gas atmosphere to form a hard titanium carbide layer on the surface, the product is formed by heat treatment in a vacuum atmosphere to remove impurities.

Zirconium nitride, which is used as a spacing mask material in the chuck of the present invention, has a fire-resistant property. The zirconium nitride film deposition may form, for example, plasma-enhanced chemical vapor deposition (Plasma-Enhanced CVD) at a temperature of 100 to 500 ° C.

The mask formed of a material such as TiC or ZrN according to the present invention does not contact the surface of the wafer 200 on which the particles 55 on the support surface 11 of the support chuck are placed thereon. Precipitates to a predetermined thickness to maintain.

Since the support members 70 formed in the mask of the present invention are metallic, they can be easily cleaned to immediately remove contamination. Therefore, contamination by the particles is limited in the space 80 between the support member 70.

In Figure 1, the ring 300 is spaced apart at regular intervals. These rings 300 or radially extending strips 400 may be used separately from the mask.

An important feature of the invention is a metallic material which allows the wafer to be supported spaced apart from the surface of the support chuck by a spacing mask and the mask has a contact property different from that of the support chuck material so that the material on the support chuck surface does not contact the bottom of the wafer. It is manufactured as.

Thus, the specific mask pattern and mask material are determined by the particular application of the chuck, including elements such as chucking voltage, chucking force, wafer thickness, chuck electrode pattern, specific process, etc., to which the wafer is affected.

1 and 2, the portion described as the supporting member 70 is formed of a plurality of pads 70 around the ring 300 and the radial strip 400.

These pads preferably have the smallest diameter possible and, in the present invention, have a diameter of approximately 0.1 cm.

Forming the pads 70 in the present invention to have a small diameter as small as possible is a method that can prevent defects such as scratches and damage to the lower portion of the semiconductor wafer.

In general, the number, spacing and size of the pads 70 is determined by the clamping force supplied by the support chuck. For example, if the clamping force is high and the pads 70 are relatively spaced apart, the wafer 200 will be located between these pads 70.

On the other hand, if there are too many pads 70 on the support surface 11 of the support chuck 10, it will interfere with the electrostatic field that promotes the clamping force. Thus, the pads 70 should be in a suitable position to optimize the support member 70 such that interference with the clamping force is limited.

Since the support chuck made of ceramic material is semiconductorized at a high temperature (eg, 300 ° C. or higher), the conductive pads 70 may not exist at a position independent of the electrode 90.

In order to generate the clamping force, a current must be supplied from the wafer 200 to the support chuck 10. However, this current is kept at a relatively low value to prevent wafer damage. As a result, the pads 70 are generally located between the positions of the electrode 90 to avoid being within the highest electrostatic field, thus providing a cause for a significant amount of current to flow through the wafer at the mask and wafer contact points.

1 and 2, the electrode structure will include holes (not shown) that are intensively aligned with the mask pad 70. The diameter of each hole should be slightly larger than the diameter of the corresponding pad 70. In addition, the size of the contact area between the mask 50 and the wafer 200 also plays a role in reducing the current flow through the wafer 200.

On the other hand, at low temperatures (eg 300 ° C. or lower), the support chuck 10 comes into contact with a smaller amount of current so that the support members 70 can be positioned anywhere on the support surface 11 of the support chuck 10. Can be. The support members should be evenly distributed over the entire surface of the chuck so that it can adequately and uniformly support the wafer on the chuck that can contact the bottom of the wafer without the mask.

Although the present invention has been described with reference to specific embodiments, it should be understood that modifications and variations are possible without departing from the spirit and scope of the present invention.

That is, although specific embodiments of the present invention relate to ceramic electrostatic chucks, the present invention is also usefully applied to techniques for supporting substrates on chucks, such as non-ceramic electrostatic chucks, mechanical clamping chucks, and the like.

10: electrostatic chuck 11: chuck support surface
50 wafer spacing mask 55 particle
70: support member (pad) 80: space
90 electrode 100 electrostatic chuck body
200: wafer 300: ring
400: strip 500: mask layout

Claims (7)

In order to support the wafer 200 in a state spaced apart from the support surface 11 of the support chuck 10, a spacing mask 50 deposited on the support surface 11 is formed, and the spacing mask 50 is metallic. A method of manufacturing spaced masks with reduced wafer contact area to a support chuck, characterized in that it is made of a material. The method of claim 1, wherein the metallic material is TiC or ZrN. The method of claim 1, wherein the support surface is made of ceramic material. 2. The method of claim 1, wherein the spacing mask (50) is formed with a support member (70) forming a pattern. The support chuck 10 of claim 1, wherein the support chuck 10 includes a plurality of electrodes 90 formed under the support surface 11, and the support member 70 includes a support surface 11 and a plurality of electrodes 90. A method of manufacturing a spaced mask formed therebetween, wherein the plurality of electrodes do not overlap, reducing the wafer contact area for the support chuck. 2. The method of claim 1, wherein the pattern is formed in the form of a plurality of pads (70). A spaced space mask with reduced wafer contact area for a support chuck, characterized in that it is made according to claim 1.
KR1020120046587A 2012-05-02 2012-05-02 Chuck spacing mask for reducing contacting area to wafer and manufacturing method thereof KR20130123268A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020120046587A KR20130123268A (en) 2012-05-02 2012-05-02 Chuck spacing mask for reducing contacting area to wafer and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120046587A KR20130123268A (en) 2012-05-02 2012-05-02 Chuck spacing mask for reducing contacting area to wafer and manufacturing method thereof

Publications (1)

Publication Number Publication Date
KR20130123268A true KR20130123268A (en) 2013-11-12

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Country Status (1)

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Effective date: 20140627