KR20120033440A - On die termination circuit - Google Patents

On die termination circuit

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Publication number
KR20120033440A
KR20120033440A KR1020100094950A KR20100094950A KR20120033440A KR 20120033440 A KR20120033440 A KR 20120033440A KR 1020100094950 A KR1020100094950 A KR 1020100094950A KR 20100094950 A KR20100094950 A KR 20100094950A KR 20120033440 A KR20120033440 A KR 20120033440A
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KR
South Korea
Prior art keywords
pull
driver
resistor
output
termination circuit
Prior art date
Application number
KR1020100094950A
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Korean (ko)
Inventor
김기호
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100094950A priority Critical patent/KR20120033440A/en
Publication of KR20120033440A publication Critical patent/KR20120033440A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an on die termination circuit of a semiconductor device, and more particularly to an on die termination circuit capable of compensating for resistance mismatches caused by parasitic resistance components.
The present invention includes one or more pull-up output blocks including a pull-up resistor and a pull-up switch for adjusting the pull-up resistor, and the pull-up driver for controlling the one or more pull-up output blocks according to a pull-up control signal and outputting output data to an input / output pad. And a pull-down output block including a pull-down switch configured to control a pull-down resistor and a pull-down resistor, and a pull-down driver for controlling the one or more pull-down output blocks according to a pull-down control signal and outputting output data to an input / output pad. And a pull-up current control driver disposed between the power supply voltage and the pull-down current control driver disposed between the pull-down driver and the ground voltage.
Accordingly, the present invention includes a pull-up current control driver and a pull-down current control driver between the pull-up driver and the power supply voltage, thereby compensating for the resistance mismatch by parasitic resistance components.

Description

ON DIE TERMINATION CIRCUIT}

The present invention relates to an on die termination circuit of a semiconductor device, and more particularly, to an on die termination circuit capable of compensating for resistance mismatches caused by parasitic resistance components.

Various semiconductor devices, typically implemented as integrated circuit chips such as central processing units, memory and gate arrays, are incorporated into various electrical products such as personal computers, servers, workstations, and the like. Used. As the operation speed of such electrical products is increased, the data transfer speed of the semiconductor devices is also very high.

In particular, several new concepts have been added to more quickly control the data transfer rate of Double Data Rate 3 (DDR3) Synchronous Dynamic Random Access Memory (SDRAM), among which the termination resistance facilitates signal transmission between devices. To do that.

Here, if the resistance is not properly matched, the transmitted signal is reflected, which is likely to cause an error in signal transmission. However, when a fixed resistor is applied to the outside, it may not be properly matched due to aging of the integrated circuit, temperature change, or difference in manufacturing process. Accordingly, recently, a technique of adjusting the resistance of the termination part by adjusting the number of transistors turned on among a plurality of transistors connected in parallel in order to have the same resistance value as compared with the external reference resistor has been proposed.

1 is a circuit diagram showing a configuration of a general on die termination circuit.

Referring to FIG. 1, a general on die termination circuit adjusts resistance values of resistors connected between input / output pads (DQs) of a semiconductor device to be the same. The pull-up control unit 110, the pull-up driving unit 120, and the pull-down control unit are adjusted. 130 and a pull-down driver 140.

The pull-up control unit 110 controls the PMOS transistors MP0, MP1, and MP2 that adjust the pull-up resistors PR1, PR2, and PR3 according to a PCODE signal, data, and a control signal named OCDTEN. <0: N>, UP120b <0: N>, and UP240b <0: N> are output to the pull-up driving unit 120.

The pull-up driver 120 may include one or more output blocks 121, 122, and 123 including the PMOS transistors MP0, MP1, and MP2 that adjust the pull-up resistors PR1, PR2, and PR3 and the pull-up resistors PR1, PR2, and PR3. And a pull-up resistor value according to the pull-up control signals UP60b <0: N>, UP120b <0: N>, and UP240b <0: N> output from the pull-up control unit 110 to output the output data. Output to the input / output pad DQ.

The pull-down control unit 130 controls a pull-down control signal DN240 for controlling the NMOS transistors MN0, MN1, and MN2 that adjust the pull-down resistors DR1, DR2, and DR3 according to the NCODE signal, data, and a control signal named OCDTEN. <0: N>, DN120 <0: N>, and DN60 <0: N> are output to the pull-down driving unit 140.

The pull-down driver 140 may include one or more output blocks 141, 142, and NMOS transistors MN0, MN1, and MN2 that adjust the pull-down resistors DR1, DR2, and DR3 and the pull-down resistors DR1, DR2, and DR3. And a pull-down resistance value according to the pull-down control signals DN60 <0: N>, DN120 <0: N>, and DN240 <0: N> output from the pull-down control unit 130. Is output to the input / output pad DQ.

In the general on-die termination circuit configured as described above, as shown in FIG. 1, the pull-up resistor values PU_60, PU_120, and PU_240 and the pull-down resistor values PD_60, PD_120, and PD_240 are compared by resistance values of the pull-up / pull-down driving unit. It can be seen that this is equally adjusted. However, even if the pull-up resistor values PU_60, PU_120, PU_240 and the pull-down resistor values PD_60, PD_120, PD_240 are adjusted equally, resistance mismatch may occur, and such resistance value mismatch may be an effective resistance value (effective Rtt). Is determined in a test mode after ZQ calibration, and resistance value mismatch verification can be performed by substituting the determined effective resistance value into a predetermined resistance value mismatch formula.

FIG. 2 is a graph illustrating slope occurrence between an effective resistance value and a resistance value mismatch of FIG. 1.

Referring to the graph illustrated in FIG. 2, the X axis represents an effective resistance value (effective Rtt), and the Y axis represents a resistance value mismatch. Referring to FIG. 2, the smaller the larger the effective resistance value (max), the larger the smaller the effective resistance value (min), the larger the slope occurs.

The reason for such a slope is that, on the surface, the resistance is 0 between the power supply voltage VDDQ and the PMOS transistors MP0, MP1, and MP2 and between the ground voltage VSSQ and the NMOS transistors MN0, MN1, and MN2. However, it is due to the parasitic resistance component between the power supply voltage (VDDQ) and the PMOS transistor. Here, the graph a shows the parasitic resistance generated between the ground voltage VSSQ and the NMOS transistors MN0, MN1, and MN2 rather than the parasitic resistance generated between the power supply voltage VDDQ and the PMOS transistors MP0, MP1, and MP2. This large case is shown, and the b graph shows that the parasitic resistance generated between the power supply voltage VDDQ and the PMOS transistors MP0, MP1, and MP2 is between the ground voltage VSSQ and the NMOS transistors MN0, MN1, and MN2. This is the case where it is larger than the parasitic resistance occurring in.

Therefore, in general, the on-die termination circuit has a surface area when the resistance value of the on-die termination circuit is newly set even after the ZQ calibration is adjusted such that the resistance values of the connected resistors are placed between the input / output pads (DQ) of the semiconductor device. There is a problem that a mismatch of the resistance value occurs due to the parasitic resistance components that are not exposed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an on-die termination circuit capable of compensating for mismatched resistance values caused by parasitic resistance components by adjusting a current supplied from a power supply voltage or a ground voltage.

The on-die termination circuit according to the present invention includes one or more pull-up output blocks comprising a pull-up resistor and a pull-up switch for adjusting the pull-up resistor, and controlling the one or more pull-up output blocks according to a pull-up control signal to output output data to an input / output pad. A pull-down output block including a pull-up driver for outputting a pull-down resistor and a pull-down switch for adjusting a pull-down resistor, and controlling the one or more pull-down output blocks according to a pull-down control signal to output output data to an input / output pad. And a pull-up current control driver disposed between the pull-up driver and the power supply voltage, and a pull-down current control driver disposed between the pull-down driver and the ground voltage.

The on-die termination circuit according to the present invention includes a pull-up current control driver between a pull-up driver and a power supply voltage, and a pull-down current control driver between a pull-down driver and a ground voltage to compensate for resistance mismatches caused by parasitic resistance components. It becomes possible.

1 is a circuit diagram showing a typical on die termination circuit,
FIG. 2 is a graph showing slope occurrence between an effective resistance value and a resistance value mismatch of FIG. 1;
3 is a circuit diagram illustrating an on die termination circuit according to an embodiment of the present invention;
4 is a circuit diagram illustrating a termination part of an on die termination circuit according to an embodiment of the present invention;
5 and 6 are exemplary diagrams illustrating an output block of an on die termination circuit according to an exemplary embodiment of the present invention.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, one embodiment of the present invention may be modified in various forms, and the scope of the present invention should not be construed as being limited due to the embodiments described below. One embodiment of the present invention is provided to more easily explain the present invention to those skilled in the art.

3 is a circuit diagram illustrating an on die termination circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the on die termination circuit according to an embodiment of the present invention may largely include a control signal generator 300 and a termination unit 400. At this time. The control signal generator 300 may include a pull-up controller 310 and a pull-down controller 320, and the termination unit 400 may include a pull-up driver 410, a pull-up current control driver 420, and a pull-down driver 430. And a pull-down current control driver 440.

The pull-up control unit 310 controls the pull-up switches MP0, MP1, and MP2 for adjusting the pull-up resistors PR1, PR2, and PR3 according to the PCODE signal, the data, and the control signal named OCDTEN. 0: N>, UP120b <0: N>, UP240b <0: N>) are output to the pull-up driving unit 410.

The pull-down control unit 320 controls the pull-down switch MN0, MN1, MN2 for adjusting the pull-down resistors DR1, DR2, and DR3 according to the NCODE signal, the data, and the control signal named OCDTEN. 0: N>, DN120 <0: N>, and DN240 <0: N>) are output to the pull-down driving unit 430.

The pull-up driver 410 may include one or more pull-ups including pull-up switches PR1, PR2, and PR3 and pull-up switches for adjusting the pull-up resistors PR1, PR2, and PR3, that is, PMOS transistors MP0, MP1, and MP2. Output blocks 411, 412, 413. The pull-up driver 410 may control the one or more pull-up output blocks 411, 412, and 413 by a control signal output from the pull-up control unit 310 to output output data to the input / output pad DQ.

The pull-up current control driver 420 is disposed between the power supply voltage VDDQ and the pull-up driver 410 to control a current flowing between the power supply voltage VDDQ and the pull-up driver 410. This is to compensate for the resistance mismatch due to the parasitic resistance generated between the power supply voltage VDDQ and the pull-up driver 410.

The pull-down driver 430 may include one or more pull-downs including pull-down resistors DR1, DR2, and DR3 and pull-down switches that control the pull-down resistors DR1, DR2, and DR3, that is, NMOS transistors MN0, MN1, and MN2. Output blocks 431, 432, and 433. The pull-down driver 430 may control the one or more pull-down output blocks 431, 432, and 433 by a control signal output from the pull-down controller 320 to output output data to the input / output pad DQ.

The pull-down current control driver 440 is disposed between the ground voltage VSSQ and the pull-down driver 430 to control a current flowing between the ground voltage VSSQ and the pull-down driver 430. This is to compensate for mismatches in resistance due to parasitic resistance generated between the ground voltage VSSQ and the pull-down driver 430.

4 is a circuit diagram illustrating a termination part of an on die termination circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 4, as described above with reference to FIG. 3, the termination unit 400 includes a pull-up driver 410 and a pull-up current control driver 420 with an input / output pad DQ interposed therebetween. ), A pull-down driver 430, and a pull-down current control driver 440.

Here, the pull-up current control driver 420 has a resistor Rpwr0, Rpwr1, Rpwr2, Rpwr3, Rpwr4, Rpwr5, one end of which is connected to the power supply voltage VDDQ and the other end of which is connected to the pull-up driver 410, and the resistor Rpwr0. And Rpwr1, Rpwr2, Rpwr3, Rpwr4, Rpwr5 in parallel and may include one or more PMOS transistors (P0, P1, P2) for adjusting the resistors Rpwr0, Rpwr1, Rpwr2, Rpwr3, Rpwr4, Rpwr5. have. In this case, the PMOS transistors P0, P1, and P2 are shown to be connected in parallel with the resistors Rpwr0, Rpwr1, Rpwr2, Rpwr3, Rpwr4, Rpwr5, but the resistors Rpwr0, Rpwr1, Rpwr2, Rpwr3, Rpwr4, Rpwr5) is shown as above on the drawing with an invisible resistance. Here, the resistors Rpwr0, Rpwr1, Rpwr2, Rpwr3, Rpwr4, Rpwr5 are parasitic resistors between the power supply voltage VDDQ and the pull-up driving unit 410. The parasitic resistances Rpwr0, Rpwr1, Rpwr2, Rpwr3, Rpwr4, Rpwr5 are small, but they are a factor in the resistance mismatch of the on-die termination circuit. Accordingly, the on-die termination circuit according to an embodiment of the present invention uses one or more PMOS transistors (P0, P1, P2) for adjusting the components of the parasitic resistor (Rpwr0, Rpwr1, Rpwr2, Rpwr3, Rpwr4, Rpwr5) By including a number of ohms can be controlled to compensate for the mismatch of the resistance value.

In addition, the pull-down current control driver 440 has resistors Rgnd0, Rgnd1, Rgnd2, Rgnd3, Rgnd4, and Rgnd5, one end of which is connected to the ground voltage VSSQ and the other end of which is connected to the pull-down driver 430, and the resistor Rgnd0. And Rgnd1, Rgnd2, Rgnd3, Rgnd4, and Rgnd5 in parallel to adjust the resistors Rgnd0, Rgnd1, Rgnd2, Rgnd3, Rgnd4, and Rgnd5 to control the current flowing between the ground voltage VSSQ and the pull-down driver 430. One or more NMOS transistors N0, N1, and N2 may be included. In this case, the NMOS transistors N0, N1, and N2 are shown to be connected in parallel with the resistors Rgnd0, Rgnd1, Rgnd2, Rgnd3, Rgnd4, and Rgnd5, but the resistors Rgnd0, Rgnd1, Rgnd2, Rgnd3, Rgnd4, Rgnd5) is shown as above in the drawing with an invisible resistance. Here, the resistors Rgnd0, Rgnd1, Rgnd2, Rgnd3, Rgnd4, and Rgnd5 are parasitic resistors between the ground voltage VSSQ and the pull-down driving unit 430. The parasitic resistances Rgnd0, Rgnd1, Rgnd2, Rgnd3, Rgnd4, and Rgnd5 are small in size, but are a factor in the resistance mismatch of the on-die termination circuit. Accordingly, the on-die termination circuit according to an embodiment of the present invention uses one or more NMOS transistors (N0, N1, N2) for adjusting the components of the parasitic resistors (Rgnd0, Rgnd1, Rgnd2, Rgnd3, Rgnd4, Rgnd5) By including a number of ohms can be controlled to compensate for the mismatch of the resistance value.

5 and 6 are exemplary diagrams illustrating an output block of an on die termination circuit according to an exemplary embodiment of the present invention.

First, referring to FIG. 5, an output block of any one of a plurality of output blocks 411, 412, 413, 431, 432, and 433 constituting an on die termination circuit according to an embodiment of the present invention is illustrated. The output block of the termination circuit includes pull-up resistors PR11, PR12, PR13, PR14, which have different resistance values in each of a plurality of branches (N Ohm, 2N Ohm, 4N Ohm, 8N Ohm, 16N Ohm, 32N Ohm). PR15, PR16) or pulldown resistors DR11, DR12, DR13, DR14, DR15, DR16 and the respective pullup resistors PR11, PR12, PR13, PR14, PR15, PR16 or pulldown resistors DR11, DR12, DR13, DR14, PMOS transistors (MP01, MP02, MP03, MP04, MP05, MP06) or NMOS transistors (MN01, MN02, MN03, MN04, MN05, MN06) for adjusting the DR15, DR16 may be configured. .

These branches (N Ohm, 2N Ohm, 4N Ohm, 8N Ohm, 16N Ohm, 32N Ohm) are arranged in order from the smallest resistance value to the largest. In order to compensate for the mismatch of resistance values due to parasitic resistance in the output block of the on-die termination circuit configured as described above, the resistance value of the plurality of branches (N Ohm, 2N Ohm, 4N Ohm, 8N Ohm, 16N Ohm, 32N Ohm) The pull-up current control driver 420 consisting of one or more PMOS transistors P01, P02, and P03 and the one or more NMOS transistors N01, N02, and N03 on the largest and smallest current driving branch (32N Ohm). Connect the pull-down current control driver 440 is configured. As such, the pull-up current control driver 420 is a branch (32 N Ohm) having the largest resistance value and the smallest current driving capability among the plurality of branches (N Ohm, 2N Ohm, 4N Ohm, 8N Ohm, 16N Ohm, 32N Ohm). The reason why the pull-down current control driver 440 is connected to the pull-up driver 410 and the pull-down driver is a branch 32N Ohm having the largest resistance value and the smallest current driving capability from the supply voltage VDDQ or the ground voltage VSSQ. It is most preferable to control the amount of current flowing into the number of ohms (430), because it is possible to compensate the resistance value mismatch due to parasitic resistance.

If the branch (N Ohm, 2N Ohm, 4N Ohm, 8N Ohm, 16N Ohm, 32N Ohm) has the largest resistance value and the smallest current driving capability (32N Ohm), the pull-up control unit 310 or the If it is deactivated by the control signal output from the pull-down control unit 320, as shown in FIG. 6, the branch 32N having the largest resistance value and the smallest current driving capability and the branch 32N having the same resistance value and current driving as shown in FIG. One more Ohm) can be used to compensate for mismatches in resistance due to parasitic resistance components.

The on-die termination circuit according to the embodiment of the present invention pulls down between the pull-up current control driver 420 and the pull-down driver 430 and the ground voltage VSSQ between the pull-up driver 410 and the power supply voltage VDDQ. By including the current control driver 440, it is possible to compensate the resistance mismatch by the parasitic resistance component.

310: pull-up control unit 320: pull-down driving unit
410: pull-up drive unit 411, 412, 413: pull-up output block
420: pull-up current control driver 430: pull-down driver
431, 432, 433: pull-down output block 440: pull-down current control driver

Claims (11)

A pull-up driver including at least one pull-up output block including a pull-up resistor and a pull-up switch for adjusting the pull-up resistor, and controlling the at least one pull-up output block according to a pull-up control signal to output output data to an input / output pad;
A pull-down driver including one or more pull-down output blocks including a pull-down switch for adjusting a pull-down resistor and a pull-down resistor, and controlling the one or more pull-down output blocks according to a pull-down control signal to output output data to an input / output pad;
A pull-up current control driver disposed between the pull-up driver and a power supply voltage; And
A pull-down current control driver disposed between the pull-down driver and a ground voltage;
On die termination circuit comprising a. The method of claim 1, wherein the pull-up current control driver,
A resistor having one end connected to the power supply voltage and the other end connected to the pull-up driving part; And
At least one PMOS transistor connected at one end to the power supply voltage and at the other end to the pull-up driving unit to adjust the resistance;
On die termination circuit comprising a. The method of claim 2, wherein the resistance is,
And a parasitic resistance between the power supply voltage and the pull-up driver. The method of claim 2, wherein the one or more PMOS transistors,
An on-die termination circuit disposed between the pull-up resistor source having the largest pull-up resistance value and the smallest current driving capability among the plurality of pull-up resistors constituting the pull-up output block and the power supply voltage; . The method of claim 4, wherein
When the pull-up resistor source having the largest pull-up resistance value and the smallest current driving capability is deactivated, the pull-up resistor source having the same resistance value and current driving capability as the deactivated one pull-up resistor source is further included. And disposing at least one PMOS transistor between an included pull-up resistor source and the power supply voltage. The pull-up switch of claim 1, wherein the pull-up switch includes:
An on-die termination circuit, characterized in that the NMOS transistor. The method of claim 1, wherein the pull-down current control driver,
A resistor having one end connected to the ground voltage and the other end connected to the pull-down driving unit; And
At least one NMOS transistor connected at one end to the ground voltage and at the other end to the pull-down driving unit to adjust the resistance;
On die termination circuit comprising a. The method of claim 7, wherein the resistance is,
And a parasitic resistance between the ground voltage and the pull-down driving unit. The method of claim 7, wherein the at least one NMOS transistor,
An on-die termination circuit disposed between any one of the pull-down resistor sources having the largest pull-down resistance value and the smallest current driving capability among the plurality of pull-down resistors constituting the pull-down output block and the ground voltage; . 10. The method of claim 9,
When the pull-down resistor source having the largest pull-down resistance value and the smallest current driving capability is deactivated, the pull-down resistor source having the same resistance value and current driving capability as the deactivated pull-down resistor source is further included. And disposing one or more NMOS transistors between the further included pull-down resistor source and the ground voltage. The pull down switch of claim 1, wherein
An on-die termination circuit, characterized in that the NMOS transistor.
KR1020100094950A 2010-09-30 2010-09-30 On die termination circuit KR20120033440A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180023344A (en) * 2016-08-25 2018-03-07 에스케이하이닉스 주식회사 Data transmitting device, semiconductor apparatus and system including the same
CN107786197A (en) * 2016-08-25 2018-03-09 爱思开海力士有限公司 Data transmission devices and the semiconductor devices and system for including it
KR20190029011A (en) * 2017-09-11 2019-03-20 에스케이하이닉스 주식회사 Memory system having data output driver
KR20190105863A (en) * 2018-03-06 2019-09-18 에스케이하이닉스 주식회사 Data output buffer
KR20190135863A (en) * 2018-05-29 2019-12-09 에스케이하이닉스 주식회사 Data output buffer and memory device having the same
KR20200008895A (en) * 2018-07-17 2020-01-29 에스케이하이닉스 주식회사 Data output buffer

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180023344A (en) * 2016-08-25 2018-03-07 에스케이하이닉스 주식회사 Data transmitting device, semiconductor apparatus and system including the same
CN107786197A (en) * 2016-08-25 2018-03-09 爱思开海力士有限公司 Data transmission devices and the semiconductor devices and system for including it
US10003335B2 (en) * 2016-08-25 2018-06-19 SK Hynix Inc. Data transmission device, and semiconductor device and system including the same
CN107786197B (en) * 2016-08-25 2021-03-16 爱思开海力士有限公司 Data transfer device, and semiconductor device and system including the same
KR20190029011A (en) * 2017-09-11 2019-03-20 에스케이하이닉스 주식회사 Memory system having data output driver
KR20190105863A (en) * 2018-03-06 2019-09-18 에스케이하이닉스 주식회사 Data output buffer
KR20190135863A (en) * 2018-05-29 2019-12-09 에스케이하이닉스 주식회사 Data output buffer and memory device having the same
KR20200008895A (en) * 2018-07-17 2020-01-29 에스케이하이닉스 주식회사 Data output buffer

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