KR20100074479A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- KR20100074479A KR20100074479A KR1020080132934A KR20080132934A KR20100074479A KR 20100074479 A KR20100074479 A KR 20100074479A KR 1020080132934 A KR1020080132934 A KR 1020080132934A KR 20080132934 A KR20080132934 A KR 20080132934A KR 20100074479 A KR20100074479 A KR 20100074479A
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- oxide film
- gate
- trench
- semiconductor substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 125000006850 spacer group Chemical group 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 12
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims description 12
- 239000007943 implant Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
The present invention relates to a semiconductor device, and more particularly to a semiconductor device and a method of manufacturing the same.
In semiconductor devices that are highly integrated and have a MOS transistor, the channel length is generally dependent on the length of the polyline for gate formation.
In this case, when the poly line is defined, gate CD variation may be caused by a photograph, an etching apparatus, and process conditions.
As a result, transistor performance characteristics may be changed due to variations in the channel length of the polyline for each semiconductor chip, and may cause short leakage defects.
An object of the present invention is to provide a semiconductor device capable of forming a channel structure that is not affected by gate CD variation and a method of manufacturing the same.
A semiconductor device according to an embodiment of the present invention for achieving the above object is a trench formed by etching a portion of the channel region in the semiconductor substrate, a gate oxide film formed in the trench, a gate electrode formed on the gate oxide film A spacer formed on sidewalls of the gate electrode, an LDD region formed on both sides of the gate electrode in the semiconductor substrate, a source and drain region formed by using the gate electrode and the spacer as a mask, and the gate electrode, source and drain And a silicide film formed on the region.
According to an aspect of the present disclosure, a method of manufacturing a semiconductor device includes etching a portion of a channel region in a semiconductor substrate to form a trench, and forming a buffer oxide layer on the semiconductor substrate including the trench. Forming a well region using ion implantation on the semiconductor substrate on which the buffer oxide film is formed, removing the buffer oxide film, and forming a gate oxide film and a gate electrode on the semiconductor substrate including the trench. Forming an LDD region in the semiconductor substrate through a sequential forming step, an ion implantation process using the gate oxide film and the gate electrode as a mask, and forming spacers on sidewalls of the gate oxide film and the gate electrode; Ion implantation using the gate electrode and the spacer as a mask; The process includes forming source and drain regions in the semiconductor substrate.
A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention have the following effects.
After etching the portion where the channel region of the silicon substrate is to be formed to form a trench, a gate oxide film is formed in the trench, and a poly gate electrode is formed on the gate oxide film, thereby changing the process conditions and process equipment for forming the gate. There is an effect that can form a channel structure that is not affected by the gate CD variation (gate CD variation).
Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.
1 is a cross-sectional view of a semiconductor device according to the present invention.
Referring to FIG. 1, a
Here, when the depth of the
As such, after the
2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
Referring to FIG. 2A, a photoresist material (not shown) is applied onto the
Next, a
Next, as shown in FIG. 2B, a portion of the
Here, when the depth of the
The remaining
Subsequently, a
If the thickness of the
The
Subsequently, an ion implantation process for forming a well on the
After the well region is formed, the
Referring to FIG. 2D, a transistor is formed on the
Specifically, an insulating film for a gate oxide film (not shown) is formed on the
Subsequently, a low concentration source / gate is formed on the
A nitride film (not shown) is deposited on the
Subsequently, the semiconductor substrate is formed of a semiconductor substrate having the same conductivity type as the impurities implanted during the ion implantation process for forming the low concentration source / drain region, that is, the
Subsequently, a
In this case, the metal generally uses titanium (Ti) or cobalt (Co).
As such, after forming a trench by etching the portion where the channel region of the silicon substrate is to be formed, a gate oxide film is formed in the trench and a poly gate electrode is formed on the gate oxide film, thereby forming process conditions and process equipment for forming the gate. It is possible to form a channel structure that is not affected by gate CD variation due to a change.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.
1 is a cross-sectional view of a semiconductor device according to the present invention.
2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
<Description of Symbols for Main Parts of Drawings>
100
122: gate oxide film 127: poly gate
129: spacer 144: LDD region
145, 148: source and
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080132934A KR20100074479A (en) | 2008-12-24 | 2008-12-24 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080132934A KR20100074479A (en) | 2008-12-24 | 2008-12-24 | Semiconductor device and method for manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20100074479A true KR20100074479A (en) | 2010-07-02 |
Family
ID=42636991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020080132934A KR20100074479A (en) | 2008-12-24 | 2008-12-24 | Semiconductor device and method for manufacturing the same |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20100074479A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170030985A (en) | 2015-09-10 | 2017-03-20 | 대우조선해양 주식회사 | Subsea concrete caisson foundation structure and Method for installing the same |
-
2008
- 2008-12-24 KR KR1020080132934A patent/KR20100074479A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170030985A (en) | 2015-09-10 | 2017-03-20 | 대우조선해양 주식회사 | Subsea concrete caisson foundation structure and Method for installing the same |
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