KR20100074479A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
KR20100074479A
KR20100074479A KR1020080132934A KR20080132934A KR20100074479A KR 20100074479 A KR20100074479 A KR 20100074479A KR 1020080132934 A KR1020080132934 A KR 1020080132934A KR 20080132934 A KR20080132934 A KR 20080132934A KR 20100074479 A KR20100074479 A KR 20100074479A
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KR
South Korea
Prior art keywords
gate electrode
oxide film
gate
trench
semiconductor substrate
Prior art date
Application number
KR1020080132934A
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Korean (ko)
Inventor
이종복
Original Assignee
주식회사 동부하이텍
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Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080132934A priority Critical patent/KR20100074479A/en
Publication of KR20100074479A publication Critical patent/KR20100074479A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A semiconductor device and a method for manufacturing the same are provided to form a channel structure, which is not affected by a gate critical dimension variation, by forming a poly gate electrode on a gate oxide film. CONSTITUTION: A trench is formed by etching a part of a channel region within a semiconductor substrate. A gate oxide film(122) is formed in the trench. A gate electrode is formed on the gate oxide film. A spacer is formed on the sidewall of a gate electrode. A lightly doped drain region(144) is formed on both sides of the gate electrode. A source and drain region is formed using the gate electrode and the spacer as a mask. A silicide film(150) is formed on the gate electrode, the source and the drain region.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device, and more particularly to a semiconductor device and a method of manufacturing the same.

In semiconductor devices that are highly integrated and have a MOS transistor, the channel length is generally dependent on the length of the polyline for gate formation.

In this case, when the poly line is defined, gate CD variation may be caused by a photograph, an etching apparatus, and process conditions.

As a result, transistor performance characteristics may be changed due to variations in the channel length of the polyline for each semiconductor chip, and may cause short leakage defects.

An object of the present invention is to provide a semiconductor device capable of forming a channel structure that is not affected by gate CD variation and a method of manufacturing the same.

A semiconductor device according to an embodiment of the present invention for achieving the above object is a trench formed by etching a portion of the channel region in the semiconductor substrate, a gate oxide film formed in the trench, a gate electrode formed on the gate oxide film A spacer formed on sidewalls of the gate electrode, an LDD region formed on both sides of the gate electrode in the semiconductor substrate, a source and drain region formed by using the gate electrode and the spacer as a mask, and the gate electrode, source and drain And a silicide film formed on the region.

According to an aspect of the present disclosure, a method of manufacturing a semiconductor device includes etching a portion of a channel region in a semiconductor substrate to form a trench, and forming a buffer oxide layer on the semiconductor substrate including the trench. Forming a well region using ion implantation on the semiconductor substrate on which the buffer oxide film is formed, removing the buffer oxide film, and forming a gate oxide film and a gate electrode on the semiconductor substrate including the trench. Forming an LDD region in the semiconductor substrate through a sequential forming step, an ion implantation process using the gate oxide film and the gate electrode as a mask, and forming spacers on sidewalls of the gate oxide film and the gate electrode; Ion implantation using the gate electrode and the spacer as a mask; The process includes forming source and drain regions in the semiconductor substrate.

A semiconductor device and a method of manufacturing the same according to an embodiment of the present invention have the following effects.

After etching the portion where the channel region of the silicon substrate is to be formed to form a trench, a gate oxide film is formed in the trench, and a poly gate electrode is formed on the gate oxide film, thereby changing the process conditions and process equipment for forming the gate. There is an effect that can form a channel structure that is not affected by the gate CD variation (gate CD variation).

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

1 is a cross-sectional view of a semiconductor device according to the present invention.

Referring to FIG. 1, a trench 110 formed in a channel region in a silicon substrate, which is a semiconductor substrate 100, a gate oxide film 122 formed in the trench 110, and a poly gate formed on the gate oxide film 122. An electrode 127, a spacer 129 formed on sidewalls of the poly gate electrode 127, a lightly doped drain (LDD) region 144 formed on both sides of the poly gate electrode 127 in the semiconductor substrate 100, and a poly Source and drain regions 145 and 148 formed using the spacers 129 on both sides of the gate electrode 127 as a mask, and the poly gate electrode 127 and the source and drain to form a contact point of the device region. Metal silicide film 150 formed over regions 145 and 148.

Here, when the depth of the trench 110 is formed too thin, a gate CD variation is induced as in the prior art, and when the depth of the trench 110 is formed too deep, a subsequent well implant Since it is difficult to control the well region depth during the process and the copper field characteristics of the transistors are deteriorated, the depth is preferably 200 mW to 300 mW.

As such, after the trench 110 is formed by etching the portion where the channel region of the silicon substrate is to be formed, the gate oxide layer 122 is formed in the trench 110, and the poly gate electrode 127 is formed on the gate oxide layer 122. ), It is possible to form a channel structure that is not affected by gate CD variation due to changes in process conditions and process equipment for forming a gate.

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, a photoresist material (not shown) is applied onto the semiconductor substrate 100.

Next, a photoresist pattern 102 is formed to expose the channel region 104 through an etching process using a photoresist material (not shown) as a mask.

Next, as shown in FIG. 2B, a portion of the channel region 104 of the semiconductor substrate 100 is etched through an etching process using the photoresist pattern 102 to form the trench 110.

Here, when the depth of the trench 110 is formed too thin, a gate CD variation is induced as in the prior art, and when the depth of the trench 110 is formed too deep, a subsequent well implant Since it is difficult to control the well region depth during the process and the copper field characteristics of the transistors are deteriorated, the depth is preferably 200 mW to 300 mW.

The remaining photoresist pattern 102 is removed through an ashing process or the like.

Subsequently, a buffer oxide film 120 is formed on the semiconductor substrate 100 on which the trench 110 is formed as shown in FIG. 2C.

If the thickness of the buffer oxide film 120 is formed too thin, damage on the semiconductor substrate 100 may occur during the implant process, and if the thickness is too thick, impurity ions are difficult to be implanted during the implant process. Is formed to a thickness of 100 kPa to 150 kPa.

The buffer oxide film 120 formed as described above is formed to prevent damage on the semiconductor substrate 100 and to adjust the well region depth during a subsequent well implant process.

Subsequently, an ion implantation process for forming a well on the buffer oxide layer 120 is performed. The ion implantation process may be performed several times using a separate ion implantation mask film pattern.

After the well region is formed, the buffer oxide film 120 is removed.

Referring to FIG. 2D, a transistor is formed on the semiconductor substrate 100 from which the buffer oxide film 120 is removed.

Specifically, an insulating film for a gate oxide film (not shown) is formed on the semiconductor substrate 100 on which the trench 110 is formed, and a polysilicon film (not shown) is deposited as a conductive material thereon. Subsequently, the gate electrode 127 and the gate oxide film 122 are formed by patterning an insulating film for a polysilicon film and a gate oxide film by performing a photolithography and an etching process using a gate mask.

Subsequently, a low concentration source / gate is formed on the semiconductor substrate 100 on which the gate electrode 127 and the gate oxide film 122 are formed, with the gate electrode 127 interposed between the gate electrode 127 through low concentration impurity ion implantation. A lightly doped drain (LDD) region 144 that is a drain region is formed.

A nitride film (not shown) is deposited on the semiconductor substrate 100, and then anisotropically etched to form spacers 129 on sidewalls of the gate electrode 127.

Subsequently, the semiconductor substrate is formed of a semiconductor substrate having the same conductivity type as the impurities implanted during the ion implantation process for forming the low concentration source / drain region, that is, the LDD region 144 using the gate electrode 127 and the spacers 129 on the sidewalls as masks. High concentration source / drain regions 145 and 148 are formed by ion implantation into 100.

Subsequently, a metal silicide film 150 is formed to form a contact of the device region, and then the source and drain regions 145 and 148 and the poly gate electrode 127 on the device region. The remaining metal silicide film 150 is removed, leaving only the metal silicide 150 film on top.

In this case, the metal generally uses titanium (Ti) or cobalt (Co).

As such, after forming a trench by etching the portion where the channel region of the silicon substrate is to be formed, a gate oxide film is formed in the trench and a poly gate electrode is formed on the gate oxide film, thereby forming process conditions and process equipment for forming the gate. It is possible to form a channel structure that is not affected by gate CD variation due to a change.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a cross-sectional view of a semiconductor device according to the present invention.

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Description of Symbols for Main Parts of Drawings>

100 semiconductor substrate 110 trench

122: gate oxide film 127: poly gate

129: spacer 144: LDD region

145, 148: source and drain regions 150 silicide film

Claims (5)

A trench formed by etching a portion of the channel region in the semiconductor substrate; A gate oxide film formed in the trench; A gate electrode formed on the gate oxide film; A spacer formed on sidewalls of the gate electrode; LDD regions formed on both sides of the gate electrode in the semiconductor substrate; Source and drain regions formed using the gate electrode and the spacer as a mask; And a silicide layer formed on the gate electrode, the source, and the drain region. The method of claim 1, The trench is a semiconductor device, characterized in that formed in a depth of 200 ~ 300Å. Etching a portion of the channel region in the semiconductor substrate to form a trench; Forming a buffer oxide film on the semiconductor substrate including the trench; Forming a well region using ion implantation on the semiconductor substrate on which the buffer oxide film is formed, and then removing the buffer oxide film; Sequentially forming a gate oxide film and a gate electrode on the semiconductor substrate including the trench; Forming an LDD region in the semiconductor substrate through an ion implantation process using the gate oxide film and the gate electrode as a mask; Forming a spacer on sidewalls of the gate oxide layer and the gate electrode; Forming a source and a drain region in the semiconductor substrate through an ion implantation process using the gate electrode and the spacer as a mask. The method of claim 3, wherein The trench is a method of manufacturing a semiconductor device, characterized in that formed in a depth of 200 ~ 300Å. The method of claim 3, wherein The buffer oxide film is a semiconductor device manufacturing method, characterized in that formed in a thickness of 100 ~ 150Å.
KR1020080132934A 2008-12-24 2008-12-24 Semiconductor device and method for manufacturing the same KR20100074479A (en)

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Application Number Priority Date Filing Date Title
KR1020080132934A KR20100074479A (en) 2008-12-24 2008-12-24 Semiconductor device and method for manufacturing the same

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Application Number Priority Date Filing Date Title
KR1020080132934A KR20100074479A (en) 2008-12-24 2008-12-24 Semiconductor device and method for manufacturing the same

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170030985A (en) 2015-09-10 2017-03-20 대우조선해양 주식회사 Subsea concrete caisson foundation structure and Method for installing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170030985A (en) 2015-09-10 2017-03-20 대우조선해양 주식회사 Subsea concrete caisson foundation structure and Method for installing the same

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