KR20090001078A - Method for forming the alignment key of semiconductor device - Google Patents
Method for forming the alignment key of semiconductor device Download PDFInfo
- Publication number
- KR20090001078A KR20090001078A KR1020070065178A KR20070065178A KR20090001078A KR 20090001078 A KR20090001078 A KR 20090001078A KR 1020070065178 A KR1020070065178 A KR 1020070065178A KR 20070065178 A KR20070065178 A KR 20070065178A KR 20090001078 A KR20090001078 A KR 20090001078A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- hard mask
- pattern
- layer
- mask layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 125000006850 spacer group Chemical group 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The present invention relates to a method of forming an alignment key of a semiconductor device, wherein spacers are formed on both sides of a hard mask layer pattern, the hard mask layer pattern is removed, and an alignment key is formed using the spacer as an etch mask. By doing so, it is possible to form a fine pattern of 40nm or less by using existing equipment, thereby improving the alignment accuracy to disclose a technique for improving the characteristics of the device.
Description
1A to 1C are cross-sectional views illustrating a method for forming an alignment key of a semiconductor device according to the prior art.
2A to 2G are cross-sectional views illustrating a method for forming an alignment key of a semiconductor device according to the present invention.
<Explanation of Signs of Major Parts of Drawings>
100, 200:
120 and 220:
140, 240: antireflection film 150: photosensitive film pattern
110a, 210a: amorphous
130a and 230a: Hard Mask Layer Pattern 225: Etched Layer
225a: alignment key 250: first photosensitive film pattern
255: spacer 260: second photosensitive film pattern
The present invention relates to a method of forming an alignment key of a semiconductor device, wherein spacers are formed on both sides of a hard mask layer pattern, the hard mask layer pattern is removed, and an alignment key is formed using the spacer as an etch mask. By doing so, it is possible to form a fine pattern of 40 nm or less while using existing equipment, thereby improving the alignment accuracy (alignment accuracy) to disclose a technique for improving the characteristics of the device.
Pattern size is decreasing with high integration of semiconductor devices. Accordingly, various approaches have been taken in terms of equipment and processes to form fine patterns. For example, a method of reducing the exposure wavelength or increasing the size of a lens has been mainly used for forming a fine pattern.
However, this method requires the development of equipment, which increases the equipment investment cost, and causes difficulties in operating the equipment.
Accordingly, as an alternative method of forming a fine pattern conforming to high integration even using existing equipment, a double exposure technique using two exposure masks and a SPT (Spacer Patterning Technology) method using three exposure masks have been proposed.
1A to 1C are cross-sectional views illustrating a method of forming an alignment key of a semiconductor device according to the prior art.
Referring to FIG. 1A, an amorphous carbon layer (a-Carbon) 110, a silicon oxynitride layer (SiON, 120), a
Next, the
Referring to FIG. 1B, the
Next, the anti-reflection film pattern (not shown) and the
Referring to FIG. 1C, the
Next, the hard
In the above-described method for forming an alignment key of a semiconductor device according to the related art, a photosensitive film pattern is formed using one exposure mask, and an alignment key is formed using the mask. Such direct patterning is 40 nm or less. There is a problem that is difficult to implement a fine pattern.
The present invention forms spacers on both sides of the hard mask layer pattern, removes the hard mask layer pattern, and forms an alignment key using the spacer as an etch mask. It is an object of the present invention to provide a method for forming an alignment key of a semiconductor device in which a pattern can be formed, thereby improving alignment accuracy and improving device characteristics.
Method for forming an alignment key of a semiconductor device according to the present invention
Forming an etched layer on the semiconductor substrate;
Forming a hard mask layer pattern on the etched layer;
Forming spacers on both sides of the hard mask layer pattern;
Removing the hard mask layer pattern;
And etching the lower etched layer under the spacers as a mask to form the alignment key by removing the spacers.
The etching layer is formed of an amorphous carbon layer (a-Cabon) and silicon oxynitride (SiON),
Forming a spacer layer on the entire spacer including the hard mask layer pattern;
Performing an etch back process to form spacers on both sides of the hard mask layer pattern;
The spacer is formed to a thickness of 10 ~ 100nm,
The spacer may be formed of a nitride film.
In addition, in the semiconductor element of the cell region and the peripheral circuit region,
Forming an etched layer and a hard mask layer on the semiconductor substrate;
Etching the hard mask layer to form a hard mask layer pattern;
Forming spacers on both sides of the hard mask layer pattern;
Removing the hard mask layer pattern;
Forming a photoresist pattern for opening the cell region;
Removing the photoresist pattern after performing an etching process in the cell region;
Etching the etched layer below using the spacer as a mask;
And removing the spacers to form an alignment key.
Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
2A to 2G are cross-sectional views illustrating a method of forming an alignment key of a semiconductor device according to the present invention, and show only peripheral circuit regions.
Referring to FIG. 2A, an
Here, the
Next, a first
In this case, the first
Referring to FIG. 2B, the
Next, the
Referring to FIG. 2C, a spacer layer (not shown) having a predetermined thickness is formed on the entire semiconductor substrate including the hard
Here, the spacer layer (not shown) is formed of a nitride film, and the spacer layer (not shown) is preferably formed to a thickness of 10 ~ 100nm to secure the line width (Width) of the alignment key in the subsequent process.
Next, an
In this case, the spacer layer (not shown) formed on the hard
Referring to FIG. 2D, the hard
At this time, while the hard
Referring to FIG. 2E, the second
In this case, the second
The reason why the peripheral circuit region is not opened is to prevent the
Next, the
Referring to FIG. 2F, the
Although not shown, a third photoresist pattern (not shown) for a third photolithography process is formed, and the third photoresist pattern (not shown) is formed of a silicon oxynitride layer (3) during the third photolithography process of the cell region. It is preferable that the peripheral circuit area is formed to be open to etch 220.
Referring to FIG. 2G, the
Next, the
Thereafter, the third photoresist layer pattern (not shown) is removed to form an
Here, by forming an alignment key using a spacer patterning technology (SPT) process using the
In the method of forming an alignment key of a semiconductor device according to the present invention, spacers are formed on both sides of a hard mask layer pattern, the hard mask layer pattern is removed, and an alignment key is formed by using the spacer as an etch mask. It is possible to form a fine pattern of, thereby improving the alignment accuracy has the effect of improving the characteristics of the device.
In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070065178A KR20090001078A (en) | 2007-06-29 | 2007-06-29 | Method for forming the alignment key of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070065178A KR20090001078A (en) | 2007-06-29 | 2007-06-29 | Method for forming the alignment key of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20090001078A true KR20090001078A (en) | 2009-01-08 |
Family
ID=40484190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070065178A KR20090001078A (en) | 2007-06-29 | 2007-06-29 | Method for forming the alignment key of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20090001078A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106919015A (en) * | 2015-12-25 | 2017-07-04 | 株洲南车时代电气股份有限公司 | A kind of semiconductor devices makes lithography alignment method |
US9812364B2 (en) | 2015-10-28 | 2017-11-07 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device with an overlay mask pattern |
KR20220147881A (en) | 2021-04-28 | 2022-11-04 | 농업회사법인 해담주식회사 | Pickled cabbage manufactured by sterilization and preservative methods and their manufacturing methods |
-
2007
- 2007-06-29 KR KR1020070065178A patent/KR20090001078A/en not_active Application Discontinuation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9812364B2 (en) | 2015-10-28 | 2017-11-07 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device with an overlay mask pattern |
CN106919015A (en) * | 2015-12-25 | 2017-07-04 | 株洲南车时代电气股份有限公司 | A kind of semiconductor devices makes lithography alignment method |
KR20220147881A (en) | 2021-04-28 | 2022-11-04 | 농업회사법인 해담주식회사 | Pickled cabbage manufactured by sterilization and preservative methods and their manufacturing methods |
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