KR20080029273A - Stack package and hi-density multi package using the same - Google Patents

Stack package and hi-density multi package using the same Download PDF

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Publication number
KR20080029273A
KR20080029273A KR1020060095097A KR20060095097A KR20080029273A KR 20080029273 A KR20080029273 A KR 20080029273A KR 1020060095097 A KR1020060095097 A KR 1020060095097A KR 20060095097 A KR20060095097 A KR 20060095097A KR 20080029273 A KR20080029273 A KR 20080029273A
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South Korea
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substrate
package
stack
printed circuit
circuit board
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KR1020060095097A
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Korean (ko)
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도은혜
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주식회사 하이닉스반도체
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Publication of KR20080029273A publication Critical patent/KR20080029273A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

A stack package and a high-density multi-package using the same are provided to stack more number of stack packages in the same area relative to the prior art using a rectangular encapsulant. A printed circuit board includes a circuit pattern having an electrode terminal disposed on an upper surface and a ball land disposed on a lower surface. Plural semiconductor chips(110,111,112,113) of edge pad type are stacked on the substrate via an adhesive. Bonding pads of the stacked semiconductor chips are connected to each other via plural metal wires(120), and a bonding pad of the lowermost semiconductor chip is connected to the electrode terminal of the printed circuit board via a metal wire. The upper surface of the substrate comprising the metal wires and the semiconductor chips is sealed by a pyramid-shaped encapsulant(160), and a solder ball(150) is attached to the ball land of the substrate.

Description

스택 패키지 및 이를 이용한 고밀도 멀티 패키지{STACK PACKAGE AND HI-DENSITY MUlTI PACKAGE USING THE SAME}STACK PACKAGE AND HI-DENSITY MUlTI PACKAGE USING THE SAME

도 1은 종래 스택 패키지를 도시한 단면도.1 is a cross-sectional view showing a conventional stack package.

도 2는 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도.2 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 고밀도 멀티 패키지를 도시한 단면도.3 is a cross-sectional view showing a high density multi-package according to an embodiment of the present invention.

도 4a 내지 도 4c는 본 발명의 실시예에 따른 고밀도 멀티 패키지의 제조 방법을 설명하기 위하여 도시한 단면도.4A to 4C are cross-sectional views illustrating a method of manufacturing a high density multi-package according to an embodiment of the present invention.

도 5는 본 발명의 다른 실시예에 따른 고밀도 멀티 패키지를 도시한 단면도.5 is a cross-sectional view showing a high density multi-package according to another embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

110 : 칩 140 : 인쇄회로 기판110: chip 140: printed circuit board

150 : 제1솔더볼 160 : 봉지제150: first solder ball 160: sealing agent

170 : 제1기판 180 : 제2기판170: first substrate 180: second substrate

190a : 제2솔더볼 240 : 접합 수단190a: second solder ball 240: bonding means

본 발명은 반도체 패키지에 관한 것으로서, 보다 상세하게는, 피라미드 형태 의 봉지제를 가지는 스택 패키지와 그를 이용한 경박단소한 고밀도 멀티 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a stack package having a pyramidal encapsulant and a light and simple high density multi-package using the same.

전기·전자 제품이 고성능화되고 전자기기들이 경박단소화됨에 따라 핵심 소자인 패키지의 고밀도, 고실장화가 중요한 문제로 대두되고 있으며, 또한 컴퓨터의 경우 기억 용량의 증가에 따라 대용량의 램(Random Access Memory) 및 플래쉬 메모리(Flash Memory)와 같이 칩의 용량은 증대되지만, 패키지는 소형화되는 경향으로 연구되고 있어 한정된 크기의 기판에 더 많은 수의 패키지를 실장하기 위한 여러 가지 기술들이 제안·연구되고 있다. As electrical and electronic products are getting higher performance and electronic devices are lighter and shorter, the high density and high mounting of packages, which are key components, are becoming an important issue.In the case of computers, as the memory capacity increases, a large amount of RAM (Random Access Memory) As chips have increased capacities, such as flash memory, but packages are being miniaturized, various techniques for mounting a larger number of packages on a limited size substrate have been proposed and studied.

고용량의 반도체 모듈을 제공하기 위한 방법으로서는 메모리 칩의 용량 증대, 즉, 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간 내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. 그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선폭을 요구하는 등의 고난도의 기술과 많은 개발 시간을 필요로 한다. 따라서, 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서 스택(Stack) 기술이 제안되었다.As a method for providing a high capacity semiconductor module, there is an increase in the capacity of the memory chip, that is, high integration of the memory chip, which can be realized by integrating a larger number of cells in a limited space of the semiconductor chip. have. However, such high integration of the memory chip requires a high level of technology and a lot of development time, such as requiring a precise fine line width. Therefore, a stack technology has been proposed as another method for providing a high capacity semiconductor module.

반도체 산업에서 말하는 "스택"이란 적어도 2개 이상의 반도체 칩, 또는 반도체 패키지를 수직으로 쌓아 올린 것으로서, 스택 패키지는 메모리 용량 증대와 실장 밀도 및 실장 면적 사용의 효율성 측면에서 잇점이 있기 때문에, 이러한 스택 패키지에 대한 연구 및 개발은 가속화 되고 있는 실정이다.The term "stack" in the semiconductor industry is a stack of at least two semiconductor chips, or semiconductor packages, which are stacked in such a way that stack packages have advantages in terms of increased memory capacity and efficiency in mounting density and footprint. The research and development of this technology is being accelerated.

도 1은 종래 스택 패키지를 도시한 단면도이다.1 is a cross-sectional view showing a conventional stack package.

우선 스택 패키지를 구현하기 위한 패키지(30)들의 구성을 설명하면, 도시된 바와 같이, 다수의 본딩 패드(미도시)를 가지는 반도체 칩(10)과 외부와의 전기적 연결을 위한 매개체인 인쇄회로 기판(12)이 접착제(20)에 의해 물리적으로 부착되어 있다. 그리고, 본딩 와이어(18)를 통하여 반도체 칩(10)에 구비된 다수의 본딩 패드(미도시)와 인쇄회로 기판(12)의 전극 단자(16)가 전기적으로 연결되어 있다. 또한, 상기 반도체 칩(10), 본딩 와이어(18), 전극 단자(16) 등은 봉지제(22)로 봉지되어 있고, 인쇄회로 기판(12)의 하면에 위치한 다수의 볼랜드(미도시)에는 솔더볼(24)들이 부착되어 패키지(30)들이 구성된다. First, the configuration of the packages 30 for implementing the stack package will be described. As shown, a printed circuit board which is a medium for electrical connection between the semiconductor chip 10 having a plurality of bonding pads (not shown) and the outside 12 is physically attached by the adhesive 20. The plurality of bonding pads (not shown) provided on the semiconductor chip 10 and the electrode terminals 16 of the printed circuit board 12 are electrically connected through the bonding wires 18. In addition, the semiconductor chip 10, the bonding wire 18, the electrode terminal 16, and the like are encapsulated with the encapsulant 22, and a plurality of ball lands (not shown) disposed on the lower surface of the printed circuit board 12 are provided. The solder balls 24 are attached to the package 30.

그리고, 스택 패키지(30)는 상기와 같이 제작된 패키지(30)들이 별도의 기판(26) 상에 마운팅(Mounting)되어 있고, 상기 마운팅된 패키지(30)들 사이에 전기적인 패스 및 물리적인 접합을 형성하기 위하여 패키지(30)들이 마운팅되어 있는 기판(26)의 양측에는 각각 메탈 핀(Pin)(28)이 연결되어 있으며, 최하부의 패키지(30)가 실장된 기판(26)의 하부 볼랜드에는 외부와의 전기적인 연결을 이루는 솔더볼(32)이 부착되어 구성된다. In addition, the stack package 30 is mounted on the separate substrate 26, the package 30 is manufactured as described above, the electrical path and physical bonding between the mounted package 30 Metal pins 28 are connected to both sides of the substrate 26 on which the packages 30 are mounted, respectively, and to the lower borland of the substrate 26 on which the lower package 30 is mounted. The solder ball 32 forming an electrical connection with the outside is attached.

그러나, 종래 스택 패키지의 가장 큰 문제점은 요구되는 용량을 얻기 위하여 패키지를 적층할 때, 적층되는 패키지들 사이의 전기적 연결을 위하여 별도의 인쇄회로 기판과 솔더볼 또는 메탈 핀 등이 사용되므로 실장 면적이 넓어지고 전체 스택 패키지의 높이가 상승하는 문제점이 있다. However, the biggest problem of the conventional stack package is that when a package is stacked to obtain a required capacity, a separate printed circuit board and solder balls or metal pins are used for electrical connection between the stacked packages, thereby increasing the mounting area. There is a problem that the height of the entire stack package rises.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 본 발명은 피라미드 형태의 봉지제를 가지는 스택 패키지와 이를 이용한 경박단소한 고밀도 멀티 패키지를 제작함에 그 목적이 있다. The present invention has been made to solve the above problems, the present invention has an object to produce a stack package having a pyramidal type sealing agent and a light and simple high density multi-package using the same.

상기와 같은 목적을 달성하기 위한 본 발명의 스택 패키지는, 상면에 배치되는 전극 단자 및 하면에 배치되는 볼랜드를 포함하여 회로 패턴이 구비된 인쇄회로 기판; 상기 인쇄회로 기판 상에 접착제를 매개로 하여 적층되며, 하부로부터 상부로 갈수록 작은 크기를 갖는 다수의 에지 패드형 반도체 칩; 상기 적층된 위/아래 반도체 칩들의 본딩 패드들간을 상호 연결함과 아울러 최하부에 배치된 반도체 칩의 본딩 패드와 인쇄회로 기판의 전극 단자를 상호 연결시키는 다수의 금속 와이어; 상기 금속 와이어들 및 적층된 반도체 칩들을 포함한 기판 상면을 밀봉하는 피라미드 형태의 봉지제; 및 상기 인쇄회로 기판의 볼랜드에 부착된 솔더볼을 제공한다.The stack package of the present invention for achieving the above object, the printed circuit board is provided with a circuit pattern including an electrode terminal disposed on the upper surface and a ball land disposed on the lower surface; A plurality of edge pad type semiconductor chips stacked on the printed circuit board through an adhesive and having a smaller size from bottom to top; A plurality of metal wires interconnecting the bonding pads of the stacked upper and lower semiconductor chips and interconnecting the bonding pads of the semiconductor chip disposed at the bottom and the electrode terminals of the printed circuit board; A pyramidal encapsulant sealing the upper surface of the substrate including the metal wires and the stacked semiconductor chips; And it provides a solder ball attached to the ball land of the printed circuit board.

(실시예)(Example)

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 보다 상세하게 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도이다.2 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

도시된 바와 같이, 상면에 다수의 본딩 패드(미도시)가 형성되어 있고 스택이 가능하도록 하부로부터 상부로 갈수록 작은 크기를 갖는 다수의 에지 패드형 반도체 칩(110, 111, 112, 113)들이 접착제를 매개로 하여 인쇄회로 기판(140) 상에 스택되어 있다. 그리고, 상기 스택된 칩들(110, 111, 112, 113) 상호 간에 그리고 최하부의 칩(113)과 인쇄회로 기판(140) 사이는 금(Au) 등으로 이루어진 금속 와이 어(120)로 연결되어 전기적 패스를 형성하고 있다. 또한, 상기 스택된 칩들(110, 111, 112, 113)과 금속 와이어(120) 등을 보호하기 위하여 피라미드 형태의 봉지제(160)가 형성되어 있으며, 상기 인쇄회로 기판(140)의 하면에 위치한 각 볼랜드(미도시)에 제1솔더볼(150)이 부착되어 본 발명의 실시예에 따른 스택 패키지가 구성되어 있다. As shown, a plurality of bonding pads (not shown) are formed on the upper surface, and a plurality of edge pad type semiconductor chips 110, 111, 112, and 113 having a smaller size from the bottom to the top to enable stacking are adhesives. Stacked on the printed circuit board 140 via the. In addition, the stacked chips 110, 111, 112, and 113, and the lowermost chip 113 and the printed circuit board 140 are connected to each other by a metal wire 120 made of gold (Au) or the like. Forming a path. In addition, a pyramidal encapsulant 160 is formed to protect the stacked chips 110, 111, 112, and 113 and the metal wire 120. The pyramid-shaped encapsulant 160 is formed on the bottom surface of the printed circuit board 140. A first solder ball 150 is attached to each borland (not shown) to form a stack package according to an embodiment of the present invention.

여기서, 상기 피라미드 형태의 봉지제(160)는 피라미드 형태을 가진 금형으로 제작할 수 있다. Here, the pyramid-type encapsulant 160 may be manufactured in a mold having a pyramid shape.

그리고, 상기 피라미드 형태의 봉지제(160)는 종래의 4각 박스 형태의 봉지제와 비교하여 봉지제의 양이 적고, 따라서, 열 방출에 용이하며, 경박단소한 특징을 가진다. In addition, the pyramidal encapsulant 160 has a smaller amount of encapsulant than a conventional quadrangular encapsulant, and therefore, is easy to dissipate heat and has a light and simple feature.

한편, 상기에서는 피라미드 형태의 봉지제를 가지는 스택 패키지에 대하여 설명하였고, 상기 본 발명의 실시예에 따른 스택 패키지를 이용하여 고밀도 멀티 패키지를 제조할 수 있다.Meanwhile, the stack package having a pyramid-type encapsulant has been described, and a high density multi-package can be manufactured using the stack package according to the embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 고밀도 멀티 패키지를 도시한 단면도이다.3 is a cross-sectional view showing a high density multi-package according to an embodiment of the present invention.

도시된 바와 같이, 전술된 본 발명의 실시예와 같이 제조된 스택 패키지들이 별도의 제1기판(170)에 나란히 마운팅되어 제1스택 패키지를 구성하고 있다. 그리고, 전술된 본 발명의 실시예와 같이 제조된 스택 패키지들이 플렉서블(Flexible)한 특성을 가지는 제2기판(180) 상에 나란히 마운팅되어 있는 제2스택 패키지가 상기 제1스택 패키지에 대응하여 역피라미드 형태의 엇갈린 구조로 적층되어 있다. 또한, 상기 플렉서블한 특성을 가지는 제2기판(180)의 양쪽 타단이 제1기판(170)에 접착 수단(240)으로 부착되어 있으며, 상기 제1기판(170)의 하면에는 제2솔더볼(190a)이 부착되어 고밀도 멀티 패키지가 구성된다.As shown, the stack packages manufactured as described above in the embodiment of the present invention are mounted side by side on a separate first substrate 170 to form a first stack package. In addition, a second stack package mounted side by side on the second substrate 180 having the flexible characteristics of the stack packages manufactured as described above may be reversed to correspond to the first stack package. Stacked in a pyramidal staggered structure. In addition, both ends of the second substrate 180 having the flexible characteristic are attached to the first substrate 170 by the adhesive means 240, and the second solder ball 190a is disposed on the bottom surface of the first substrate 170. ) Is attached to form a high density multi-package.

여기서, 제1기판(170) 및 제2기판(180)에 마운팅되는 스택 패키지의 수는 제한이 없으며, 제1기판(170)은 내부에 전기 신호의 전달을 위한 회로 패턴(미도시)이 내재되어 있고, 상면에 전극 단자(미도시)와 하면에 볼랜드(미도시)를 다수 구비하고 있으며, 제2기판(180)은 내부에 전기 도선(미도시)이 내재되어 있고 상면에 전극 단자(미도시)를 다수 구비하고 있다. Here, the number of stack packages mounted on the first substrate 170 and the second substrate 180 is not limited, and the first substrate 170 has a circuit pattern (not shown) for transmitting electrical signals therein. It is provided with a plurality of electrode terminals (not shown) on the upper surface and a plurality of borland (not shown) on the lower surface, the second substrate 180 is embedded with an electrical conductor (not shown) inside the electrode terminal (not shown) Many) are provided.

또한, 스택 패키지들에 부착되어 있는 다수의 제1솔더볼(150)은 제1기판(170)과 제2기판(180)의 전극 단자(미도시)에 부착되어 있고, 제2기판(180)은 유동성을 가지는 플레서블한 기판이기 때문에, 제1기판(170)과의 전기적인 연결을 위하여 구부릴 경우에도 전기적인 연결의 끊어짐 현상은 발생하지 않는다.In addition, the plurality of first solder balls 150 attached to the stack packages are attached to electrode terminals (not shown) of the first substrate 170 and the second substrate 180, and the second substrate 180 is Since it is a flexible substrate having fluidity, the breakage of the electrical connection does not occur even when bent for electrical connection with the first substrate 170.

그리고, 제2기판(180)의 양 끝단과 제1기판(170)은 솔더 등의 전도성 접착제 또는 고정핀 등과 같은 접합 수단(240)으로 연결되어 전기적 패스를 형성하고 물리적으로 접착된다.In addition, both ends of the second substrate 180 and the first substrate 170 are connected to each other by a bonding means 240 such as a conductive adhesive or a fixing pin, such as solder, to form an electrical path and physically bond.

또한, 피라미드 형태의 봉지제(160)를 가지는 스택 패키지가 마운팅된 제1 및 제2기판(170, 180)이 상호 엇갈린 형태로 적층될 때, 서로 대응하여 맞닿는 피라미드 형태의 봉지제(160) 면에 접착제를 개재하여 적층시킬 수 있다. In addition, when the stack package having the encapsulant 160 in the form of pyramids and the first and second substrates 170 and 180 mounted thereon are stacked in a staggered form, the surfaces of the encapsulant 160 in contact with each other correspond to each other. It can be laminated | stacked through the adhesive agent.

이와 같은, 본 발명의 고밀도 멀티 스택 패키지는 다수의 피라미드 형태의 봉지제를 가진 스택 패키지들로 서로 엇갈리는 형태를 적층되기 때문에 종래의 사각 박스 형태의 봉지제를 가진 멀티 패키지에 비하여 적층 면적을 줄일 수 있기 때문에 동일한 면적에 대하여 많은 수의 스택 패키지를 적층할 수 있다.As such, the high-density multi-stack package of the present invention can stack stacking forms with stack packages having a plurality of pyramidal encapsulants, thereby reducing the stacking area compared to a multi-package having a rectangular box-type encapsulant. As a result, a large number of stack packages can be stacked on the same area.

이하에서는 본 발명의 실시예에 따른 멀티 패키지의 제작 과정을 도 4a 내지 도 4c를 참조하여 설명하도록 한다.Hereinafter, a manufacturing process of a multi-package according to an embodiment of the present invention will be described with reference to FIGS. 4A to 4C.

먼저, 도 4a를 참조하면, 다수의 스택 패키지를 마운팅시킬 수 있을 정도의 크기를 가지고 상면과 하면에 각각 다수의 전극 단자(미도시)와 볼랜드(미도시)가 형성되어 있으며 내부에는 인쇄회로(미도시)가 내재된 제1기판을(170) 준비한다. First, referring to FIG. 4A, a plurality of electrode terminals (not shown) and borland (not shown) are formed on an upper surface and a lower surface of a size enough to mount a plurality of stack packages, and a printed circuit ( A first substrate 170 having an embedded therein is prepared.

이어서, 상기 제1기판(170) 상에 상기 도 3에 도시된 바와 같이 제작된 피라미드 형태의 봉지제(160)가 형성되어 있는 다수의 스택 패키지들을 나란히 마운팅시켜 제1스택 패키지(300)를 제조한다. 이때, 솔더링(Soldering) 공정을 이용하여 제1기판(170) 상에 형성된 전극 단자(미도시)에 상기 스택 패키지의 제1솔더볼(150)을 부착시킨다. Subsequently, the first stack package 300 is manufactured by mounting a plurality of stack packages in which a pyramidal encapsulant 160 formed on the first substrate 170 is formed as shown in FIG. 3. do. In this case, the first solder ball 150 of the stack package is attached to an electrode terminal (not shown) formed on the first substrate 170 using a soldering process.

그런 다음, 도 4b에 도시된 바와 같이, 다수의 스택 패키지를 배치시킬 수 있을 정도의 크기를 가지고 유동성을 가지는 플렉서블한 제2기판(180)에 피라미드 형태의 봉지제(160)가 형성되어 있는 다수의 스택 패키지를 나란히 마운팅시켜 제2스택 패키지(400)를 제조한다.Next, as shown in FIG. 4B, a plurality of pyramidal encapsulants 160 are formed on the flexible second substrate 180 having a size enough to arrange a plurality of stack packages and having fluidity. A stack package of 400 is mounted side by side to manufacture a second stack package 400.

이어서, 도 4c에 도시된 바와 같이, 상기 제2스택 패키지(400)를 뒤집어서 제1스택 패키지(300) 상에 위치시키고, 제1스택 패키지(300)와 제2스택 패키지(400)에 각각 마운팅되어 있는 피라미드 형태의 봉지제(160)가 상호 엇갈린 형태를 가지도록 하면서 적층시킨다. Subsequently, as shown in FIG. 4C, the second stack package 400 is inverted and positioned on the first stack package 300 and mounted on the first stack package 300 and the second stack package 400, respectively. Pyramidal encapsulant 160 is stacked while having a mutually staggered form.

그런 다음, 유동성을 가지는 플렉서블한 제2기판(180)의 양쪽 타단을 제1기 판(170) 방향으로 접고 솔더 등의 전도성 접착제 또는 고정 핀 등과 같은 접합 수단(240)으로 고정시켜 제1기판(170)과 제2기판(180) 사이에 전기적, 물리적 연결을 형성시킨다. Then, both ends of the flexible second substrate 180 having fluidity are folded in the direction of the first substrate 170 and fixed with a bonding means 240 such as a conductive adhesive or a fixing pin such as solder or the like. An electrical and physical connection is formed between the 170 and the second substrate 180.

마지막으로, 제1기판(170)의 하부에 위치한 볼랜드(미도시)에 외부와의 전기적인 연결을 위한 제2솔더볼(190a)을 부착시켜 고밀도 멀티 패키지를 완성한다.  Finally, the second solder ball 190a for electrical connection to the outside is attached to the borland (not shown) positioned below the first substrate 170 to complete the high density multi-package.

한편, 본 발명의 다른 실시예에 따른 고밀도 멀티 패키지를 도 5를 참조하여 설명한다.On the other hand, a high-density multi-package according to another embodiment of the present invention will be described with reference to FIG.

도시된 바와 같이, 상기 도 4a에서와 같이 제작된 피라미드 형태의 봉지제(160)를 가지는 스택 패키지가 제1기판에(170) 나란히 마운팅된 제1스택 패키지와, 상기 제1스택 패키지와 동일한 구조를 가지는 제2스택 패키지가 상기 제1스택 패키지와 대응하여 엇갈린 형태로 적층되어 있다. 그리고, 상기 적층된 제1 및 제2스택 패키지의 양측 끝단 사이는 각각 메탈 핀(210)과 부도체 물질(220)로 이루어진 지지체로 부착되어 있으며, 상기 제1스택 패키지의 제1기판(170) 하부에 위치한 볼랜드(미도시)에 외부와의 전기적인 연결을 위한 제3솔더볼(190b)을 부착되어 고밀도 멀티 패키지가 구성되어 있다.As shown in FIG. 4A, a stack package having a pyramidal encapsulant 160 manufactured as shown in FIG. 4A includes a first stack package mounted side by side on a first substrate 170, and the same structure as the first stack package. The second stack package having stacks stacked in a staggered manner corresponding to the first stack package. In addition, between the ends of both sides of the stacked first and second stack packages are attached to a support made of a metal pin 210 and a non-conductive material 220, respectively, and the lower portion of the first substrate 170 of the first stack package. A high density multi-package is formed by attaching a third solder ball 190b for electrical connection to the outside in Borland (not shown).

여기서, 지지체의 내부의 메탈 핀(210)은 제1스택 패키지와 제2스택 패키지 사이의 전기적인 패스를 형성하기 위하여 구리(Cu) 등으로 구성되어 있고, 외부를 형성하는 부도체 물질(220)은 제1스택 패키지와 제2스택 패키지로 이루어진 멀티 패키지 구조를 지지할 수 있을 정도로 단단하다. Here, the metal pin 210 inside the support is made of copper (Cu) or the like to form an electrical path between the first stack package and the second stack package, the non-conductive material 220 forming the outside is It is hard enough to support a multi-package structure comprising a first stack package and a second stack package.

그리고, 지지체로 솔더볼들을 적층시켜 사용할 수도 있다. In addition, solder balls may be stacked and used as a support.

본 발명들에 따르면, 피라미드 형태의 봉지제를 가진 다수의 스택 패키지들을 별도의 기판들 상에 마운팅시키고, 피라미드 형태의 봉지제를 가진 다수의 스택 패키지들이 서로 엇갈리는 형태를 가지도록 적층시킴으로써 종래의 사각 박스 형태의 봉지제를 가진 패키지가 마운팅된 멀티 패키지에 비하여 적층 면적을 줄일 수 있기 때문에, 동일한 면적에 대하여 많은 수의 스택 패키지를 적층할 수 있어 고밀도 멀티 패키지를 제작할 수 있다.According to the present invention, a plurality of stack packages having a pyramidal encapsulant are mounted on separate substrates, and a plurality of stack packages having a pyramidal encapsulant are stacked so as to cross each other. Since the package having a box-type encapsulant can reduce the stacking area as compared to the mounted multi-package, a large number of stack packages can be stacked on the same area, thereby producing a high density multi-package.

이상에서와 같이, 본 발명은 불필요한 면적을 줄인 피라미드 형태의 봉지제를 가진 스택 패키지들을 제작하고, 상기 스택 패키지들을 적층함으로써 경박단소한 고밀도 멀티 스택 패키지를 제작할 수 있다. As described above, the present invention can manufacture a stack package having a pyramidal encapsulant with unnecessary area, and by stacking the stack package, it is possible to manufacture a light and simple high density multi-stack package.

Claims (6)

상면에 배치되는 전극 단자 및 하면에 배치되는 볼랜드를 포함하여 회로 패턴이 구비된 인쇄회로 기판;A printed circuit board having a circuit pattern including an electrode terminal disposed on an upper surface and a ball land disposed on a lower surface thereof; 상기 인쇄회로 기판 상에 접착제를 매개로 하여 적층되며, 하부로부터 상부로 갈수록 작은 크기를 갖는 다수의 에지 패드형 반도체 칩;A plurality of edge pad type semiconductor chips stacked on the printed circuit board through an adhesive and having a smaller size from bottom to top; 상기 적층된 위/아래 반도체 칩들의 본딩 패드들간을 상호 연결함과 아울러 최하부에 배치된 반도체 칩의 본딩 패드와 인쇄회로 기판의 전극 단자를 상호 연결시키는 다수의 금속 와이어;A plurality of metal wires interconnecting the bonding pads of the stacked upper and lower semiconductor chips and interconnecting the bonding pads of the semiconductor chip disposed at the bottom and the electrode terminals of the printed circuit board; 상기 금속 와이어들 및 적층된 반도체 칩들을 포함한 기판 상면을 밀봉하는 피라미드 형태의 봉지제; 및A pyramidal encapsulant sealing the upper surface of the substrate including the metal wires and the stacked semiconductor chips; And 상기 인쇄회로 기판의 볼랜드에 부착된 솔더볼;A solder ball attached to a ball land of the printed circuit board; 포함하는 것을 특징으로 하는 스택 패키지.Stack package comprising a. 상면에 접속 패들들이 구비되고 하면에 볼랜드들이 구비된 제1기판;A first substrate having connection paddles on an upper surface thereof and ball lands on a lower surface thereof; 상기 제1기판 상에 나란하게 마운팅된 청구항1의 구성을 갖는 피라미드 형태의 제1스택 패키지들;First stack packages having a pyramid shape having a configuration of claim 1 mounted side by side on the first substrate; 상기 나란하게 마운팅된 제1스택 패키지들 사이마다 역피라미드 형태로 배치된 청구항1의 구성을 갖는 제2스택 패키지들;Second stack packages having the configuration of claim 1 disposed in an inverse pyramid form between the first and second stack packages mounted side by side; 상기 제2스택 패키지들 상에 배치되면서 상면에 전극 단자들이 구비되어 상 기 제2스택 패키지들이 마운팅됨과 아울러 제1기판과 전기적으로 연결된 제2기판; 및A second substrate disposed on the second stack packages and having electrode terminals disposed on an upper surface thereof to mount the second stack packages and to be electrically connected to the first substrate; And 상기 제1기판 하면의 볼랜드에 부착된 솔더볼;Solder balls attached to the ball land on the lower surface of the first substrate; 을 포함하고 것을 특징으로 하는 고밀도 멀티 패키지.High density multi-packages, characterized in that it comprises a. 제 2 항이 있어서,The method of claim 2, 상기 제1기판과 제2기판 사이에 개재되어 상호간을 전기적으로 연결시키는 연결핀을 더 포함하는 것을 특징으로 하는 고밀도 멀티 패키지.And a connection pin interposed between the first substrate and the second substrate to electrically connect each other. 제 3 항에 있어서,The method of claim 3, wherein 상기 연결핀의 연결부위에 형성된 솔더를 더 포함하는 것을 특징으로 하는 고밀도 멀티 패키지.The high density multi-package, characterized in that it further comprises a solder formed on the connection portion of the connecting pin. 제 2 항에 있어서,The method of claim 2, 상기 제2기판은 플렉서블 한 재질로 이루어져 그 가장자리의 전극 단자가 제1기판의 전극 단자와 직접 연결된 플러서블 기판인 것을 특징으로 하는 고밀도 멀티 패키지.The second substrate is made of a flexible material, the electrode terminal of the edge of the high density multi-package, characterized in that the flexible substrate directly connected to the electrode terminal of the first substrate. 제 5 항에 있어서,The method of claim 5, 상기 제1기판과 제2기판간 연결부위에 형성된 솔더를 더 포함하는 것을 특징 으로 하는 고밀도 멀티 패키지.The high-density multi-package further comprises a solder formed on the connection portion between the first substrate and the second substrate.
KR1020060095097A 2006-09-28 2006-09-28 Stack package and hi-density multi package using the same KR20080029273A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105185755A (en) * 2014-06-13 2015-12-23 矽品精密工业股份有限公司 Package structure and method for fabricating the same
KR20170008958A (en) * 2015-07-15 2017-01-25 주식회사 에스에프에이반도체 Stacked semiconductor package and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105185755A (en) * 2014-06-13 2015-12-23 矽品精密工业股份有限公司 Package structure and method for fabricating the same
KR20170008958A (en) * 2015-07-15 2017-01-25 주식회사 에스에프에이반도체 Stacked semiconductor package and method for manufacturing the same

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