KR20030047403A - Ball grid array type stack package - Google Patents
Ball grid array type stack package Download PDFInfo
- Publication number
- KR20030047403A KR20030047403A KR1020010077883A KR20010077883A KR20030047403A KR 20030047403 A KR20030047403 A KR 20030047403A KR 1020010077883 A KR1020010077883 A KR 1020010077883A KR 20010077883 A KR20010077883 A KR 20010077883A KR 20030047403 A KR20030047403 A KR 20030047403A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- package
- substrate
- attached
- lead
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 칩 패키지에 관한 것으로서, 더욱 상세하게는 기판에 반도체 칩이 실장된 단위 반도체 칩 패키지가 복수 개 수직으로 적층되고 외부접속단자가 면 배열되어 있는 볼 그리드 어레이형 적층 패키지에 관한 것이다.The present invention relates to a semiconductor chip package, and more particularly, to a ball grid array multilayer package in which a plurality of unit semiconductor chip packages in which semiconductor chips are mounted on a substrate are vertically stacked and external connection terminals are arranged in a plane.
최근에 반도체 산업의 발전 그리고 사용자의 요구에 따라 전자 기기는 더욱 더 소형화 및 경량화가 요구되고 있다. 이에 따라, 개발된 기술 중의 하나가 용량과 실장밀도의 증가를 위하여 여러 개의 단위 반도체 소자 또는 단위 반도체 칩 패키지를 적층시키는 형태의 3차원 적층 기술이다.Recently, in accordance with the development of the semiconductor industry and the demands of users, electronic devices are increasingly required to be smaller and lighter. Accordingly, one of the developed technologies is a three-dimensional stacking technology in which a plurality of unit semiconductor devices or unit semiconductor chip packages are stacked in order to increase capacity and mounting density.
3차원 적층 기술로 제조되는 패키지는 일반적으로 3차원 패키지라 일컬으며 IBM에서 최초로 소개되었다. 이러한 3차원 패키지 기술은 고집적도를 구현할 수 있다는 장점 외에도 전체적인 상호연결(interconnection)의 길이를 감소시킴으로써 전기적 특성 향상 및 저전력 소비 등의 장점이 있다. 이러한 적층 기술의 구현에 있어서 패키징(packaging)되지 않은 반도체 소자를 여러 개 적층시키는 기술은 신뢰성이 입증된 노운 굿 다이(known good die)의 제조 기술이 선행되어야 하는 등 여러 가지 필요한 기술이 요구된다. 따라서, 개별적으로 조립공정이 완료된 단위 반도체 칩 패키지를 여러 개 적층하여 구성되는 패키지 적층 기술이 현실적으로 실현 가능성이 높다. 3차원 적층 기술이 적용된 대표적인 예로 적층 패키지를 소개하기로 한다. 동일한 기억용량의 반도체 칩 패키지를 3차원적으로 다수 개 적층하여 구성되는 적층 패키지에 대한 예가 도 1에 도시되어 있다.Packages manufactured with three-dimensional stacking technology are commonly referred to as three-dimensional packages and were first introduced by IBM. In addition to the high integration, the three-dimensional package technology has advantages such as improved electrical characteristics and low power consumption by reducing the overall interconnect length. In the implementation of such a stacking technology, a technique for stacking a plurality of unpacked semiconductor devices requires a number of necessary technologies, such as manufacturing a known good die, which has proven reliability. Therefore, there is a high possibility of realizing a package stacking technique composed of a plurality of unit semiconductor chip packages in which individual assembly processes are completed. As a representative example of three-dimensional lamination technology, a lamination package will be introduced. An example of a stack package formed by stacking a plurality of semiconductor chip packages having the same storage capacity in three dimensions is shown in FIG. 1.
도 1은 종래 기술에 따른 적층 패키지의 일 예를 나타낸 단면도이다.1 is a cross-sectional view showing an example of a laminated package according to the prior art.
도 1을 참조하면, 이 적층 패키지(450)는 도 1에 도시된 바와 같이 단위 반도체 칩 패키지(451)가 적어도 2개 이상 수직으로 적층되어 각 단위 반도체 칩 패키지(451)들의 외부리드(457)가 서로 접합되어 전기적인 연결을 이루고 있는 구조이다. 각 단위 반도체 칩 패키지(451)들의 구조는 일반적인 리드프레임의 내부리드(455)에 반도체 칩(453)이 실장되고, 그 반도체 칩(453)의 전극패드(도시 안됨)와 내부리드(455)가 도전성 금속선(459)으로 와이어 본딩(wire bonding)되어 전기적 접속을 이루며, 반도체 칩(453)을 포함하여 전기적인 접합 부위가 에폭시 성형 수지(EMC; Epoxy Molding Compound)와 같은 수지 봉지재로 형성된 봉지부(461)에 의해 봉지되어 외부 환경요소로부터 물리적으로나 화학적으로 보호되는 구조이다.Referring to FIG. 1, the multilayer package 450 includes at least two unit semiconductor chip packages 451 vertically stacked as illustrated in FIG. 1, so that the external leads 457 of the unit semiconductor chip packages 451 are stacked. Are bonded to each other to form an electrical connection. Each unit semiconductor chip package 451 has a structure in which a semiconductor chip 453 is mounted on an inner lead 455 of a general lead frame, and an electrode pad (not shown) and an inner lead 455 of the semiconductor chip 453 are mounted. An encapsulation portion formed of a resin encapsulation material such as an epoxy molding compound (EMC) is formed by wire bonding with the conductive metal wire 459 to form an electrical connection, and an electrical bonding portion including the semiconductor chip 453. It is enclosed by 461 to be physically and chemically protected from external environmental elements.
그러나, 이와 같이 리드프레임을 이용하는 구조의 적층 패키지는 외부 접속단자로서 핀의 배열에 한계가 있기 때문에 많은 핀 수가 요구되는 제품에 제한적으로 사용될 수밖에 없다. 이의 극복을 위하여, 면 배열 배치된 외부접속단자를 갖는 형태의 단위 반도체 칩 패키지 복수 개를 적층하는 방안이 연구되고 있으나 기판 에 면 배열되어 있는 솔더 볼로 인하여 적층하기가 어려웠다.However, since the stack package having the structure using the lead frame has a limitation in the arrangement of the pins as external connection terminals, it is inevitably limited to products requiring a large number of pins. In order to overcome this problem, a method of stacking a plurality of unit semiconductor chip packages having an external connection terminal arranged in a plane has been studied, but it has been difficult to stack due to solder balls arranged in a plane on a substrate.
따라서 본 발명의 목적은 기판을 이용하여 핀 수의 증가에 대한 대응이 유리하도록 외부 접속 단자가 면 배열 배치되는 구조의 적층 패키지를 제공하는 데 있다.Accordingly, it is an object of the present invention to provide a laminated package having a structure in which external connection terminals are arranged face to face to increase the number of pins by using a substrate.
도 1은 종래 기술에 따른 적층 패키지의 일 예를 나타낸 단면도,1 is a cross-sectional view showing an example of a laminated package according to the prior art,
도 2는 본 발명에 따른 적층 패키지의 제 1실시예를 나타낸 단면도,2 is a cross-sectional view showing a first embodiment of a laminated package according to the present invention;
도 3은 본 발명에 따른 적층 패키지의 제 2실시예를 나타낸 단면도,3 is a cross-sectional view showing a second embodiment of a laminated package according to the present invention;
도 4는 본 발명에 따른 적층 패키지의 제 3실시예를 나타낸 단면도,4 is a cross-sectional view showing a third embodiment of a laminated package according to the present invention;
도 5는 본 발명에 따른 적층 패키지의 제 4실시예를 나타낸 단면도이다.5 is a cross-sectional view showing a fourth embodiment of a laminated package according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10; 적층 패키지20,40; 단위 반도체 칩 패키지10; Laminated packages 20, 40; Unit semiconductor chip package
21,41; 반도체 칩23,43; 본딩패드21,41; Semiconductor chips 23 and 43; Bonding pad
24; 접착제25,45; 기판24; Adhesive 25,45; Board
27,28,47,48; 금속배선27a,47a; 기판 본딩패드27,28,47,48; Metal wiring 27a and 47a; Board Bonding Pad
29; 볼 패드31,51; 리드29; Ball pads 31 and 51; lead
33,53; 본딩와이어35,55; 봉지부33,53; Bonding wires 35,55; Encapsulation
57; 솔더 볼57; Solder ball
이와 같은 목적을 달성하기 위한 본 발명에 따른 볼 그리드 어레이형 적층 패키지는, 복수의 본딩패드가 형성된 반도체 칩, 그 반도체 칩이 실장되어 있으며금속배선이 형성된 기판, 기판 가장자리에 부착되어 기판의 측면 방향으로 소정 길이만큼 돌출된 리드, 반도체 칩과 리드를 전기적으로 연결하는 본딩와이어, 및 반도체 칩과 본딩와이어 및 그 접합된 부분을 봉지하는 봉지부를 포함하는 단위 반도체 칩 패키지 복수 개가, 상위 반도체 칩 패키지의 리드가 절곡되어 하위 반도체 칩 패키지의 리드에 부착되어 수직으로 적층되어 있고 최하위 반도체 칩 패키지의 기판에 외부접속단자가 면 배열되어 부착되어 있는 것을 특징으로 한다.The ball grid array stack package according to the present invention for achieving the above object is a semiconductor chip having a plurality of bonding pads, the semiconductor chip is mounted and the metal wiring is formed, the substrate is attached to the edge of the substrate side direction A plurality of unit semiconductor chip packages including a lead projecting by a predetermined length, a bonding wire for electrically connecting the semiconductor chip and the lead, and an encapsulation portion for encapsulating the semiconductor chip, the bonding wire, and a bonded portion thereof. The leads are bent, attached to the leads of the lower semiconductor chip package, stacked vertically, and the external connection terminals are arranged side by side to the substrate of the lowermost semiconductor chip package.
이하 첨부 도면을 참조하여 본 발명에 따른 볼 그리드 어레이형 적층 패키지를 보다 상세하게 설명하고자 한다.Hereinafter, a ball grid array stack package according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 적층 패키지의 제 1실시예를 나타낸 단면도이다. 도 2에 도시된 본 발명에 따른 적층 패키지(10)는 기판(25,45)에 반도체 칩(21,41)이 실장된 구조의 단위 반도체 칩 패키지(20,40) 2개가 수직으로 적층된 구조로서, 단위 반도체 칩 패키지들(20,40)간의 전기적인 연결은 기판(25)에 부착된 리드(31,51)를 이용하며 외부접속단자로서 하부 반도체 칩 패키지(40)의 기판(45)에 부착된 솔더 볼(57)을 이용한다. 각각의 기판(25,45)에 실장되는 반도체 칩들(21,41)은 모두 에지패드형(edge pad type)이다. 기판(25,45)은 상면과 하면에 금속배선(27,28,47,48)이 형성되어 있으며 상면에서 반도체 칩(21,41) 주변에는 금속배선(27,47)에서 와이어 본딩을 위해 마련된 기판 본딩패드(27a,47a)가 형성되어 있다. 그리고, 기판(25,45)의 하면에는 금속배선(28,48)과 연결되어 솔더 볼(57)이 부착될 수 있는 볼 패드(29,49)가 형성되어 있다.2 is a cross-sectional view showing a first embodiment of a laminated package according to the present invention. In the multilayer package 10 according to the present invention shown in FIG. 2, two unit semiconductor chip packages 20 and 40 having a structure in which semiconductor chips 21 and 41 are mounted on substrates 25 and 45 are vertically stacked. As an electrical connection between the unit semiconductor chip packages 20 and 40, the leads 31 and 51 attached to the substrate 25 are used and the external connection terminal is connected to the substrate 45 of the lower semiconductor chip package 40. Attached solder balls 57 are used. The semiconductor chips 21 and 41 mounted on the respective substrates 25 and 45 are all edge pad type. The substrates 25 and 45 have metal wirings 27, 28, 47, and 48 formed on the upper and lower surfaces thereof, and are provided for wire bonding in the metal wirings 27 and 47 around the semiconductor chips 21 and 41 on the upper surface. Substrate bonding pads 27a and 47a are formed. In addition, ball pads 29 and 49 are formed on lower surfaces of the substrates 25 and 45 to be connected to the metal wires 28 and 48 and to which the solder balls 57 may be attached.
상부 반도체 칩 패키지(20)는 기판(25)의 상면 가장자리에서 금속배선(27)에전기 전도성 재질의 리드(31)가 부착되어 있다. 이 리드(31)는 기판(25)의 측면 방향으로 일정 길이만큼 돌출되고 일정 부분이 하향 절곡이 된다. 또한, 하부 반도체 칩 패키지(40)는 기판(45)의 상면 가장자리에서 금속배선(47)에 리드(51)가 부착되어 있으며 기판(45)의 측면 방향으로 일정 길이만큼 돌출되어 있다. 하부 반도체 칩 패키지(40)에 부착된 리드(51)는 상부 반도체 칩 패키지(20)에 부착된 리드(27)와 동일한 것이 부착된 후 절단에 의해 형성될 수 있다. 상부 반도체 칩 패키지(20)와 하부 반도체 칩 패키지(40)의 리드(31,51)는 각각 그에 대응되는 반도체 칩(21,41)의 본딩패드(23,43)와 도전성 재질의 본딩와이어(33,53)에 의해 전기적으로 연결된다. 반도체 칩(21,41)과 본딩와이어(33,53) 및 그 접합 부분을 포함하여 기판(25,45)의 상부가 에폭시 성형 수지와 같은 수지 성형재로 형성되는 봉지부(35,55)에 의해 봉지된다.In the upper semiconductor chip package 20, a lead 31 of an electrically conductive material is attached to the metal wire 27 at the upper edge of the substrate 25. The lead 31 protrudes by a predetermined length in the lateral direction of the substrate 25 and the predetermined portion is bent downward. In addition, the lower semiconductor chip package 40 has a lead 51 attached to the metal wire 47 at the upper edge of the substrate 45 and protrudes by a predetermined length in the lateral direction of the substrate 45. The lead 51 attached to the lower semiconductor chip package 40 may be formed by cutting after the same thing as the lead 27 attached to the upper semiconductor chip package 20 is attached. Leads 31 and 51 of the upper semiconductor chip package 20 and the lower semiconductor chip package 40 are respectively bonded to the bonding pads 23 and 43 of the semiconductor chips 21 and 41 and the bonding wires 33 of a conductive material. 53 is electrically connected. The upper portions of the substrates 25 and 45, including the semiconductor chips 21 and 41, the bonding wires 33 and 53, and the bonding portions thereof, are formed in the encapsulation portions 35 and 55 formed of a resin molding material such as an epoxy molding resin. It is sealed by.
상부 반도체 칩 패키지(20)와 하부 반도체 칩 패키지(40)의 적층은 상부 반도체 칩 패키지(20)의 리드(31)가 하부 반도체 칩 패키지(40)의 리드(51)에 부착되어 이루어진다. 리드들(31,51)간의 부착은 솔더링(soldering)에 의하여 이루어질 수 있다. 이와 같은 적층에 의하여 상부 반도체 칩 패키지(20)와 하부 반도체 칩 패키지(40)가 전기적으로 연결된다. 한편, 하부 반도체 칩 패키지(40)의 기판 하면에 형성된 볼 패드(49)에 솔더 볼이 부착되어 적층 패키지가 외부와의 전기적인 연결 통로로 제공된다.The stack of the upper semiconductor chip package 20 and the lower semiconductor chip package 40 is formed by attaching the lead 31 of the upper semiconductor chip package 20 to the lead 51 of the lower semiconductor chip package 40. Attachment between the leads 31 and 51 may be made by soldering. By this lamination, the upper semiconductor chip package 20 and the lower semiconductor chip package 40 are electrically connected. Meanwhile, solder balls are attached to the ball pads 49 formed on the lower surface of the substrate of the lower semiconductor chip package 40 so that the laminated package is provided as an electrical connection passage to the outside.
전술한 제 1실시예와 같이 본 발명에 따른 적층 패키지는, 기판에 반도체 칩이 실장된 단위 반도체 칩 패키지의 적층 구조로서 최하위의 반도체 칩 패키지에서기판 하면에 솔더 볼과 같은 외부접속단자를 면 배열 할 수 있어 핀 수 증가에 대등할 수 있다.As in the first embodiment described above, the multilayer package according to the present invention is a laminated structure of a unit semiconductor chip package in which a semiconductor chip is mounted on a substrate, and in the lowermost semiconductor chip package, external connection terminals such as solder balls are arranged on the lower surface of the substrate. You can do this to match the increase in pin count.
도 3은 본 발명에 따른 적층 패키지의 제 2실시예를 나타낸 단면도이다. 도 3에 도시된 적층 패키지(110)는 전술한 제 1실시예와 유사한 구조를 가지고 있으나 리드 부착 위치에서 차이가 있다. 상부 반도체 칩 패키지(120)에서 리드(131)는 기판(125)의 하면에 형성된 금속배선(128) 부착된다. 그리고, 하부 반도체 칩 패키지(140)에서 리드(151) 또한 기판(145)의 하면에 형성된 금속배선(148)에 부착된다. 절곡된 상부 반도체 칩 패키지(120)의 리드(131)가 절단된 하부 반도체 칩 패키지(140)의 리드(151)에 부착되어 적층이 이루어진다. 패키지 두께 감소를 위하여 하부 반도체 칩 패키지(140)의 봉지부(155)가 상부 반도체 칩 패키지(120)의 기판(125)에 밀착되어 적층된다. 상부 반도체 칩 패키지(120)의 리드(131)는 이에 적합한 높이를 갖도록 형성된다.3 is a cross-sectional view showing a second embodiment of a laminated package according to the present invention. The stack package 110 shown in FIG. 3 has a structure similar to that of the first embodiment described above, but there is a difference in a lead attachment position. In the upper semiconductor chip package 120, the leads 131 are attached to the metal wires 128 formed on the bottom surface of the substrate 125. In the lower semiconductor chip package 140, the lead 151 is also attached to the metal wire 148 formed on the bottom surface of the substrate 145. The lead 131 of the bent upper semiconductor chip package 120 is attached to the lead 151 of the cut lower semiconductor chip package 140 to form a stack. In order to reduce the thickness of the package, the encapsulation portion 155 of the lower semiconductor chip package 140 is stacked on the substrate 125 of the upper semiconductor chip package 120. The lead 131 of the upper semiconductor chip package 120 is formed to have a height suitable for this.
제 2실시예에서와 같이 본 발명에 따른 적층 패키지는 리드의 위치가 변화될 수 있다. 제 1실시예에서 리드의 위치가 기판 상면인 것을 소개하였고 제 2실시예에서 기판 하면인 것을 소개하였으나 이에 한정되지 않는다. 즉, 리드가 기판 상면과 하면 중 어느 한 면에 형성되기만 하면 된다.As in the second embodiment, in the laminated package according to the present invention, the position of the lead may be changed. In the first embodiment, the position of the lead is introduced as the upper surface of the substrate, and in the second embodiment, the lower surface of the substrate is introduced, but is not limited thereto. That is, the lead only needs to be formed on either of the upper and lower surfaces of the substrate.
도 4는 본 발명에 따른 적층 패키지의 제 3실시예를 나타낸 단면도이다. 도 4에 도시된 적층 패키지(210)는 전술한 실시예와는 달리 3개의 단위 반도체 칩 패키지(220,240,260)가 적층된 구조이다. 최하위의 반도체 칩 패키지(260)는 기판(265)에 리드(271)가 부착되어 있고 기판 하면에 솔더 볼(275)이 부착되어 있는 구조이다. 그리고, 상위 반도체 칩 패키지들(220,240)은 리드(231,251)가 기판(225,245)의 상면에 부착되어 있으며 돌출된 부분은 절곡되어 있고 기판(225,245) 하면에 솔더 볼이 부착되지 않은 구조를 갖는다.4 is a cross-sectional view showing a third embodiment of a laminated package according to the present invention. Unlike the above-described embodiment, the stack package 210 illustrated in FIG. 4 has a structure in which three unit semiconductor chip packages 220, 240, and 260 are stacked. The lowermost semiconductor chip package 260 has a structure in which a lead 271 is attached to the substrate 265 and solder balls 275 are attached to the lower surface of the substrate. The upper semiconductor chip packages 220 and 240 have a structure in which leads 231 and 251 are attached to upper surfaces of the substrates 225 and 245, protruding portions are bent, and solder balls are not attached to the lower surfaces of the substrates 225 and 245.
제 3실시예에서와 같이 본 발명에 따른 적층 패키지는 최하위의 반도체 칩 패키지가 절단된 형태의 리드가 부착되고 솔더 볼이 부착된 구조를 갖도록 하기만 하면 솔더 볼이 부착되지 않고 절곡된 리드가 부착된 형태를 갖는 다수의 단위 반도체 칩 패키지가 적층될 수 있다.As in the third embodiment, the laminated package according to the present invention has a structure in which a lowermost semiconductor chip package is attached with a cut lead and a solder ball is attached, and a solder lead is not attached and a bent lead is attached. A plurality of unit semiconductor chip packages having a predetermined shape may be stacked.
도 5는 본 발명에 따른 적층 패키지의 제 4실시예를 나타낸 단면도이다. 도 5에 도시된 본 발명에 따른 적층 패키지(310)는 전술한 실시에와 달리 하위 반도체 칩 패키지(320)의 기판(325)에 부착된 리드(331)가 상향 절곡되어 있다. 그리고, 하위 반도체 칩 패키지(320) 상부에 리드프레임을 이용하는 형태의 반도체 칩 패키지(340)가 적층되어 있는 구조이다.5 is a cross-sectional view showing a fourth embodiment of a laminated package according to the present invention. In the multilayer package 310 according to the present invention illustrated in FIG. 5, the lead 331 attached to the substrate 325 of the lower semiconductor chip package 320 is bent upwardly, unlike the above-described embodiment. The semiconductor chip package 340 having a lead frame is stacked on the lower semiconductor chip package 320.
상부 반도체 칩 패키지(340)는 다이패드(345)에 반도체 칩(341)이 실장되어 있고 그 주변에 내부리드(347a)가 형성되어 있으며 본딩와이어(353)에 의해 반도체 칩(341)과 내부리드(347a)가 와이어 본딩되어 전기적으로 연결되어 있다. 내부리드(347a)와 일체형으로 형성되며 수지 봉지재로 형성되는 봉지부(355)의 외부로 돌출된 외부리드(347b)가 적층에 적합한 형상으로 성형되어 있다. 이 외부리드(347b)가 하위 반도체 칩 패키지(320)의 리드(331)와 접합되어 있다.In the upper semiconductor chip package 340, a semiconductor chip 341 is mounted on a die pad 345, and an inner lead 347a is formed around the semiconductor chip 341, and the semiconductor chip 341 and the inner lead are formed by bonding wires 353. 347a is wire bonded and electrically connected. The outer lead 347b, which is formed integrally with the inner lead 347a and protrudes to the outside of the encapsulation portion 355 formed of a resin encapsulation material, is molded into a shape suitable for lamination. The external lead 347b is bonded to the lead 331 of the lower semiconductor chip package 320.
제 4실시예에서와 같이 본 발명에 따른 적층 패키지는 최하위 반도체 칩 패키지로서 기판을 채택하고 그 기판에 리드가 부착되어 있으며 외부접속단자가 면배열된 반도체 칩 패키지를 사용함으로써 기판을 채택하지 않는 일반적인 구조의 반도체 칩 패키지를 적층하여 적층 패키지의 구현이 가능하다.As in the fourth embodiment, the laminated package according to the present invention adopts a substrate as a lowermost semiconductor chip package, has a lead attached to the substrate, and does not adopt a substrate by using a semiconductor chip package in which external connection terminals are face-arrayed. A stack package may be implemented by stacking a semiconductor chip package having a structure.
이상과 같이 본 발명에 의한 적층 패키지에 따르면, 기판을 이용하여 핀 수의 증가에 대한 대응할 수 있는 볼 그리드 어레이형 적층 패키지의 구현이 가능하다.As described above, according to the stacking package according to the present invention, it is possible to implement a ball grid array stacking package that can cope with an increase in the number of pins by using a substrate.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010077883A KR20030047403A (en) | 2001-12-10 | 2001-12-10 | Ball grid array type stack package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010077883A KR20030047403A (en) | 2001-12-10 | 2001-12-10 | Ball grid array type stack package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030047403A true KR20030047403A (en) | 2003-06-18 |
Family
ID=29574022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010077883A KR20030047403A (en) | 2001-12-10 | 2001-12-10 | Ball grid array type stack package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030047403A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7253025B2 (en) | 2000-08-09 | 2007-08-07 | Micron Technology, Inc. | Multiple substrate microelectronic devices and methods of manufacture |
| US8067827B2 (en) | 2000-08-23 | 2011-11-29 | Micron Technology, Inc. | Stacked microelectronic device assemblies |
-
2001
- 2001-12-10 KR KR1020010077883A patent/KR20030047403A/en active IP Right Grant
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7253025B2 (en) | 2000-08-09 | 2007-08-07 | Micron Technology, Inc. | Multiple substrate microelectronic devices and methods of manufacture |
| US7298031B1 (en) | 2000-08-09 | 2007-11-20 | Micron Technology, Inc. | Multiple substrate microelectronic devices and methods of manufacture |
| US8067827B2 (en) | 2000-08-23 | 2011-11-29 | Micron Technology, Inc. | Stacked microelectronic device assemblies |
| US8587109B2 (en) | 2000-08-23 | 2013-11-19 | Micron Technology, Inc. | Stacked microelectronic dies and methods for stacking microelectronic dies |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100753415B1 (en) | Stack package | |
| KR100621991B1 (en) | Chip scale stack package | |
| US6781240B2 (en) | Semiconductor package with semiconductor chips stacked therein and method of making the package | |
| US20040183173A1 (en) | Semiconductor device | |
| US7829990B1 (en) | Stackable semiconductor package including laminate interposer | |
| US20020113325A1 (en) | Semiconductor package and mounting structure on substrate thereof and stack structure thereof | |
| KR100673379B1 (en) | Stack package and manufacturing method thereof | |
| JP4435756B2 (en) | Semiconductor device | |
| KR101450758B1 (en) | Integrated circuit package | |
| KR100788341B1 (en) | Chip Stacked Semiconductor Package | |
| KR20010073345A (en) | Stack package | |
| KR100351922B1 (en) | Semiconductor package amd method of manufacturing the same | |
| KR20030047403A (en) | Ball grid array type stack package | |
| KR20000040586A (en) | Multi chip package having printed circuit substrate | |
| KR100437821B1 (en) | semiconductor package and metod for fabricating the same | |
| KR100650049B1 (en) | Assembly-stacked package using multichip module | |
| KR20010027266A (en) | Stack package | |
| KR20010068781A (en) | Semiconductor chip package | |
| KR100376884B1 (en) | Stack package | |
| KR20080029273A (en) | Stack package and hi-density multi package using the same | |
| KR100480908B1 (en) | method for manufacturing stacked chip package | |
| KR100708050B1 (en) | semiconductor package | |
| KR20030055834A (en) | Ball grid array type semiconductor chip package using leadframe and stack package | |
| KR100525450B1 (en) | Chip Stack Type Semiconductor Package | |
| KR100650770B1 (en) | Flip chip double die package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| NORF | Unpaid initial registration fee |