KR20070000181A - Chip stack package - Google Patents

Chip stack package Download PDF

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Publication number
KR20070000181A
KR20070000181A KR1020050055713A KR20050055713A KR20070000181A KR 20070000181 A KR20070000181 A KR 20070000181A KR 1020050055713 A KR1020050055713 A KR 1020050055713A KR 20050055713 A KR20050055713 A KR 20050055713A KR 20070000181 A KR20070000181 A KR 20070000181A
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South Korea
Prior art keywords
semiconductor chip
bonding
substrate
metal wire
attached
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KR1020050055713A
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Korean (ko)
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현문언
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주식회사 하이닉스반도체
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Priority to KR1020050055713A priority Critical patent/KR20070000181A/en
Publication of KR20070000181A publication Critical patent/KR20070000181A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

A chip stack package is provided to reduce a height thereof and stack a plurality of semiconductor chips by minimizing a loop of a metal wire. A substrate(110) includes a bond finger(111), bonding balls, and a ball land(112). A first semiconductor chip(130) is attached on the substrate. A first epoxy(132) is attached to both edges of the first semiconductor chip. A plurality of bonding balls(113,133) are formed on a bonding pad(131) of the first semiconductor chip. A first metal wire(134) is used for connecting electrically the bonding balls of the first semiconductor chip with the bonding balls of the substrate. A first fixing agent(140) is formed on the first semiconductor chip in order to fix the first metal wire. A second semiconductor chip(160) is attached to the first semiconductor chip. A second epoxy is attached to the second semiconductor chip. A plurality of bonding balls(163) are formed on a bonding pad of the second semiconductor chip. A second metal wire(164) is used for connecting electrically the bonding balls of the second semiconductor chip with the bonding balls of the substrate. A second fixing agent(170) is formed on the second semiconductor chip in order to fix the second metal wire. A sealant(180) is used for sealing the substrate and the second fixing agent. A solder ball(190) is attached on the ball land.

Description

칩 스택 패키지{Chip stack package}Chip stack package

본 발명은 반도체 패키지에 관한 것으로, 금속 와이어의 루프(loop)를 최소화하여, 패키지의 높이를 감소시키는 칩 스택 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and to a chip stack package that minimizes the loop of metal wires, thereby reducing the height of the package.

전기·전자 제품의 소형화와 더불어 고성능화가 요구됨에 따라, 고용량의 반도체 모듈을 제공하기 위한 다양한 기술들이 연구 개발되고 있다. 고용량의 반도체 모듈을 제공하기 위한 방법으로서는 메모리 칩의 용량 증대, 다시 말해, 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간 내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. 그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선 폭을 요구하는 등, 고난도의 기술과 많은 개발 시간을 필요로 한다. 따라서, 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서 칩 스택(stack) 기술이 제안되었다. As miniaturization of electric and electronic products and high performance are required, various technologies for providing high capacity semiconductor modules have been researched and developed. A method for providing a high-capacity semiconductor module may include increasing the capacity of a memory chip, that is, high integration of the memory chip, which may be realized by integrating a larger number of cells in a limited space of a semiconductor chip. Can be. However, such high integration of the memory chip requires a high level of technology and a lot of development time, such as requiring a fine fine line width. Therefore, a chip stack technology has been proposed as another method for providing a high capacity semiconductor module.

이러한 칩 스택 기술은 적어도 2개 이상의 반도체 칩을 수직으로 쌓아 올리는 것으로서, 이러한 칩 스택 기술에 의한 칩 스택 패키지는 메모리 용량 증대는 물론, 실장 밀도 및 실장 면적 사용의 효율성 측면에서 이점이 있다. The chip stack technology stacks at least two semiconductor chips vertically, and the chip stack package according to the chip stack technology has advantages in terms of increasing memory capacity and efficiency of mounting density and mounting area.

이하에서는 도 1을 참조하여 종래의 칩 스택 패키지에 관하여 설명하도록 한다. 참고로, 도 1과 같은 구조를 업-업 타입 칩 스택 패키지라고 한다. Hereinafter, a conventional chip stack package will be described with reference to FIG. 1. For reference, the structure shown in FIG. 1 is called an up-up type chip stack package.

도시된 바와 같이, 종래의 업-업 타입 칩 스택 패키지는 회로패턴이 구비된 기판(10) 상에 접착제(20)를 매개로 센터 패드형의 제 1 반도체 칩(30)이 페이스 업 타입으로 부착되고, 제 1 반도체 칩(30)의 본딩 패드(31)와 기판(10)의 본드 핑거(11)는 제 1 금속 와이어(32)에 의해 전기적으로 연결된다. 그리고, 제 1 반도체 칩(30) 상부는 상기 제 1 금속 와이어(32)를 보호하기 위한 고정제(40)가 형성된다. 또한, 고정제(40) 상부에는 접착제(50)를 매개로 센터 패드형 제 2 반도체 칩(60)이 페이스 업 타입으로 부착되고, 제 2 반도체 칩(60)의 본딩 패드(61)와 기판(10)의 본드 핑거(11)는 제 2 금속 와이어(62)에 의해 전기적으로 연결된다. 이 후, 제 2 반도체 칩(60) 상부에는 제 2 금속 와이어(62)를 보호하기 위한 고정제(70)가 형성되며, 기판 상부면을 포함한 고정제(70)의 상부면은 봉지제(80)에 의해 밀봉되고, 기판 하부면에는 솔더 볼(90)이 부착된다.As shown in the drawing, the conventional up-up type chip stack package attaches the center pad-type first semiconductor chip 30 to the face-up type on the substrate 10 provided with the circuit pattern via the adhesive 20. The bonding pad 31 of the first semiconductor chip 30 and the bond finger 11 of the substrate 10 are electrically connected by the first metal wire 32. In addition, a fixing agent 40 for protecting the first metal wire 32 is formed on the first semiconductor chip 30. In addition, the center pad type second semiconductor chip 60 is attached to the upper part of the fixing agent 40 by an adhesive 50 in a face up type, and the bonding pad 61 of the second semiconductor chip 60 and the substrate ( The bond finger 11 of 10 is electrically connected by the second metal wire 62. Thereafter, a fixing agent 70 for protecting the second metal wire 62 is formed on the second semiconductor chip 60, and an upper surface of the fixing agent 70 including the upper surface of the substrate is encapsulant 80. ) And a solder ball 90 is attached to the lower surface of the substrate.

이와 같은 구성을 갖는, 종래의 업-업 타입 칩 스택 패키지는 제 1 및 제 2 반도체 칩의 본딩 패드(31,61)와 기판의 본드 핑거(11)간의 와이어 본딩시, 본딩 패드(31,61) 상에 볼(33,63)을 형성하고, 상기 볼(33,63)을 매개로 와이어 본딩이 실시된다. 이를 도 2를 참조하여 살펴보면, 제 1 및 제 2 반도체 칩의 본딩 패드(31,61) 상에는 와이어 본딩을 위한 볼(33,63)이 형성되며, 상기 볼(33,63) 상에는 금속 와이어(32,62)가 본딩된다. 이 때, 금속 와이어(32,62)는 각각 제 1 및 제 2 반도체 칩(30,60)의 측면에서의 쇼트를 방지하기 위한 공간을 마련하기 위해 루프(loop)를 형성하며, 최종적으로 기판(10)의 본드 핑거(11)와 본딩된다. 그러나, 이와 같은 루프(loop)는 금속 와이어의 길이 및 패키지의 자체의 높이를 증가시키며, 더욱이, 금속 와이어를 보호하기 위한 고정제는 패키지의 높이를 한층 더 증가시킨다.The conventional up-up type chip stack package having such a configuration has bonding pads 31 and 61 when wire bonding between the bonding pads 31 and 61 of the first and second semiconductor chips and the bond fingers 11 of the substrate. Balls 33 and 63 are formed on the wire, and wire bonding is performed via the balls 33 and 63. Referring to FIG. 2, balls 33 and 63 for wire bonding are formed on bonding pads 31 and 61 of the first and second semiconductor chips, and metal wires 32 are formed on the balls 33 and 63. 62 is bonded. In this case, the metal wires 32 and 62 form loops to provide a space for preventing shorts on the side surfaces of the first and second semiconductor chips 30 and 60, respectively, and finally, the substrate ( 10 is bonded with the bond finger 11. However, such a loop increases the length of the metal wire and the height of the package itself, and furthermore, the fixing agent for protecting the metal wire further increases the height of the package.

따라서, 본 발명은 전술한 바와 같은 문제점을 해결하기 위하여 제안된 것으로서, 본 발명의 목적은 와이어 본딩시 금속 와이어의 루프(loop)를 최소화하여, 패키지의 높이를 감소시키는 칩 스택 패키지를 제공함에 있다.Accordingly, the present invention has been proposed to solve the above problems, and an object of the present invention is to provide a chip stack package which reduces the height of the package by minimizing the loop of the metal wire during wire bonding. .

본 발명의 상기와 같은 목적을 달성하기 위해, 본 발명의 일면에 따라, 칩 스택 패키지가 제공되며: 이 패키지는, 상부면에 본드 핑거를 구비하고, 상기 본드 핑거 상에 형성된 본딩용 볼을 포함하며, 아울러 하부면에 볼 랜드가 구비된 기판; 상기 기판 상에 접착제를 매개로 페이스 업 방식으로 부착되며, 상부 양측 가장자리에 제 1 에폭시가 부착된 센터 패드형의 제 1 반도체 칩; 상기 제 1 반도체 칩의 본딩 패드 상에 형성된 본딩용 볼; 상기 제 1 에폭시와 밀착된 상태로, 상기 제 1 반도체 칩의 본딩 패드 상에 형성된 본딩용 볼과 상기 기판의 본드 핑거 상에 형성된 본딩용 볼을 전기적으로 연결하는 제 1 금속 와이어; 상기 제 1 반도체 칩 상부에 형성되며, 상기 제 1 금속 와이어를 고정시키기 위한 제 1 고정제; 상기 고정제를 포함한 상기 반도체 칩 상부에 접착제를 매개로 페이스 업 방식으로 부착되며, 상부 양측 가장자리에 제 2 에폭시가 부착된 센터 패드형의 제 2 반도체 칩; 상기 제 2 반도체 칩의 본딩 패드 상에 형성된 본딩용 볼; 상기 제 2 에폭시와 밀착된 상태로, 제 2 반도체 칩의 본딩 패드 상에 형성된 본딩용 볼과 상기 기판의 본드 상에 형성된 본딩용 볼을 전기적으로 연결하는 제 2 금속 와이어; 상기 제 2 반도체 칩 상부에 형성되며, 상기 제 2 금속 와이어를 고정시키기 위한 제 2 고정제; 상기 기판 상부면 및 상기 제 2 고정제 상부면 포함한 영역을 밀봉하는 봉지제; 및 상기 기판 하부면의 볼 랜드 상에 부착되는 솔더 볼;을 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, according to one aspect of the present invention, a chip stack package is provided: the package includes a bonding finger on the upper surface and a bonding ball formed on the bond finger. A substrate having a ball land on a lower surface thereof; A center pad type first semiconductor chip attached to the substrate by a face-up method through an adhesive and having first epoxy attached to upper edges thereof; A bonding ball formed on a bonding pad of the first semiconductor chip; A first metal wire electrically connecting the bonding ball formed on the bonding pad of the first semiconductor chip with the bonding ball formed on the bond finger of the substrate in close contact with the first epoxy; A first fixing agent formed on the first semiconductor chip to fix the first metal wire; A center pad type second semiconductor chip attached to an upper surface of the semiconductor chip including the fixing agent through an adhesive, and having a second epoxy attached to both upper edges thereof; A bonding ball formed on a bonding pad of the second semiconductor chip; A second metal wire which electrically connects the bonding ball formed on the bonding pad of the second semiconductor chip and the bonding ball formed on the bond of the substrate while being in close contact with the second epoxy; A second fixing agent formed on the second semiconductor chip to fix the second metal wire; An encapsulant sealing an area including the upper surface of the substrate and the upper surface of the second fixing agent; And solder balls attached to the ball lands on the lower surface of the substrate.

(실시예)(Example)

이하, 도면을 참조하여 본 발명의 바람직한 실시예를 상술하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명의 실시예에 따른 칩 스택 패키지의 단면도를 도시한다.3 shows a cross-sectional view of a chip stack package according to an embodiment of the invention.

도시한 바와 같이, 본 발명의 실시예에 따른 칩 스택 패키지는, 상부면에 본드 핑거(111) 및 하부면에 볼 랜드(112)를 구비한 기판(110) 상에 접착제(120)를 매개로 센터 패드형의 제 1 반도체 칩(130)이 페이스 업 타입으로 부착된다. 이 때, 기판(110)의 본드 핑거(111) 및 제 1 반도체 칩(130)의 본딩 패드(131) 상에는 본딩용 볼(113,133)이 부착되며, 또한, 제 1 반도체 칩(130) 상부 가장자리에는 에폭시(132)가 부착되어 있다. As shown, the chip stack package according to an embodiment of the present invention, via the adhesive 120 on the substrate 110 having the bond finger 111 on the upper surface and the ball land 112 on the lower surface. The center pad type first semiconductor chip 130 is attached in a face up type. At this time, the bonding balls 113 and 133 are attached to the bond finger 111 of the substrate 110 and the bonding pad 131 of the first semiconductor chip 130, and the upper edges of the first semiconductor chip 130. Epoxy 132 is attached.

그리고, 제 1 반도칩(130)의 본딩 패드(131) 및 기판(110)의 본드 핑거(111) 상에 형성된 본딩용 볼(113,133)은 제 1 금속 와이어(134)에 의해 상호 전기적으로 연결된다. 이 때, 제 1 금속 와이어(134)는 제 1 반도체 칩(130)의 가장자리에서, 에폭시(132)와 밀착된 상태로 와이어 본딩되며, 그에 따라, 금속 와이어(134)의 루프(loop)의 높이는 최소화가 된다.In addition, the bonding balls 113 and 133 formed on the bonding pad 131 of the first semiconductor chip 130 and the bond finger 111 of the substrate 110 are electrically connected to each other by the first metal wire 134. . In this case, the first metal wire 134 is wire bonded at the edge of the first semiconductor chip 130 in close contact with the epoxy 132, and thus, the height of the loop of the metal wire 134 may be increased. Minimized.

이 후, 제 1 금속 와이어(134)를 고정하기 위한 고정제(140)가 제 1 반도체 칩(130) 상부에 형성된다. 그런 다음, 고정제 상부(140)에는 접착제(150)를 매개로 센터 패드형의 제 2 반도체 칩(160)이 페이스 업 타입으로 부착된다. 이 때, 제 2 반도체 칩(160)은 제 1 반도체 칩(130)과 마찬가지로, 상부면 가장자리에 에폭시(162)가 부착되어 있으며, 본딩 패드(161) 상에는 본딩용 볼(163)이 형성되어 있다.Thereafter, a fixing agent 140 for fixing the first metal wire 134 is formed on the first semiconductor chip 130. Thereafter, the second semiconductor chip 160 of the center pad type is attached to the upper part of the fixing agent 140 in the form of a face up type through the adhesive 150. At this time, like the first semiconductor chip 130, the second semiconductor chip 160 has an epoxy 162 attached to the top edge thereof, and a bonding ball 163 is formed on the bonding pad 161. .

그리고, 제 2 반도칩(160)의 본딩 패드(131) 및 기판(110)의 본드 핑거(111) 상에 형성된 본딩용 볼(114,134)은 제 2 금속 와이어(164)에 의해 상호 전기적으로 연결된다. 이 때, 제 2 금속 와이어(164)는 제 1 금속 와이어(134)와 마찬가지로 제 2 반도체 칩(160)의 가장자리에서, 에폭시(162)와 밀착된 상태로 와이어 본딩되며, 그에 따라, 금속 와이어(164)의 루프(loop)의 높이는 최소화가 된다. 이 후, 제 2 금속 와이어(164)를 고정하기 위한 고정제(170)가 제 2 반도체 칩(160) 상부에 형성된다. 그런 다음, 기판(110) 상부면 및 고정제(170) 상부면을 포함한 영역은 봉제제(180)로 밀봉되며, 기판(110) 하부면에 형성된 볼 랜드(112) 상에는 솔더 볼(190)이 부착된다.In addition, the bonding balls 114 and 134 formed on the bonding pad 131 of the second semiconductor chip 160 and the bond finger 111 of the substrate 110 are electrically connected to each other by the second metal wire 164. . In this case, the second metal wire 164 is wire-bonded in close contact with the epoxy 162 at the edge of the second semiconductor chip 160, similarly to the first metal wire 134. The height of the loop of 164 is minimized. Thereafter, a fixing agent 170 for fixing the second metal wire 164 is formed on the second semiconductor chip 160. Then, the region including the upper surface of the substrate 110 and the upper surface of the fixing agent 170 is sealed with the sewing material 180, and the solder balls 190 are formed on the ball lands 112 formed on the lower surface of the substrate 110. Attached.

이와 같은 구조를 갖는 본 발명에 따른 칩 스택 패키지는, 와이어 본딩시, 반도체 칩 상부에 부착된 에폭시(132,162) 상에 제 1 및 제 2 금속 와이어(134,164)를 밀착시켜 본딩함으로써, 금속 와이어(134,164)의 루프 높이를 최소화시킬 수 있다. 그에 따라, 패키지 자체의 높이는, 금속 와이어(134,164) 루프의 감소된 높이만큼 감소된다. 여기서, 에폭시(132,162)는 각각 제 1 및 제 2 반도체 칩(130,160)의 가장자리에서 제 1 및 제 2 금속 와이어(134,164)와의 쇼트를 방지한다. In the chip stack package according to the present invention having the above structure, the metal wires 134 and 164 are bonded by bonding the first and second metal wires 134 and 164 on the epoxy 132 and 162 attached to the semiconductor chip. Loop height can be minimized. Thus, the height of the package itself is reduced by the reduced height of the metal wire 134, 164 loops. Here, the epoxy 132 and 162 prevents shorts with the first and second metal wires 134 and 164 at the edges of the first and second semiconductor chips 130 and 160, respectively.

이하에서는, 도 4 내지 도 10을 참조하여, 본 발명에 따른 칩 스택 패키지의 공정 순서를 살펴보기로 한다.Hereinafter, a process sequence of a chip stack package according to the present invention will be described with reference to FIGS. 4 to 10.

먼저, 도 4를 참조하면, 제 1 반도체 칩(130)이 접착제(120)를 매개로 기판 (110) 상에 부착된다.First, referring to FIG. 4, the first semiconductor chip 130 is attached onto the substrate 110 through the adhesive 120.

이 후, 도 5를 참조하면, 제 1 반도체 칩(130)의 상부 가장자리에 에폭시(132)가 부착되고, 본딩 패드(131) 상에는 본딩용 볼(133)이 형성된다.Subsequently, referring to FIG. 5, an epoxy 132 is attached to an upper edge of the first semiconductor chip 130, and a bonding ball 133 is formed on the bonding pad 131.

다음, 도 6을 참조하면, 기판의 보드 핑거(111) 상에는 본딩용 볼(113)이 형성되며, 기판(110) 상에 형성된 본딩용 볼(113)과 제 1 반도체 칩(130)의 본딩용 볼(133)은 제 1 금속 와이어(134)에 의해 와이어 본딩된다. 이 때, 제 1 금속 와이어(134)는 제 1 반도체 칩(130) 상에 부착된 에폭시(132)와 밀착되도록 와이어 본딩된다. 따라서, 제 1 금속 와이어(134)와 제 1 반도체 칩(130)은 에폭시(132)의 높이만큼 이격되어 있는 형상을 가진다.Next, referring to FIG. 6, a bonding ball 113 is formed on the board finger 111 of the substrate, and the bonding ball 113 and the first semiconductor chip 130 formed on the substrate 110 are bonded. The ball 133 is wire bonded by the first metal wire 134. In this case, the first metal wire 134 is wire bonded to closely contact the epoxy 132 attached on the first semiconductor chip 130. Accordingly, the first metal wire 134 and the first semiconductor chip 130 have a shape spaced apart by the height of the epoxy 132.

그리고 나서, 도 7을 참조하면, 제 1 반도체 칩(130) 상부에 제 1 금속 와이어(134)를 고정하기 위한 고정제(140)가 형성되고, 도 8에 도시한 바와 같이, 고정제(140) 상부에는 접착제(150)를 매개로 제 2 반도체 칩(160)이 페이스 업 타입으로 부착된다.Then, referring to FIG. 7, a fixing agent 140 for fixing the first metal wire 134 is formed on the first semiconductor chip 130, and as shown in FIG. 8, the fixing agent 140. The second semiconductor chip 160 is attached as a face up type through the adhesive 150.

그런 다음, 도 9를 참조하면, 제 2 반도체 칩(160)의 상부 가장자리에 에폭시(162)가 부착되고, 본딩 패드(161) 상에는 본딩용 볼(163)이 형성된다. 이 후,기판(110) 상에 형성된 본딩용 볼(114)과 제 2 반도체 칩(130)의 본딩용 볼(163)은 제 2 금속 와이어(164)에 의해 와이어 본딩된다. 이 때, 제 2 금속 와이어(164)는 제 1 금속 와이어(134)와 마찬가지로 에폭시(162)와 밀착된 상태로 와이어 본딩된다.Next, referring to FIG. 9, an epoxy 162 is attached to an upper edge of the second semiconductor chip 160, and a bonding ball 163 is formed on the bonding pad 161. Thereafter, the bonding ball 114 formed on the substrate 110 and the bonding ball 163 of the second semiconductor chip 130 are wire bonded by the second metal wire 164. At this time, the second metal wire 164 is wire-bonded in close contact with the epoxy 162 like the first metal wire 134.

마지막으로, 도 10을 참조하면, 제 2 반도체 칩(160) 상부에 제 2 금속 와이어(164)를 고정하기 위한 고정제(170)가 형성되고, 기판(110) 상부면 및 고정제(170) 상부면을 포함한 영역은 봉제제(180)로 밀봉되며, 기판(110) 하부면에 형성된 볼 랜드(112) 상에는 솔더 볼(190)이 부착되어, 패키지가 완성된다.Finally, referring to FIG. 10, a fixing agent 170 for fixing the second metal wire 164 is formed on the second semiconductor chip 160, and the upper surface and the fixing agent 170 of the substrate 110 are formed. The region including the upper surface is sealed with the sewing agent 180, and the solder ball 190 is attached to the ball land 112 formed on the lower surface of the substrate 110 to complete the package.

상기한 바와 같은 본 발명의 구성에 따라, 금속 와이어(134,164)의 루프 높이를 최소화하여, 패키지 자체의 높이를 감소시킬 수 있으므로, 다수의 반도체 칩을 적층할 수 있다.According to the configuration of the present invention as described above, since the height of the package itself can be reduced by minimizing the loop height of the metal wires 134 and 164, a plurality of semiconductor chips can be stacked.

본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구범위에 의해 마련되는 본 발명의 정신이나 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자는 용이하게 알 수 있다.While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. It will be readily apparent to one of ordinary skill in the art that modifications and variations can be made.

도 1은 종래 기술에 따른 칩 스택 패키지의 단면도.1 is a cross-sectional view of a chip stack package according to the prior art.

도 2는 종래 기술에 따른 와이어 본딩 방법을 설명하기 위한 도면.2 is a view for explaining a wire bonding method according to the prior art.

도 3은 본 발명의 실시예에 따른 칩 스택 패키지의 단면도.3 is a cross-sectional view of a chip stack package according to an embodiment of the present invention.

도 4 내지 도 10은 본 발명에 따른 칩 스택 패키지의 공정 순서를 설명하기 위한 도면.4 to 10 are views for explaining the process sequence of the chip stack package according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

110: 기판 111: 본드 핑거110: substrate 111: bond finger

112: 볼랜드 120,150: 접착제112: Borland 120, 150: adhesive

130: 제 1 반도체 칩 132,162: 에폭시130: first semiconductor chip 132,162: epoxy

134: 제 1 금속 와이어 140,170: 고정제134: first metal wire 140, 170: fixing agent

160: 제 2 반도체 칩 164: 제 2 금속 와이어160: second semiconductor chip 164: second metal wire

Claims (1)

상부면에 본드 핑거를 구비하고, 상기 본드 핑거 상에 형성된 본딩용 볼을 포함하며, 아울러 하부면에 볼 랜드가 구비된 기판;A substrate having a bond finger on an upper surface, a bonding ball formed on the bond finger, and a ball land provided on a lower surface thereof; 상기 기판 상에 접착제를 매개로 페이스 업 방식으로 부착되며, 상부 양측 가장자리에 제 1 에폭시가 부착된 센터 패드형의 제 1 반도체 칩;A center pad type first semiconductor chip attached to the substrate by a face-up method through an adhesive and having first epoxy attached to upper edges thereof; 상기 제 1 반도체 칩의 본딩 패드 상에 형성된 본딩용 볼;A bonding ball formed on a bonding pad of the first semiconductor chip; 상기 제 1 에폭시와 밀착된 상태로, 상기 제 1 반도체 칩의 본딩 패드 상에 형성된 본딩용 볼과 상기 기판의 본드 핑거 상에 형성된 본딩용 볼을 전기적으로 연결하는 제 1 금속 와이어;A first metal wire electrically connecting the bonding ball formed on the bonding pad of the first semiconductor chip with the bonding ball formed on the bond finger of the substrate in close contact with the first epoxy; 상기 제 1 반도체 칩 상부에 형성되며, 상기 제 1 금속 와이어를 고정시키기 위한 제 1 고정제;A first fixing agent formed on the first semiconductor chip to fix the first metal wire; 상기 고정제를 포함한 상기 반도체 칩 상부에 접착제를 매개로 페이스 업 방식으로 부착되며, 상부 양측 가장자리에 제 2 에폭시가 부착된 센터 패드형의 제 2 반도체 칩;A center pad type second semiconductor chip attached to an upper surface of the semiconductor chip including the fixing agent through an adhesive, and having a second epoxy attached to both upper edges thereof; 상기 제 2 반도체 칩의 본딩 패드 상에 형성된 본딩용 볼;A bonding ball formed on a bonding pad of the second semiconductor chip; 상기 제 2 에폭시와 밀착된 상태로, 제 2 반도체 칩의 본딩 패드 상에 형성된 본딩용 볼과 상기 기판의 본드 상에 형성된 본딩용 볼을 전기적으로 연결하는 제 2 금속 와이어;A second metal wire which electrically connects the bonding ball formed on the bonding pad of the second semiconductor chip and the bonding ball formed on the bond of the substrate while being in close contact with the second epoxy; 상기 제 2 반도체 칩 상부에 형성되며, 상기 제 2 금속 와이어를 고정시키기 위한 제 2 고정제;A second fixing agent formed on the second semiconductor chip to fix the second metal wire; 상기 기판 상부면 및 상기 제 2 고정제 상부면 포함한 영역을 밀봉하는 봉지제; 및An encapsulant sealing an area including the upper surface of the substrate and the upper surface of the second fixing agent; And 상기 기판 하부면의 볼 랜드 상에 부착되는 솔더 볼;을 포함하는 것을 특징으로 하는 칩 스택 패키지.And a solder ball attached on the ball land of the lower surface of the substrate.
KR1020050055713A 2005-06-27 2005-06-27 Chip stack package KR20070000181A (en)

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