KR20050033204A - A semiconductor device, and a manufacturing method thereof - Google Patents
A semiconductor device, and a manufacturing method thereofInfo
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- KR20050033204A KR20050033204A KR1020030069173A KR20030069173A KR20050033204A KR 20050033204 A KR20050033204 A KR 20050033204A KR 1020030069173 A KR1020030069173 A KR 1020030069173A KR 20030069173 A KR20030069173 A KR 20030069173A KR 20050033204 A KR20050033204 A KR 20050033204A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 91
- 230000008569 process Effects 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 150000004767 nitrides Chemical class 0.000 claims abstract description 33
- 125000006850 spacer group Chemical group 0.000 claims abstract description 25
- 238000000059 patterning Methods 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000001312 dry etching Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 14
- 238000001039 wet etching Methods 0.000 claims description 12
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 230000003667 anti-reflective effect Effects 0.000 claims description 4
- 239000006117 anti-reflective coating Substances 0.000 abstract description 3
- 239000010949 copper Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000009977 dual effect Effects 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000000149 argon plasma sintering Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자 및 그 제조 방법에 관한 것으로, 보다 구체적으로, 듀얼-다마신(Dual-damascene) 공정으로 반도체 소자를 제조할 경우, 비아(via) 식각 시에 과도식각(over etch)으로 인한 핀치-오프 현상을 발생시키지 않도록 습식 식각과 스페이서(spacer)를 이용하는 반도체 소자 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, when a semiconductor device is manufactured by a dual-damascene process, it may be caused by overetching during via etching. The present invention relates to a semiconductor device using wet etching and a spacer so as not to generate a pinch-off phenomenon, and a method of manufacturing the same.
반도체 집적회로의 집적도가 증가함에 따라, 소자를 연결하는데 필요한 상호연결의 수 또한 증가하게 되었다. 그러므로 두 개 또는 그 이상의 금속층을 사용하는 설계가 집적회로 제조 방법에 있어서 하나의 표준이 되고 있다. 집적회로의 집적도를 증가시키면, 고 수율(production yield) 및 신뢰성(reliability)을 얻기란 쉽지 않다. 다마신 공정을 이용한 반도체 제조 방법은 평평한 유전체 막에 트렌치를 형성하는 우선 식각(first etching)에 의해 상호연결 선을 만들고, 그다음 생성된 트렌치에 금속을 채우는 단계를 포함하는 제조 기술이다. 이러한 방법에서 반도체 기판을 쉽게 식각되지 않는 구리 금속으로 채울 수 있다. 이러한 다마신 공정을 이용한 제조 방법은 서브쿼터 미크론 상호연결(subquarter micron interconnects)의 제조 산업에 있어서 가장 많이 선택되고 있는 방법이다.As the degree of integration of semiconductor integrated circuits has increased, so has the number of interconnections required to connect the devices. Therefore, designs using two or more metal layers have become a standard in integrated circuit fabrication methods. Increasing the density of integrated circuits, it is not easy to achieve high production yield and reliability. A semiconductor fabrication method using a damascene process is a fabrication technique that includes forming interconnect lines by first etching to form trenches in a flat dielectric film, and then filling the resulting trenches with metal. In this way, the semiconductor substrate can be filled with a copper metal that is not easily etched. The manufacturing method using this damascene process is the method of choice in the manufacturing industry of subquarter micron interconnects.
최근에 반도체소자의 집적도가 증가함에 따라 다층 금속배선(Multi-metal interconnects) 구조가 요구되고 있다. 이러한 다층 금속배선을 효율적으로 제조하기 위해 다마신 공정이 제안되었는데, 특히 듀얼 다마신 공정이 주로 적용되고 있다.Recently, as the degree of integration of semiconductor devices increases, a multi-metal interconnect structure is required. In order to efficiently manufacture such multi-layered metallization, a damascene process has been proposed. In particular, a dual damascene process is mainly applied.
이러한 듀얼 다마신 공정은 금속배선 외에 비트 라인 또는 워드라인 형성에 이용되며, 특히 다층 금속배선에서 상층 금속배선과 하층 금속배선을 접속시키기 위한 비아홀을 동시에 형성할 수 있을 뿐만 아니라, 금속배선에 의해 발생하는 단차를 제거할 수 있으므로 후속 공정을 용이하게 하는 장점이 있다.The dual damascene process is used to form bit lines or word lines in addition to metal wiring, and in particular, not only can form via holes for connecting upper metal wiring and lower metal wiring in multilayer metal wiring, but also by metal wiring. Since the step can be eliminated, there is an advantage of facilitating subsequent processes.
듀얼 다마신 공정은 크게 비아 퍼스트법(Via first)과 트렌치 퍼스트법(Trench first)으로 구분되는데, 비아 퍼스트법은 절연막을 사진 및 식각으로 식각하여 비아홀(via hole)을 먼저 형성한 후, 절연막을 다시 식각하여 비아홀 상부에 트렌치(Trench)를 형성하는 방법이다.The dual damascene process is largely divided into a via first method and a trench first method. In the via first method, a via hole is formed by etching an insulating film by photo and etching, and then the insulating film is removed. By etching again, a trench is formed in the upper portion of the via hole.
그리고 트렌치 퍼스트법은 반대로 트렌치를 먼저 형성한 후, 비아홀을 형성하는 방법이다. 상기한 두 방법 중 비아 퍼스트법이 주로 적용되고 있다.In contrast, the trench first method is a method of forming a via hole after forming a trench first. Via first method is mainly applied among the above two methods.
그리고 반도체 소자의 제조 공정에서 다층 금속배선의 알루미늄(Al)과 같은 금속막은 표면 반사율이 매우 높기 때문에 금속막을 패터닝하기 위한 사진공정시 빛의 산란이 발생하여 금속막에 노칭(Notching) 및 씨닝(Thinning) 문제가 발생된다.In the semiconductor device manufacturing process, since the metal film such as aluminum (Al) of the multilayer metal wiring has a very high surface reflectance, light scattering occurs during the photolithography process for patterning the metal film, thereby notching and thinning the metal film. A problem occurs.
이러한 문제는 반도체 소자가 고집적화됨에 따라 금속배선의 폭이 감소되기 때문에 더욱 심하게 나타나기 때문에, 이를 방지하기 위하여 금속막상에 반사 방지막(Anti Reflective Coating; ARC)을 형성한다.This problem is more severe because the width of the metal wiring decreases as the semiconductor device is highly integrated, and thus, an anti-reflective coating (ARC) is formed on the metal film to prevent this problem.
한편, 디자인룰이 0.15㎛ 이하로 미세화 됨에 따라, 알루미늄의 백엔드 공정에서 비아 홀 패턴과 금속 배선 패턴 형성이 어려워지고 있다. 알루미늄은 낮은 비저항과 우수한 전기전도도를 가지는 특성을 가지고 있지만, 질량 이동(mass transport)으로 인해 보이드(void) 등을 형성하는 일렉트로-마이그레이션(electro- migration: EM)에 대한 저항성이 열악하다는 단점이 있다. 그에 따라 차세대 배선 재료로서 구리가 고려되는데, 구리는 알루미늄에 비해 일렉트로-마이그레이션에 대한 저항성이 우수하다.On the other hand, as the design rule becomes finer to 0.15 µm or less, it is difficult to form the via hole pattern and the metal wiring pattern in the back end process of aluminum. Aluminum has the characteristics of low specific resistance and excellent electrical conductivity, but has a disadvantage of poor resistance to electro-migration (EM), which forms voids due to mass transport. . Accordingly, copper is considered as a next-generation wiring material, which has better resistance to electro-migration than aluminum.
이러한 구리를 이용하여 반도체 집적회로 소자의 금속 배선을 형성하기 위하여 듀얼 다마신 공정이 이용되는 바, 일반적으로 비아 콘택홀과 배선영역을 구현하기 위한 듀얼 다마신 패턴 공정을 거쳐 증착공정을 통해 도전물질을 채워 넣고 화학 기계적 연마(CMP) 공정을 통해 평탄화하는 방법으로 금속 배선을 형성한다.A dual damascene process is used to form a metal interconnection of a semiconductor integrated circuit device using copper. In general, a conductive material is deposited through a dual damascene pattern process to realize a via contact hole and a wiring region. The metal wires are formed by filling them and planarizing them through a chemical mechanical polishing (CMP) process.
그러나 종래의 듀얼-다마신 공정에 있어서, 다마신 프로파일이 거의 직각에 가깝기 때문에 후속 리소그래피 공정에서 반사 방지막으로 이용되는 유기-반사 방지막(Organic-ARC)의 제거가 용이하지 않으므로 반도체 소자의 제작이 어렵다는 문제점이 있고, 또한 2번에 걸친 건식 식각을 적용하기 때문에 반도체 소자의 신뢰성에 악영향을 준다는 문제점이 있다. However, in the conventional dual-damacin process, since the damascene profile is nearly right, it is difficult to remove the organic-ARC, which is used as the anti-reflection film in the subsequent lithography process. There is a problem, and there is a problem that adversely affects the reliability of the semiconductor device because the dry etching is applied twice.
상기 문제점을 해결하기 위한 본 발명의 목적은 습식 식각 공정을 이용하여 다마신 프로파일을 보다 완만하게 형성함으로써 반사 방지막을 용이하게 제거할 수 있는 듀얼-다마신 공정을 이용하는 반도체 소자 및 그 제조 방법을 제공하기 위한 것이다.SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a semiconductor device using a dual-damacin process that can easily remove the anti-reflection film by forming a gentle damascene profile using a wet etching process and a method of manufacturing the same. It is to.
또한, 본 발명의 다른 목적은 비아 측벽에 스페이서막을 형성하여 과도식각으로 인한 핀치-오프를 방지할 수 있는 듀얼-다마신 공정을 이용하는 반도체 소자 및 그 제조 방법을 제공하기 위한 것이다.In addition, another object of the present invention is to provide a semiconductor device and a method of manufacturing the same using a dual damascene process capable of forming a spacer film on a sidewall of a via to prevent pinch-off due to overetching.
상기 목적을 달성하기 위한 수단으로서, 본 발명에 따른 듀얼-다마신 공정을 이용하여 반도체 소자를 제조하는 방법은,As a means for achieving the above object, a method of manufacturing a semiconductor device using a dual- damascene process according to the present invention,
ⅰ) 반도체 기판 혹은 하부 메탈층 상에 제1 질화막, 제1 산화막, 제2 질화막, 제2 산화막을 순차적으로 증착하는 단계;Iii) sequentially depositing a first nitride film, a first oxide film, a second nitride film, and a second oxide film on the semiconductor substrate or the lower metal layer;
ⅱ) 상기 제2 산화막을 패터닝한 후, 완만한 경사를 갖도록 습식 식각하는 단계; Ii) wet etching the patterned second oxide layer to have a gentle slope;
ⅲ) 상기 패터닝된 제2 산화막의 전면에 하부-반사 방지막(Bottom ARC)을 증착하는 단계;Iii) depositing a bottom anti-reflection film (Bottom ARC) on the entire surface of the patterned second oxide film;
ⅳ) 상기 하부-반사 방지막, 제2 질화막, 제1 산화막 및 제1 질화막을 패터닝한 후, 건식 식각을 통해 홀(hole)을 형성하는 단계;Iv) patterning the lower anti-reflection film, the second nitride film, the first oxide film, and the first nitride film, and then forming a hole through dry etching;
ⅴ) 상기 하부-반사 방지막을 제거하는 단계;Iii) removing the bottom anti-reflective film;
ⅵ) 상기 형성된 홀(hole) 내측벽에 스페이서막을 형성하는 단계; 및Iii) forming a spacer film on the inner wall of the formed hole; And
ⅶ) 상기 스페이서막이 증착된 홀 내부에 도전체를 증착한 후, 평탄화 공정을 통해 플러그를 형성하는 단계;Iv) depositing a conductor in the hole in which the spacer film is deposited, and then forming a plug through a planarization process;
를 포함하여 이루어지는 것을 특징으로 한다.Characterized in that comprises a.
여기서, 상기 패터닝 공정은 감광막을 이용하는 것이 바람직하다.Here, it is preferable that the said patterning process uses a photosensitive film.
여기서, 상기 제1 질화막은 상기 제1 산화막에 비해 식각 선택비(etch selectivity)가 높은 것이 바람직하며, 상기 제2 질화막은 상기 제1 산화막 및 제2 산화막에 비해 식각 선택비가 높은 것이 바람직하다.The first nitride layer may have a higher etch selectivity than the first oxide layer, and the second nitride layer may have a higher etch selectivity than the first oxide layer and the second oxide layer.
여기서, 상기 홀은 메탈 패턴을 형성하기 위해 등방성 건식 식각 방법을 이용하는 것을 특징으로 한다.Here, the hole is characterized by using an isotropic dry etching method to form a metal pattern.
여기서, 상기 도전체를 형성하기 전에 CMP 정지층(stop layer)으로 배리어 메탈(Barrier metal)을 형성하여 이용할 수 있다.Here, before forming the conductor, a barrier metal may be formed and used as a CMP stop layer.
여기서, 상기 홀의 내측벽에 형성된 스페이서막으로 질화막을 이용하는 것이 바람직하다.Here, it is preferable to use a nitride film as the spacer film formed on the inner wall of the hole.
상기한 제조 방법에 의하면 본 발명은,According to the above-described manufacturing method, the present invention,
반도체 기판 혹은 하부 메탈층 상에 증착된 제1 산화막, 질화막 및 제2 산화막;A first oxide film, a nitride film, and a second oxide film deposited on a semiconductor substrate or a lower metal layer;
습식 식각을 통해 완만한 경사를 갖도록 제2 산화막을 패터닝하여 형성된 트렌치;A trench formed by patterning the second oxide layer to have a gentle slope through wet etching;
등방성 식각을 통해 수직의 프로파일을 갖도록 질화막 및 제1 산화막을 패터닝하여 형성된 비아홀;A via hole formed by patterning the nitride film and the first oxide film to have a vertical profile through isotropic etching;
상기 비아홀 내측벽에 형성된 스페이서막; 및A spacer film formed on the inner wall of the via hole; And
상기 스페이서막이 형성된 비아홀 및 상기 트렌치 내부에 증착된 도전체;A via hole in which the spacer layer is formed and a conductor deposited in the trench;
를 포함하는 듀얼-다마신 공정을 이용한 반도체 소자를 얻을 수 있다.A semiconductor device using a dual damascene process may be obtained.
본 발명에 따른 듀얼-다마신 공정을 이용하는 반도체 소자 및 그 제조 방법에서는 습식 식각 공정을 이용하여 다마신 프로파일을 보다 완만하게 형성함으로써 반사 방지막을 용이하게 제거할 수 있고, 또한, 비아홀 측벽에 스페이서막을 형성하여 과도식각으로 인한 핀치-오프를 방지할 수 있으므로, 후속 배리어 메탈 공정시에 배선으로 사용될 구리가 산화막 내로 확산되는 것을 방지할 수 있다.In the semiconductor device using the dual-damacin process and the method of manufacturing the same according to the present invention, the anti-reflection film can be easily removed by forming the damascene profile more smoothly by using the wet etching process, and the spacer film is formed on the sidewalls of the via hole. Since it is possible to prevent pinch-off due to overetching, the copper to be used as a wiring in a subsequent barrier metal process can be prevented from being diffused into the oxide film.
이하, 첨부된 도면을 참조하여 본 발명의 실시예에 따른 듀얼-다마신 공정을 이용하여 제조되는 반도체 소자 및 그 제조 방법을 상세히 설명한다.Hereinafter, a semiconductor device manufactured using a dual-damascene process and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 각각 본 발명에 따른 듀얼-다마신 공정을 이용하여 반도체 소자를 제조하는 공정을 나타내는 도면들이다.1A to 1F are diagrams illustrating a process of manufacturing a semiconductor device using the dual-damascene process according to the present invention, respectively.
본 발명에 따른 듀얼-다마신 공정을 이용하여 반도체 소자를 제조하는 방법은, 먼저 도 1a를 참조하면, 반도체 기판(11) 상에 제1 질화막(13), 제1 산화막(15), 제2 질화막(17), 제2 산화막(19)을 순서대로 증착시킨 후에 제1 마스크 또는 제1 감광막(30)을 이용하여 패턴을 형성한다. 여기서, 상기 제1 질화막(13)은 상기 제1 산화막(15)에 비해 식각 선택비(etch selectivity)가 높은 것이 바람직하며, 상기 제2 질화막(17)은 상기 제1 산화막(15) 및 제2 산화막(19)에 비해 식각 선택비가 높은 것이 바람직하다.A method of manufacturing a semiconductor device using a dual-damascene process according to the present invention, first referring to FIG. 1A, a first nitride film 13, a first oxide film 15, and a second oxide film on a semiconductor substrate 11. After the nitride film 17 and the second oxide film 19 are deposited in this order, a pattern is formed using the first mask or the first photosensitive film 30. The first nitride layer 13 may have a higher etch selectivity than the first oxide layer 15, and the second nitride layer 17 may be formed of the first oxide layer 15 and the second layer 15. It is preferable that the etching selectivity is higher than that of the oxide film 19.
다음으로, 도 1a의 패턴을 이용하여 습식 식각 방법으로 메탈 패턴을 형성하기 위해 제2 산화막(19')을 형성한 후에 상기 제1 마스크 또는 제1 감광막(30)을 제거하게 된다(도 1b 참조). 여기서, 상기 제2 산화막은 습식 식각 방법을 이용하여 완만하게 경사를 이루도록 형성된 다마신 프로파일인 것이 바람직하다.Next, after forming the second oxide film 19 ′ to form the metal pattern by the wet etching method using the pattern of FIG. 1A, the first mask or the first photosensitive film 30 is removed (see FIG. 1B). ). Here, the second oxide film is preferably a damascene profile formed to be gently inclined using a wet etching method.
다음으로, 도 1b에 유기-반사 방지막(Organic-ARC)으로 하부-반사 방지막(Bottom-ARC)(21)을 형성한 후에, 제2 마스크 또는 제2 감광막(40)을 이용하여 패턴을 형성한다(도 1c 참조). 여기서, 상기 하부-반사 방지막(Bottom ARC)은 통상적으로 유기-반사 방지막이다.Next, after forming the bottom anti-reflective film (Bottom-ARC) 21 with an organic anti-reflection film (Organic-ARC) in Figure 1b, a pattern is formed using a second mask or the second photosensitive film 40. (See FIG. 1C). Here, the bottom anti-reflection film (Bottom ARC) is typically an organic anti-reflection film.
다음으로, 도 1c의 상기 패턴을 이용하여 건식 식각 방법으로 하부-반사 방지막(Bottom-ARC)(21), 제2 질화막(17'), 제1 산화막(15')을 식각하여 비아(via)를 형성한 다음에 제2 마스크 또는 제2 감광막(40)과 상기 유기-반사 방지막(Organic-ARC)(21)을 완전히 제거하게 된다(도 1d 참조). 여기서, 상기 비아는 메탈 패턴을 형성하기 위해 등방성 건식 식각 방법을 이용하게 된다.Next, the bottom anti-reflective film (Bottom-ARC) 21, the second nitride film 17 ′, and the first oxide film 15 ′ are etched by dry etching using the pattern of FIG. 1C. Next, the second mask or the second photoresist film 40 and the organic-ARC 21 are completely removed (see FIG. 1D). The via may use an isotropic dry etching method to form a metal pattern.
다음으로, 스페이서막을 형성하기 위해 질화물을 상기 건식 식각 방법으로 식각된 비아(via)에 증착한 다음에 전면 식각(blanket etch) 방법을 이용하여 비아를 식각하고 상기 비아의 양쪽 측벽에 스페이서막(23)을 형성하게 된다(도 1e 참조). 여기서, 상기 스페이서막으로 질화막을 이용하는 것이 바람직하다. Next, in order to form a spacer layer, nitride is deposited on vias etched by the dry etching method, and then vias are etched using a blanket etch method, and spacer layers 23 are formed on both sidewalls of the vias. ) (See FIG. 1E). Here, it is preferable to use a nitride film as the spacer film.
마지막으로, 배선용 구리(Cu)를 상기 비아 내부에 증착하여 화학 기계적 연마(CMP) 공정을 이용하여 제1 도전체(25)를 형성하게 된다(도 1f 참조). 여기서, CMP 공정에서 CMP 정지층(stop layer)으로서 상기 제1 도전체(13) 증착 시에 배리어 메탈(도시되지 않음)을 미리 형성하여 이용할 수도 있다.Finally, wiring copper (Cu) is deposited inside the via to form the first conductor 25 using a chemical mechanical polishing (CMP) process (see FIG. 1F). Here, in the CMP process, a barrier metal (not shown) may be formed in advance when the first conductor 13 is deposited as a CMP stop layer.
종래의 다마신 공정에서는 2번에 걸친 건식 식각 방법을 이용하였지만, 본 발명에서는 도 1d에 도시된 바와 같이, 건식 식각 방법이 1번만 적용되게 된다. 즉, 먼저 습식 식각 방법으로 상기 제1 산화막(15)을 완만한 경사를 이루도록 식각하고, 이후 등방성 건식 식각으로 비아를 형성하게 된다.In the conventional damascene process, two dry etching methods are used, but in the present invention, as shown in FIG. 1D, only one dry etching method is applied. That is, first, the first oxide layer 15 is etched to form a gentle inclination by a wet etching method, and then vias are formed by isotropic dry etching.
한편, 본 발명에 다른 실시예에 따른 듀얼-다마신 공정을 이용하여 반도체 소자를 제조하는 방법으로, 상기 반도체 기판(11) 상에 제1 질화물(13)을 형성하는 대신에 하부 메탈(도 3의 도면부호 27 참조) 상에 상부-반사 방지막(Top-ARC)을 형성할 수도 있다. 이후, 건식 식각 방법을 이용하여 상기 하부-반사 방지막, 질화막, 제1 산화막 및 상부-반사 방지막을 순서대로 식각하여 비아(via)를 형성하게 되며, 나머지 공정은 도 1a 내지 도 1f의 방법과 동일하다.Meanwhile, in the method of manufacturing a semiconductor device using the dual-damascene process according to another embodiment of the present invention, instead of forming the first nitride 13 on the semiconductor substrate 11, a lower metal (FIG. 3) is formed. A top anti-reflection film (Top-ARC) may be formed. Thereafter, the lower anti-reflection film, the nitride film, the first oxide film, and the upper anti-reflection film are etched sequentially to form vias using a dry etching method, and the rest of the processes are the same as those of FIGS. 1A to 1F. Do.
여기서, 상기 상부-반사 방지막은 티타늄 질화물(TiN)이거나, 또는 티타늄/티타늄 질화물(Ti/TiN)인 것이 바람직하다. 또한, 상기 상부-반사 방지막은 상기 하부 메탈 증착 시에 인-시츄(In-situ)로 증착되게 된다.Here, the upper anti-reflection film is preferably titanium nitride (TiN), or titanium / titanium nitride (Ti / TiN). In addition, the upper anti-reflection film is deposited in-situ during the lower metal deposition.
한편, 도 2는 본 발명에 따라 스페이서막(23)을 형성하기 위해 질화막을 전면 증착(Blanket deposition)한 것을 예시하는 도면이다.Meanwhile, FIG. 2 is a diagram illustrating blanket deposition of a nitride film to form the spacer film 23 according to the present invention.
도 3은 종래의 듀얼-다마신 공정에서 비아 식각시 오정렬(misalign) 발생과 함께 과도식각(over etch)된 경우를 설명하기 위한 도면이다.FIG. 3 is a diagram for explaining a case where overetching occurs along with misalignment during via etching in a conventional dual-damacin process.
도 3은 종래의 기술에 따라 다마신 비아 식각시 오정렬 발생과 함께 과도식각(over etch)한 경우를 나타낸 도면으로서, 과도식각이 발생할 경우 도면부호 A의 점선으로 도시된 부분에서 후속 확산 방지막인 배리어 메탈의 핀치-오프(pinch-off)가 발생되어, 이후 배선용 구리가 산화막 내부로 확산되어 반도체 소자의 신뢰성에 나쁜 영향을 미치게 되는 것을 도시하고 있다.FIG. 3 is a diagram illustrating a case of overetching with misalignment occurring during damascene via etching according to the related art, and a barrier, which is a subsequent diffusion barrier in a portion indicated by the dotted line A when overetching occurs. The pinch-off of the metal is generated, and then the copper for wiring is diffused into the oxide film, which adversely affects the reliability of the semiconductor device.
도 4는 본 발명에 따라 듀얼-다마신 공정에서 스페이서막을 사용하여 과도식각으로 발생되는 핀치-오프를 방지하는 것을 설명하기 위한 도면이다.FIG. 4 is a view for explaining pinch-off caused by overetching using a spacer film in a dual-damascene process according to the present invention.
도 4는 도 3에서 발생하는 문제점을 개선한 것으로서, 스페이서막(23)을 사용함으로써 도 3의 A 부분처럼 과도식각에 의해 발생되는 핀치-오프 영역을 스페이서막(23)으로 메꿀 수 있으며(도면부호 B 참조), 후속 배리어 메탈 증착시 핀치-오프가 형성되지 않기 때문에 배선용 구리의 확산을 억제하는 것을 나타내고 있다.FIG. 4 is an improvement of the problem occurring in FIG. 3. By using the spacer film 23, the pinch-off region generated by the overetching as shown in part A of FIG. 3 can be filled with the spacer film 23 (FIG. Reference numeral B) shows that the pinch-off is not formed during subsequent barrier metal deposition, thereby suppressing the diffusion of copper for wiring.
결국, 본 발명에 따른 듀얼-다마신 공정을 이용하는 반도체 소자 및 그 제조 방법에서는 습식 식각 공정을 이용하여 다마신 프로파일을 보다 완만하게 형성함으로써 유기-반사 방지막을 후속 공정에서 용이하게 제거할 수 있고, 또한, 비아 측벽에 스페이서막을 형성함으로써, 종래의 과도식각으로 인한 핀치-오프를 방지할 수 있으므로, 후속 배리어 메탈 공정시에 배선으로 사용될 구리가 산화막 내로 확산되는 것을 방지하게 된다.As a result, in the semiconductor device using the dual-damacin process and the method of manufacturing the same, the organic-anti-reflection film can be easily removed in a subsequent process by forming the damascene profile more smoothly using the wet etching process. In addition, by forming a spacer film on the sidewall of the via, it is possible to prevent pinch-off due to the conventional over-etching, thereby preventing the copper to be used as wiring in the subsequent barrier metal process to diffuse into the oxide film.
이상의 설명에서 본 발명은 특정의 실시예와 관련하여 도시 및 설명하였지만, 특허청구범위에 의해 나타난 발명의 사상 및 영역으로부터 벗어나지 않는 한도 내에서 다양한 개조 및 변화가 가능하다는 것을 당업계에서 통상의 지식을 가진 자라면 누구나 쉽게 알 수 있을 것이다.While the invention has been shown and described in connection with specific embodiments thereof, it will be appreciated that various modifications and changes can be made without departing from the spirit and scope of the invention as indicated by the claims. Anyone who owns it can easily find out.
본 발명에 따르면, 종래의 다마신 공정에서는 2번에 걸친 건식 식각 방법을 이용하여 하부에 형성되는 트랜지스터가 손상될 우려가 있었으나, 본 발명은 건식 식각 방법이 1번만 적용되기 때문에 트랜지스터의 손상을 방지할 수 있다.According to the present invention, in the conventional damascene process, there is a possibility that the transistor formed at the lower portion is damaged by using two dry etching methods, but the present invention prevents damage to the transistor because the dry etching method is applied only once. can do.
또한, 본 발명에 따르면, 다마신 프로파일을 습식 식각 방법을 이용하여 완만하게 형성함으로써 후속 리소그래피 공정 이후에 유기-반사 방지막 제거를 용이하게 함으로써, 반도체 소자의 신뢰성을 향상시킬 수 있다.In addition, according to the present invention, the damascene profile is gently formed using a wet etching method to facilitate the removal of the organic-reflective coating after the subsequent lithography process, thereby improving the reliability of the semiconductor device.
또한, 본 발명에 따르면, 반도체 소자에 미치는 손상을 감소시킴으로써 동작 특성이 우수한 트랜지스터를 제조할 수 있다.In addition, according to the present invention, a transistor having excellent operating characteristics can be manufactured by reducing damage to a semiconductor element.
도 1a 내지 도 1f는 각각 본 발명에 따른 듀얼-다마신 공정을 이용하여 반도체 소자를 제조하는 공정을 나타내는 도면들이다.1A to 1F are diagrams illustrating a process of manufacturing a semiconductor device using the dual-damascene process according to the present invention, respectively.
도 2는 본 발명에 따라 스페이서막을 형성하기 위해 질화막을 전면 증착(Blanket deposition)한 것을 예시하는 도면이다.FIG. 2 is a diagram illustrating blanket deposition of a nitride film to form a spacer film according to the present invention.
도 3은 종래의 듀얼-다마신 공정에서 비아 식각시 오정렬(misalign) 발생과 함께 과도식각(over etch)된 경우를 설명하기 위한 도면이다.FIG. 3 is a diagram for explaining a case where overetching occurs along with misalignment during via etching in a conventional dual-damacin process.
도 4는 본 발명에 따라 듀얼-다마신 공정에서 스페이서막을 사용하여 과도식각으로 발생되는 핀치-오프를 방지하는 것을 설명하기 위한 도면이다.FIG. 4 is a view for explaining pinch-off caused by overetching using a spacer film in a dual-damascene process according to the present invention.
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