KR20050021905A - 반도체 장치용 패키지 - Google Patents
반도체 장치용 패키지 Download PDFInfo
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- KR20050021905A KR20050021905A KR1020040067913A KR20040067913A KR20050021905A KR 20050021905 A KR20050021905 A KR 20050021905A KR 1020040067913 A KR1020040067913 A KR 1020040067913A KR 20040067913 A KR20040067913 A KR 20040067913A KR 20050021905 A KR20050021905 A KR 20050021905A
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- interposer
- chip
- material layer
- polymer material
- solder ball
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Abstract
Description
Claims (14)
- 반도체 장치에 있어서,제1 및 제2 주면(major surface) - 상기 제1 면은 패터닝된 금속 도체와 본딩 패드를 구비하며 상기 제2 면은 상기 제1 면 상의 선택된 패드에 접속된 솔더볼 어레이를 구비함 - 을 갖는 인터포저(interposer);상면 및 하면(back surface) - 상기 하면은 상기 인터포저의 상기 제1 면에 인접하며 상기 상면은 복수의 단자를 구비함 - 을 갖는 반도체 칩;상기 인터포저의 상기 제1 면에 배치된 고분자 재료층 - 상기 고분자 재료층의 적어도 일부는 상기 칩과 상기 인터포저 사이에 배치됨 - ; 및상기 인터포저 상의 상기 본딩 패드와 상기 칩 단자 사이의 복수의 전기 접속부를 포함하는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 고분자 재료층은 상기 솔더볼 어레이 위쪽의 상기 인터포저 영역을 덮는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 인터포저는 플렉시블 필름, 박막 적층(thin laminate) 또는 박막 콤포지트 재료를 포함하는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 고분자 재료층의 탄성계수는 대략 1 내지 15 GPa 범위인 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 고분자 재료층의 두께는 대략 75 내지 200 미크론 범위인 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 고분자 재료층은 열전도성(thermally conductive)인 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 고분자 재료층은 열경화성 페이스트(paste)를 포함하는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 고분자 재료층은 미리 형성된 필름인 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 고분자 재료층은 상기 인터포저에 인접한 절연체층과 상기 절연체층 상의 금속 충진 고분자층을 구비하는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 칩의 에지는 하나 이상의 상기 솔더볼 위쪽에 위치하는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 칩은 상기 솔더볼 어레이보다 면적이 작으며; 상기 칩의 하면은 상기 인터포저의 제1 면에 부착되며; 상기 고분자 재료층은 상기 인터포저의 제1 면에 배치된 복수의 고분자 구조 - 상기 고분자 구조는 각각 상기 솔더볼 어레이에서의 솔더볼 지점의 위쪽에 배치됨 - 를 포함하는 것을 특징으로 하는 반도체 장치.
- 제12항에 있어서,상기 고분자 구조는 상기 솔더볼 어레이를 덮을 정도의 크기를 갖는 유전체막에 미리 형성된 것을 특징으로 하는 반도체 장치.
- 반도체 장치의 제조 방법에 있어서,패터닝된 금속 도체와 본딩 패드를 갖는 제1 면 및 복수의 솔더볼을 갖는 제2 면을 구비하는 인터포저를 제공하는 단계;상기 인터포저의 제1 면에 상기 복수의 솔더볼을 충분히 덮을 정도의 크기를 갖는 고분자 재료층을 배치하는 단계;상면 및 하면 - 상기 상면은 복수의 단자를 포함함 - 을 갖는 반도체 칩을 제공하는 단계;상기 칩을 상기 고분자 재료층에 실장하는 단계; 및상기 인터포저 상의 상기 본딩 패드를 상기 칩 상의 상기 단자에 접속하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제13항에 있어서,상기 고분자 재료층을 배치하는 단계는 대략 75 내지 200 미크론 범위의 두께를 갖는 고분자 재료층을 배치하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
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US10/651,522 US6992380B2 (en) | 2003-08-29 | 2003-08-29 | Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area |
US10/651,522 | 2003-08-29 |
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KR20050021905A true KR20050021905A (ko) | 2005-03-07 |
KR101096330B1 KR101096330B1 (ko) | 2011-12-20 |
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Cited By (2)
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KR100934269B1 (ko) * | 2005-04-14 | 2009-12-28 | 샌디스크 코포레이션 | 반도체 및 전자 서브-시스템 패키징을 위한 칩 캐리어 기판및 인쇄 회로 기판 상의 강체 웨이브 패턴 설계 |
US9728477B2 (en) | 2014-07-30 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of manufacturing a semiconductor device having scribe lines |
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US6826827B1 (en) | 1994-12-29 | 2004-12-07 | Tessera, Inc. | Forming conductive posts by selective removal of conductive material |
DE10350239A1 (de) * | 2003-10-27 | 2005-06-16 | Infineon Technologies Ag | Halbleiterbauteil mit Gehäusekunststoffmasse, Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung desselben |
US7453157B2 (en) * | 2004-06-25 | 2008-11-18 | Tessera, Inc. | Microelectronic packages and methods therefor |
DE102005015036B4 (de) * | 2004-07-19 | 2008-08-28 | Qimonda Ag | Verfahren zur Montage eines Chips auf einer Unterlage |
DE102004037610B3 (de) * | 2004-08-03 | 2006-03-16 | Infineon Technologies Ag | Verfahren zur Verbindung einer integrierten Schaltung mit einem Substrat und entsprechende Schaltungsanordnung |
WO2006047028A2 (en) * | 2004-10-23 | 2006-05-04 | Freescale Semiconductor, Inc. | Packaged device and method of forming same |
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JP4744269B2 (ja) * | 2005-11-02 | 2011-08-10 | パナソニック株式会社 | 半導体装置とその製造方法 |
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US7868465B2 (en) * | 2007-06-04 | 2011-01-11 | Infineon Technologies Ag | Semiconductor device with a metallic carrier and two semiconductor chips applied to the carrier |
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KR101677322B1 (ko) * | 2014-04-16 | 2016-11-17 | 주식회사 동부하이텍 | 반도체 패키지 및 이를 제조하는 방법 |
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JPH1154658A (ja) * | 1997-07-30 | 1999-02-26 | Hitachi Ltd | 半導体装置及びその製造方法並びにフレーム構造体 |
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- 2003-08-29 US US10/651,522 patent/US6992380B2/en not_active Expired - Lifetime
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- 2004-08-27 KR KR1020040067913A patent/KR101096330B1/ko active IP Right Grant
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100934269B1 (ko) * | 2005-04-14 | 2009-12-28 | 샌디스크 코포레이션 | 반도체 및 전자 서브-시스템 패키징을 위한 칩 캐리어 기판및 인쇄 회로 기판 상의 강체 웨이브 패턴 설계 |
US9728477B2 (en) | 2014-07-30 | 2017-08-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of manufacturing a semiconductor device having scribe lines |
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US6992380B2 (en) | 2006-01-31 |
US7344916B2 (en) | 2008-03-18 |
US20050082649A1 (en) | 2005-04-21 |
JP2005079590A (ja) | 2005-03-24 |
US20060110927A1 (en) | 2006-05-25 |
KR101096330B1 (ko) | 2011-12-20 |
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