KR20030074870A - Method for fabricating metal power line of semiconductor device - Google Patents

Method for fabricating metal power line of semiconductor device Download PDF

Info

Publication number
KR20030074870A
KR20030074870A KR1020020013855A KR20020013855A KR20030074870A KR 20030074870 A KR20030074870 A KR 20030074870A KR 1020020013855 A KR1020020013855 A KR 1020020013855A KR 20020013855 A KR20020013855 A KR 20020013855A KR 20030074870 A KR20030074870 A KR 20030074870A
Authority
KR
South Korea
Prior art keywords
barrier metal
metal film
film
conductor
forming
Prior art date
Application number
KR1020020013855A
Other languages
Korean (ko)
Inventor
전인규
김승현
Original Assignee
동부전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 동부전자 주식회사 filed Critical 동부전자 주식회사
Priority to KR1020020013855A priority Critical patent/KR20030074870A/en
Publication of KR20030074870A publication Critical patent/KR20030074870A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a metal interconnection of a semiconductor device is provided to be capable of simplifying processes and surface scratch of a substrate without omitting touch-up processing. CONSTITUTION: After forming an interlayer dielectric(104) on a semiconductor substrate(100) having metal lines(102), a contact and a via hole are formed. The first barrier layer(108) is formed in the resultant structure. A conductive layer(110") is formed on the contact/via hole and planarized. The second barrier layer(112a), a metal film(114a) and the third barrier layer(116a) are sequentially formed on the conductive layer.

Description

반도체 소자의 금속 배선 형성 방법{METHOD FOR FABRICATING METAL POWER LINE OF SEMICONDUCTOR DEVICE}METHOD FOR FABRICATING METAL POWER LINE OF SEMICONDUCTOR DEVICE}

본 발명은 반도체 제조방법에 관한 것으로서, 특히 Ti과 실리콘/금속 배선이 접촉되는 콘택(contact)/비아(via)에 형성되는 도전성 물질의 평탄화 공정에서 발생되는 기판의 스크래치 및 절연막의 벗겨지는 것을 방지하는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor, and in particular, to prevent scratching of a substrate and peeling of an insulating layer generated in a planarization process of a conductive material formed at a contact / via in which Ti and a silicon / metal wire contact. A metal wiring formation method of a semiconductor element is described.

근래, 반도체 집적회로(이하 LSI라고 함)의 고집적화, 고성능화에 따라서 새로운 미세 가공 기술이 개발되고 있다. 화학기계연마(이하 CMP라고 함)법도 그 일예이고, LSI 제조공정, 특히 다층배선 형성공정에서의 층간 절연막의 평탄화, 금속플러그 형성, 매립배선형성에 있어서 빈번하게 이용되는 기술이다. 이 기술은, 예컨대 미국특허 제4,944,836호 공보에 개시되어 있다.Recently, new microfabrication technologies have been developed in accordance with high integration and high performance of semiconductor integrated circuits (hereinafter referred to as LSI). The chemical mechanical polishing (hereinafter referred to as CMP) method is one example, and is a technique frequently used in planarization of interlayer insulating films, metal plug formation, and buried wiring formation in the LSI manufacturing process, especially in the multilayer wiring formation process. This technique is disclosed, for example, in US Pat. No. 4,944,836.

도 1a 내지 도 1f는 종래 기술에 의한 반도체 소자의 금속 배선 형성 방법을 순차적으로 나타낸 공정 순서도로서, 여기에서는 다층 구조의 배선을 수직으로 연결하는 비아의 제조 공정에 대해 설명한다.1A to 1F are process flowcharts sequentially illustrating a metal wiring forming method of a semiconductor device according to the prior art, and a manufacturing process of a via for vertically connecting wirings having a multilayer structure will be described.

먼저 도 1a에 도시된 바와 같이, 반도체 기판(10)에 소자 공정을 실시하고 금속 배선(12)을 형성한다. 그리고 금속 배선(12)이 형성된 반도체 기판(10)의 구조물에 층간 절연막(14)을 형성하고 배선들 사이의 전기적 연결 통로인 비아홀(16)을 형성한다.First, as shown in FIG. 1A, an element process is performed on the semiconductor substrate 10, and the metal wiring 12 is formed. The interlayer insulating layer 14 is formed in the structure of the semiconductor substrate 10 on which the metal wiring 12 is formed, and the via hole 16, which is an electrical connection path between the wirings, is formed.

이어서 도 1b에 도시된 바와 같이, 비아홀(16)이 형성된 층간 절연막(14) 상부에 제 1장벽 금속막(18)으로서 Ti막(18a) 및 TiN막(18b)을 적층해서 형성한다. 이때, 제 1장벽 금속막(18)은 물리적기상증착(Physical Vapor Deposition : 이하 PVD라 함) 공정 또는 화학적기상증착(Chemical Vapor Deposition : 이하 CVD라 함) 공정으로 진행될 수 있으나 대개 PVD인 스퍼터링(sputtering) 방식으로 형성된다.Subsequently, as shown in FIG. 1B, the Ti film 18a and the TiN film 18b are formed by laminating the first barrier metal film 18 on the interlayer insulating film 14 on which the via holes 16 are formed. In this case, the first barrier metal film 18 may be a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process, but is usually PVD sputtering. ) Is formed in a manner.

그 다음 도 1c에 도시된 바와 같이, 제 1장벽 금속막(18)이 형성된비아홀(16)에 도전체 물질로서 텅스텐(W)(20)을 CVD로 증착하여 비아홀(16)을 매립한다.1C, tungsten (W) 20 is deposited by CVD as a conductive material in the via hole 16 on which the first barrier metal film 18 is formed, and the via hole 16 is buried.

그리고 나서 도 1d에 도시된 바와 같이, 화학적기계적연마(Chemical Mechanical Polishing: 이하 CMP라 함) 공정으로 텅스텐(20) 및 제 1장벽 금속막(18)을 연마한 후에 층간 절연막(14)의 상부에 잔존하는 텅스텐(20)을 제거하기 위해 터치 업(Touch-up) 공정을 통해 텅스텐 플러그(W plug:)(20')을 형성한다. 여기서, 텅스텐 플러그(20')는 비아를 구성하는 것으로 비아홀에 매립되는 텅스텐을 일컫는 것이다.Then, as shown in FIG. 1D, the tungsten 20 and the first barrier metal film 18 are polished by a chemical mechanical polishing (hereinafter referred to as CMP) process, and then, on the upper portion of the interlayer insulating film 14. In order to remove the remaining tungsten 20, a tungsten plug (W plug) 20 'is formed through a touch-up process. Here, the tungsten plug 20 'refers to tungsten embedded in the via hole as a part of the via.

그런 후에, 도 1e에 도시된 바와 같이, 상기 결과물 상에 제 2장벽 금속막(21), 금속층(22) 및 제 3장벽 금속막(23)을 순차적으로 형성한 후에 사진 공정을 진행하여 제 3장벽 금속막(23) 상부에 금속 배선을 정의하는 마스크 패턴(24)을 형성한다. 이때 제 2장벽 금속막(21)에 형성되는 금속층(22)으로는 알루미늄이다.Thereafter, as shown in FIG. 1E, the second barrier metal film 21, the metal layer 22, and the third barrier metal film 23 are sequentially formed on the resultant, and then the photographing process is performed. A mask pattern 24 defining metal wirings is formed on the barrier metal film 23. At this time, the metal layer 22 formed on the second barrier metal film 21 is aluminum.

그리고 도 1f에 도시된 바와 같이, 마스크 패턴(24)에 의해 드러난 제 3장벽 금속막(23)과 금속층(22) 및 제 2장벽 금속막(21)을 건식 식각 공정으로 패터닝한 후에 마스크 패턴(24)을 제거한다. 이로 인하여 텅스텐 플러그(20')의 상부에 알루미늄으로 이루어진 금속 배선을 형성하는데, 금속 배선은 패터닝된 제 2장벽 금속막(21a), 금속층(22a) 및 제 3장벽 금속막(23a)으로 구성된다.As shown in FIG. 1F, after the third barrier metal film 23 and the metal layer 22 and the second barrier metal film 21 exposed by the mask pattern 24 are patterned by a dry etching process, the mask pattern ( 24) Remove. This forms a metal wiring made of aluminum on top of the tungsten plug 20 ', which is composed of a patterned second barrier metal film 21a, a metal layer 22a and a third barrier metal film 23a. .

그러나, 비아에 텅스텐 플러그 형성 및 절연막의 평탄화를 위해서 CMP 공정 후에 진행되는 터치 업 공정에서는 아래와 같은 문제점을 유발한다.However, in the touch-up process performed after the CMP process to form a tungsten plug in the via and planarization of the insulating layer, the following problems are caused.

CMP 공정 진행중에 발생되는 파티클 또는 터치 업 공정 중에 발생되는 산화 물질에 의해서 기판 표면에 스크래치(연마흠(硏磨傷))의 발생하거나 비아홀이 형성된 층간 절연막이 벗겨져 후속되는 공정에 악영향을 미친다.Particles generated during the CMP process or oxidized materials generated during the touch-up process cause scratches on the surface of the substrate, or the interlayer insulating film having the via holes peeled off, which adversely affects subsequent processes.

본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 콘택/비아홀에 도전체를 매립한 후 제 1장벽 금속막 상에 소정의 두께의 도전체가 잔존하도록 CMP 공정을 진행함으로써 CMP 공정 이후에 진행되는 터치업 공정을 생략하여 반도체 기판의 스크래치 또는 층간 절연막이 벗겨지는 현상을 방지할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하고자 한다.An object of the present invention is to solve this problem of the prior art, after the CMP process by embedding the conductor in the contact / via hole and proceeding the CMP process so that the conductor having a predetermined thickness remains on the first barrier metal film By omitting the touch-up process to be carried out to provide a method for forming a metal wiring of the semiconductor device that can prevent the phenomenon of scratching or peeling the interlayer insulating film of the semiconductor substrate.

상기와 같은 목적을 달성하기 위하여 본 발명은, 도전 패턴 또는 도전 영역을 포함한 반도체 기판 상부에 층간 절연막을 형성하고 상기 층간 절연막에 콘택/비아홀을 형성하는 단계와 상기 콘택/비아홀이 형성된 층간 절연막 상부에 Ti막과 TiN막이 적층된 제 1장벽 금속막을 형성하는 단계와 상기 장벽 금속막이 형성된 콘택/비아홀에 도전체를 소정의 두께로 형성하고 상기 장벽 금속막에 도전체가 잔존하도록 상기 도전체를 CMP로 연마하는 단계와 상기 연마된 도전체 상에 제 2 장벽 금속막, 금속층, 제 2장벽 금속막을 순차적으로 형성하고, 상기 제 3장벽 금속막 상에 금속 배선을 정의하는 마스크 패턴을 형성하는 단계와 상기 마스크 패턴에 따라 상기 제 3장벽 금속막, 금속층, 제 2장벽 금속막, 패터닝된 도전체 및 장벽 금속막을 함께 패터닝하여 상기 금속 배선을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of forming an interlayer insulating film on a semiconductor substrate including a conductive pattern or a conductive region, forming a contact / via hole in the interlayer insulating film, and forming a contact / via hole on the interlayer insulating film. Forming a first barrier metal film in which a Ti film and a TiN film are laminated; and forming a conductor to a predetermined thickness in a contact / via hole in which the barrier metal film is formed, and polishing the conductor with CMP so that the conductor remains in the barrier metal film. And sequentially forming a second barrier metal film, a metal layer, and a second barrier metal film on the polished conductor, and forming a mask pattern defining metal wiring on the third barrier metal film. The third barrier metal film, the metal layer, the second barrier metal film, the patterned conductor, and the barrier metal film are patterned together according to a pattern. Forming a metal wiring.

도 1a 내지 1f는 종래 기술에 따른 배선 형성 과정을 나타내는 공정 순서 도이고,1A to 1F are process flowcharts illustrating a wire forming process according to the prior art;

도 2a 내지 2f는 본 발명에 따른 배선 형성 과정을 나타내는 공정 순서 도이다.2A to 2F are process flowcharts illustrating a process of forming a wire according to the present invention.

＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

100 : 기판 102 : 금속 배선100: substrate 102: metal wiring

104 : 층간 절연막 106 : 비아홀104: interlayer insulating film 106: via hole

108 : 제 1장벽 금속막 110 : 텅스텐108: first barrier metal film 110: tungsten

112 : 제 2장벽 금속막 114 : 금속층112: second barrier metal film 114: metal layer

116 : 제 3장벽 금속막 118 : 마스크 패턴116: third barrier metal film 118: mask pattern

본 발명의 실시 예는 다수개가 존재할 수 있으며, 이하에서 첨부한 도면을 참조하여 바람직한 실시 예에 대하여 상세히 설명하기로 한다. 이 기술 분야의 숙련자라면 이 실시 예를 통해 본 발명의 목적, 특징 및 이점들을 잘 이해할 수 있을 것이다.There may be a plurality of embodiments of the present invention, and a preferred embodiment will be described in detail below with reference to the accompanying drawings. Those skilled in the art will be able to better understand the objects, features and advantages of the present invention through this embodiment.

도 2a 내지 2f는 본 발명에 따른 반도체 소자의 다층 금속 배선 형성 방법을 순차적으로 도시한 공정 흐름 도이다.2A to 2F are process flow diagrams sequentially illustrating a method of forming a multilayer metal wiring of a semiconductor device according to the present invention.

먼저 도 2a 내지 2c에 도시된 바와 같이, 반도체 기판(100)에 소자 공정을 실시하고 금속 배선(102)을 형성한다. 그리고 금속 배선(102)이 형성된 반도체 기판(100)의 구조물에 형성된 층간 절연막(104)에 배선들 사이의 전기적 연결 통로인 비아홀(106)을 형성한다.First, as shown in FIGS. 2A to 2C, an element process is performed on the semiconductor substrate 100 and the metal wiring 102 is formed. The via hole 106, which is an electrical connection path between the wires, is formed in the interlayer insulating film 104 formed on the structure of the semiconductor substrate 100 on which the metal wires 102 are formed.

이어서 비아홀(106)이 형성된 층간 절연막(104) 상부에 제 1장벽 금속막(108)으로서 Ti막(108a) 및 TiN막(108b)을 적층해서 형성한 후에 장벽 금속막(108)이 형성된 비아홀(106)에 도전체 물질로서 텅스텐(W)(110)을 CVD로 증착하여 비아홀(106)을 매립한다.Subsequently, after the Ti film 108a and the TiN film 108b are laminated and formed as the first barrier metal film 108 on the interlayer insulating film 104 on which the via holes 106 are formed, the via holes in which the barrier metal film 108 is formed ( Tungsten (W) 110 is deposited as a conductive material in 106 by CVD to fill the via hole 106.

도 2d에 도시된 바와 같이, 화학적기계적연마(Chemical Mechanical Polishing: 이하 CMP라 함) 공정으로 텅스텐(110)을 연마하여 텅스텐 플러그(W plug:)(110')을 형성하는데, 이때 CMP은 제 1장벽 금속막(108) 상에 존재하는 텅스텐(110)을 완전히 제거하지 않고 제 1장벽 금속막(108)에서 대략 500Å 두께의 텅스텐(110)이 잔존하도록 연마한다.As shown in FIG. 2D, tungsten 110 is polished by a chemical mechanical polishing (CMP) process to form a tungsten plug (W plug) 110 ′, wherein the CMP is the first The tungsten (110) of approximately 500 mm thick remains in the first barrier metal film (108) without completely removing the tungsten (110) present on the barrier metal film (108).

도 2e에 도시된 바와 같이, 상기 결과물의 상부에 순차적으로 제 2장벽 금속막(112), 금속층(114) 및 제 3장벽 금속막(116)을 형성한 후에 사진 공정을 진행하여 제 3장벽 금속막(116) 상부에 금속 배선을 정의하는 마스크 패턴(118)을 형성한다. 이때 제 2장벽 금속막(112) 상에 형성되는 금속층(114)으로는 알루미늄이다.As shown in FIG. 2E, the second barrier metal film 112, the metal layer 114, and the third barrier metal film 116 are sequentially formed on the top of the resultant, followed by a photographic process to perform the third barrier metal. A mask pattern 118 defining metal wirings is formed over the film 116. At this time, the metal layer 114 formed on the second barrier metal film 112 is aluminum.

그리고 도 2f에 도시된 바와 같이, 마스크 패턴(118)에 의해 드러난 제 3장벽 금속막(116)과 금속층(114), 제 2장벽 금속막(112), 텅스텐 플러그(110') 및 제 1장벽 금속막(108)을 건식 식각 공정으로 패터닝한 후에 마스크 패턴(118)을 제거함으로써 패터닝된 텅스텐 플러그(110'')의 상부에 알루미늄으로 이루어진 금속 배선을 형성하는 제조 공정을 완료한다. 이때 금속 배선은 패터닝된 제 2장벽 금속막(112a), 금속층(114a) 및 제 3장벽 금속막(116a)으로 구성된다.As shown in FIG. 2F, the third barrier metal film 116 and the metal layer 114, the second barrier metal film 112, the tungsten plug 110 ′, and the first barrier are exposed by the mask pattern 118. After the metal film 108 is patterned by a dry etching process, the mask pattern 118 is removed to complete a manufacturing process of forming a metal wiring made of aluminum on top of the patterned tungsten plug 110 ″. At this time, the metal wiring is composed of a patterned second barrier metal film 112a, a metal layer 114a, and a third barrier metal film 116a.

이상 설명한 바와 같이, 콘택/비아홀에 도전체를 매립한 후에 CMP 공정 진행할 때 장벽 금속막의 상부에 증착된 도전체을 완전히 제거하지 않고 후술되는 금속 배선 공정을 진행함으로써, 터치업 공정을 생략할 수 있어 금속 배선 형성을 위한 공정을 단순화시킬 수 있는 효과가 있다.As described above, when the CMP process is performed after embedding the conductor in the contact / via hole, the touch-up process can be omitted by performing the metal wiring process described below without completely removing the conductor deposited on the barrier metal film. There is an effect that can simplify the process for forming the wiring.

또한, CMP 공정 후에 진행되는 터치업 공정에 따른 기판 표면의 스크래치와 층간 절연막이 벗겨지는 현상을 막을 수 있다. 이로 인하여 후술되는 금속 배선 형성 공정에서 발생되는 불량률을 줄일 수 있고 반도체 소자의 신뢰도 및 수율을 향상시킬 수 있는 효과가 있다.In addition, it is possible to prevent the phenomenon of scratching the surface of the substrate and peeling of the interlayer insulating layer due to the touch-up process performed after the CMP process. As a result, it is possible to reduce the defective rate generated in the metal wiring forming process described later and to improve the reliability and yield of the semiconductor device.

Claims (4)

도전 패턴 또는 도전 영역을 포함한 반도체 기판 상부에 층간 절연막을 형성하고 상기 층간 절연막에 콘택/비아홀을 형성하는 단계;Forming an interlayer insulating film over the semiconductor substrate including the conductive pattern or the conductive region and forming a contact / via hole in the interlayer insulating film; 상기 콘택/비아홀이 형성된 층간 절연막 상부에 Ti막과 TiN막이 적층된 제 1장벽 금속막을 형성하는 단계;Forming a first barrier metal film having a Ti film and a TiN film stacked on the interlayer insulating film on which the contact / via hole is formed; 상기 제 1장벽 금속막이 형성된 콘택/비아홀에 도전체를 소정의 두께로 형성하고 상기 장벽 금속막에 도전체가 잔존하도록 상기 도전체를 CMP로 연마하는 단계;Forming a conductor in a contact / via hole in which the first barrier metal film is formed to a predetermined thickness and polishing the conductor by CMP so that the conductor remains in the barrier metal film; 상기 연마된 도전체 상에 제 2장벽 금속막, 금속층, 제 3장벽 금속막을 순차적으로 형성하고, 상기 제 3장벽 금속막 상에 금속 배선을 정의하는 마스크 패턴을 형성하는 단계;Sequentially forming a second barrier metal film, a metal layer, and a third barrier metal film on the polished conductor, and forming a mask pattern defining metal wires on the third barrier metal film; 상기 마스크 패턴에 따라 상기 제 3장벽 금속막, 금속층, 제 2장벽 금속막, 패터닝된 도전체 및 제 1장벽 금속막을 함께 패터닝하여 상기 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.Patterning the third barrier metal film, the metal layer, the second barrier metal film, the patterned conductor, and the first barrier metal film together according to the mask pattern to form the metal wiring. How to form metal wiring. 제 1 항에 있어서,The method of claim 1, 상기 2절연막, 금속층, 제 2장벽 금속막, 패터닝된 도전체 및 제 1장벽 금속막은,The second insulating film, the metal layer, the second barrier metal film, the patterned conductor and the first barrier metal film, 상기 마스크 패턴에 맞추어 건식 식각 공정에 의해 패터닝되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The metal wiring forming method of the semiconductor device, characterized in that patterned by a dry etching process in accordance with the mask pattern. 제 1 항에 있어서,The method of claim 1, 상기 도전체는, 텅스텐으로 이루어지며 상기 패터닝된 도전체는 텅스텐 플러그인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.Wherein the conductor is made of tungsten and the patterned conductor is a tungsten plug-in. 제 1 항에 있어서,The method of claim 1, 상기 도전체의 연마 결과 장벽 금속막의 상부에 잔존하는 도전체의 두께는 500Å 인 것을 특징으로 하는 반도체 소자의 금속배선 형성 방법.The thickness of the conductor remaining on the barrier metal film as a result of the polishing of the conductor is 500 kW, the metal wiring forming method of a semiconductor device.
KR1020020013855A 2002-03-14 2002-03-14 Method for fabricating metal power line of semiconductor device KR20030074870A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020020013855A KR20030074870A (en) 2002-03-14 2002-03-14 Method for fabricating metal power line of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020020013855A KR20030074870A (en) 2002-03-14 2002-03-14 Method for fabricating metal power line of semiconductor device

Publications (1)

Publication Number Publication Date
KR20030074870A true KR20030074870A (en) 2003-09-22

Family

ID=32224792

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020013855A KR20030074870A (en) 2002-03-14 2002-03-14 Method for fabricating metal power line of semiconductor device

Country Status (1)

Country Link
KR (1) KR20030074870A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100645225B1 (en) * 2004-12-23 2006-11-10 동부일렉트로닉스 주식회사 Method for forming metal wiring for semiconductor device and semiconductor device therefore
KR100668960B1 (en) * 2004-12-23 2007-01-12 동부일렉트로닉스 주식회사 Metal line in semiconductor device and fabricating method threof
KR100787557B1 (en) * 2005-10-07 2007-12-21 엔이씨 일렉트로닉스 가부시키가이샤 Semiconductor device having improved metal wiring
KR101038584B1 (en) * 2009-07-08 2011-06-07 이미자 Bowling wrist protection righteousness angle controller

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960002060A (en) * 1994-06-17 1996-01-26 제임스 이. 앤더슨 Cache burst structure for parallel processing such as image processing
JP2001203267A (en) * 2000-01-21 2001-07-27 Matsushita Electric Ind Co Ltd Method of manufacturing semiconductor device
KR100327580B1 (en) * 1999-06-29 2002-03-14 박종섭 Method for forming metal line of a semiconductor device
KR100355863B1 (en) * 1999-12-23 2002-10-12 아남반도체 주식회사 a manufacturing method for lines of semiconductor devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960002060A (en) * 1994-06-17 1996-01-26 제임스 이. 앤더슨 Cache burst structure for parallel processing such as image processing
KR100327580B1 (en) * 1999-06-29 2002-03-14 박종섭 Method for forming metal line of a semiconductor device
KR100355863B1 (en) * 1999-12-23 2002-10-12 아남반도체 주식회사 a manufacturing method for lines of semiconductor devices
JP2001203267A (en) * 2000-01-21 2001-07-27 Matsushita Electric Ind Co Ltd Method of manufacturing semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100645225B1 (en) * 2004-12-23 2006-11-10 동부일렉트로닉스 주식회사 Method for forming metal wiring for semiconductor device and semiconductor device therefore
KR100668960B1 (en) * 2004-12-23 2007-01-12 동부일렉트로닉스 주식회사 Metal line in semiconductor device and fabricating method threof
KR100787557B1 (en) * 2005-10-07 2007-12-21 엔이씨 일렉트로닉스 가부시키가이샤 Semiconductor device having improved metal wiring
KR101038584B1 (en) * 2009-07-08 2011-06-07 이미자 Bowling wrist protection righteousness angle controller

Similar Documents

Publication Publication Date Title
JP2000106396A (en) Manufacture of semiconductor device
TWI690003B (en) Method for forming a dual damascene interconnect structure
US6258709B1 (en) Formation of electrical interconnect lines by selective metal etch
KR20030074870A (en) Method for fabricating metal power line of semiconductor device
JP2002299437A (en) Method of manufacturing semiconductor device
KR100571696B1 (en) Method For Manufacturing Semiconductor Devices
TW544857B (en) Manufacturing method of dual damascene structure
US6841471B2 (en) Fabrication method of semiconductor device
TW548789B (en) Method of forming metal line
KR100613384B1 (en) Method of forming interconnection line for semiconductor device
KR100955838B1 (en) Semiconductor device and method for forming metal line in the same
KR100498647B1 (en) Method for forming metal line of semiconductor device
KR100467815B1 (en) Semiconductor device and fabrication method thereof
KR20030002119A (en) Method for forming via hole by dual damascene process
KR100383084B1 (en) Plug forming method of semiconductor devices
KR100457740B1 (en) A method for manufacturing a multi-layer metal line of a semiconductor device
KR100668960B1 (en) Metal line in semiconductor device and fabricating method threof
KR100422912B1 (en) Method for forming contact or via hole of semiconductor devices
KR100688761B1 (en) Method for making metal line in semiconductor
KR20040050118A (en) Method of forming a metal line in a semiconductor device
KR100857989B1 (en) Metal line formation method of semiconductor device
KR100678008B1 (en) Method for fabricating metal line of semiconductor
KR100688719B1 (en) Method for forming a metal line in a semiconductor device
KR100393968B1 (en) method for forming dual damascene of semiconductor device
KR100306240B1 (en) Multilayer interconnection processing method in semiconducter

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application