548789 五、發明說明（1) 發明領域： 種 本發明係有關於一種半導體製程，特別是有關於一很 形成金屬線的方法，藉以維持金屬線之間距深寬比，避免 在金屬線間填入介電層時產生縫隙。 相關技術說明： 在積體電路（ICs )的應用上，導體、半導體及絕緣 層等材料已被廣泛使用，而薄膜沈積（thin film deposition)、微影製程（photolithography)及蝕刻程 序（etching )則為主要之半導體技術。其中，薄膜沈積 即是將上述各材料層沈積於待製晶圓表面，而微影製程則 是複製所欲形成之元件或電路圖案，並透過餘刻步驟，將 這些圖案轉移至待製晶圓表面各層以形成半導體元件如電 晶體或電容等。 ， 在完成元件製作之後，需接著製作金屬導線以連接各 兀件，亦即金屬化（metal丨izati〇n )製程。在金屬化製 程中，為了避免各元件或金屬導線因直接接觸而短路，故 必須在金屬線之間或元件之間形成絕緣層來作隔離，而用 來隔離之絕緣層一般稱之為内層介電層（inter_layer ^electric， ILD)及金屬層間介電層（inter_metai :iemD)，可用作電晶體、電容等半導體元件 _ -1 # π - / 隔離各金屬内連線之介電層。 , 知科从 ® 、，击了不斷縮小及積體電路積集度的增 加。相對地，用以連接各個； (λ . . Λ R ^ „個疋件的金屬内連線之線寬 (line width) 及金屬绫夕μ 3的線距（1 i n e s p a c e )需配548789 V. Description of the invention (1) Field of the invention: The present invention relates to a semiconductor process, and particularly to a method for forming metal wires, so as to maintain the aspect ratio between the metal wires and avoid filling in the metal wires. A gap is created in the dielectric layer. Relevant technical description: In the application of integrated circuits (ICs), materials such as conductors, semiconductors and insulation layers have been widely used, while thin film deposition, photolithography, and etching processes are Is the main semiconductor technology. Among them, the thin film deposition is to deposit the above-mentioned material layers on the surface of the wafer to be processed, and the lithography process is to copy the desired element or circuit patterns to be formed, and then transfer these patterns to the wafer to be processed through the remaining steps. Layers on the surface to form semiconductor elements such as transistors or capacitors. After the components are manufactured, metal wires need to be manufactured to connect the components, which is a metallization process. In the metallization process, in order to avoid short circuits between components or metal wires due to direct contact, an insulating layer must be formed between the metal wires or between the components for isolation. The insulating layer used for isolation is generally called the inner layer dielectric. The electric layer (inter_layer ^ electric, ILD) and the interlayer dielectric layer (inter_metai: iemD) can be used as semiconductor elements such as transistors and capacitors. -1 # π-/ Isolate the dielectric layer of each metal interconnect. , Zhike has continuously reduced and increased the integration degree of integrated circuits. In contrast, (λ.. Λ R ^ „line width of the metal interconnects of each piece of metal and line spacing (1 i n e s p a c e) of the metal wire)
第4頁 548789Page 4 548789
^兀=尺寸而縮小。然而，在藉由微影製程定義金 時，為了縮小線寬及線距而需增加解析度時， 莫 =且層厚度需降低而使後續的嶋程無法順利地：J的 亦：、，光阻層的厚度限制了積體電路積集度之提昇。二 令=用硬式I幕（hard mask)來製作金屬線時合使 屬線之間的間隙（gaP )深寬比（aspect ratio )二加 ，因而在利用物理氣相沉積法（physical vap〇r " deposition，PVD)或化學氣相沉積法（士仏 V”填入絕緣層，例如二氧化石夕或其他介 ，材=，以隔離金屬線時’容易在間隙内產生隙縫（ν〇Η )，導致絕緣效果變差而降低元件之可产。^ Wood = size while shrinking. However, when the gold is defined by the lithography process, when the resolution needs to be increased in order to reduce the line width and line spacing, Mo = and the layer thickness needs to be reduced so that the subsequent process cannot be smoothly: J's also: ,, light The thickness of the resistance layer limits the increase of the integration degree of the integrated circuit. Second order = Use hard mask to make metal wire and make the gap (gaP) aspect ratio between the two lines plus, so use physical vapor deposition method (physical vap〇r " deposition (PVD) or chemical vapor deposition (Shi V) fill in the insulation layer, such as stone dioxide or other media, material =, to isolate metal wires' easy to create gaps in the gap (ν〇Η ), Resulting in poor insulation and reducing the yield of components.
發明概述： X 有鑑於此，本發明之目 方法，其利用一氧化層作為 阻作為填洞材料來去除此罩 析度並維持金屬線之間距深 入介電層時產生孔洞。 的在於提供一種形成金屬線的 罩幕來形成金屬線，並利用光 幕’以同時增加微影製程之解 寬比’進而避免在金屬線間填 根據上述之目的，本發日月人 ，^ ^ ^ + A明挺供一種形成金屬線的方法 層、-抗反射層及一遮蔽圖宰声2々依序形成-金屬 ^ r*- ^ . 6J. a 敝圖案層，以遮蔽圖案層為罩幕， 依序蝕刻抗反射層及金屬層而形成—具有至少一開口之 ^圖案層；在遮蔽圖案層上形成一光阻層且填入開口内；， 方之光阻層及遮蔽圖案層以在開口内形成 餘留之先阻層，以及去除餘留之光阻層。其巾，遮蔽圖Summary of the invention: X In view of this, the purpose of the present invention is to use a oxide layer as a resist as a hole filling material to remove the mask resolution and maintain holes between metal lines when they penetrate deep into the dielectric layer. The purpose is to provide a metal wire cover to form a metal wire, and use a light curtain to 'increasing the lithographic process width ratio at the same time', thereby avoiding filling the metal wires between the metal wires. ^ ^ + A provides a method layer for forming a metal line, an anti-reflection layer, and a masking sound. 2々 Sequentially formed-metal ^ r *-^. 6J. A 敝 pattern layer, with the masking pattern layer as The mask is formed by sequentially etching the anti-reflection layer and the metal layer-a pattern layer having at least one opening; forming a photoresist layer on the masking pattern layer and filling the opening; and a square photoresist layer and the masking pattern layer in A remaining pre-resistance layer is formed in the opening, and the remaining photoresist layer is removed. Its towel, masking illustration
州789 五、發明說明（3) _____ 案層係南密度雷艰备 去除杭反射層Uri層。再者，藉由化學機械研磨法來 表面大體齊平於抗反射層表面。 使餘留之光阻 又根據上述之目的，本發明提供一 法，包括下列步驟：提# t形成金屬線的方 金：：案層；在遮蔽圖案層上形成一光阻層】；口之 之：則光阻層以露出遮蔽圖案層且在開口内 留之去除遮蔽圖案層以露出抗反射層；以及去除餘 者，葬A#斜^ ΐ遮蔽圖案層係咼讼度電漿氧化層。再 作為㈣光阻層，且接著藉由稀釋氫ι酸 作為餘刻劑以去除遮蔽圖案層。 亂酉欠 較佳實施例之詳細說明： ^ ^下配合第！到8圖說明本發明實施例之形成金屬線的 首先，明參照第1圖，提供一基底1 〇 〇 有半導體元件（未繪示）之石夕晶圓。在本實二^面= 基底100上沉積一介電層102，例如氧化矽層，以作為内声 介電層（ILD )。隨後，藉由習知薄膜沉積製程，在形成^ 有"電層102的基底1〇〇上方依序形成一金屬層，例如 一鋁金屬層、一抗反射層106，例如氮氧化矽（si〇N )或 氮化敛（TiN)、一遮蔽層108，例如高密度電聚氧化片 (HDP oxide )、一 光阻層 110。 曰State 789 V. Description of the invention (3) _____ The case layer is South Density, and the Uri layer is removed. Furthermore, the surface is substantially flush with the surface of the anti-reflection layer by a chemical mechanical polishing method. To make the remaining photoresist according to the above-mentioned object, the present invention provides a method, which includes the following steps: extracting gold to form a metal wire: a case layer; forming a photoresist layer on a masking pattern layer; For: the photoresist layer exposes the masking pattern layer and removes the masking pattern layer in the opening to expose the anti-reflection layer; and removes the rest, and the A # oblique ^ masking pattern layer is a plasma oxide layer. It is then used as a photoresist layer, and then the masking pattern layer is removed by diluting hydrogen acid as an after-treatment agent. Random owe Detailed description of the preferred embodiment: ^ ^ FIG. 8 illustrates the formation of a metal line according to an embodiment of the present invention. First, referring to FIG. 1, a substrate 100 having a semiconductor element (not shown) is provided. A dielectric layer 102, such as a silicon oxide layer, is deposited on the second surface of the substrate 100 as the inner acoustic dielectric layer (ILD). Subsequently, by a conventional thin film deposition process, a metal layer, such as an aluminum metal layer, an anti-reflection layer 106, such as silicon oxynitride (si ON) or nitride (TiN), a shielding layer 108, such as a high-density electro-polymerized oxide film (HDP oxide), a photoresist layer 110. Say
548789 五、發明說明（4) 接下來，請參照第2圖，藉由習知微影製程以形成光 阻圖案層110。接著，以光阻圖案層u〇作為罩幕來蝕刻遮 蔽層108，以形成具有複數開口 1〇ι之遮蔽圖案層Kg，並 露出抗反射層106表面。 接下來’請參照第3圖，在剝除圖案化之光阻層1 1 〇之 後，以遮蔽圖案層108作為一硬式罩幕（hard mask)來乾 钱刻抗反射層1 〇 6及金屬層1 〇 4，藉以形成抗反射圖案層 106及金屬圖案層1〇4而露出介電層1〇2表面及形成複數開 口 103 。此金屬圖案層1〇4係作為連接各半導體元件（未繪 不）的金屬線。另外’受到乾蝕刻的作用，由高密度電漿 氧化層所構成之遮蔽圖案層1 〇 8係呈島狀，如圖所示。 由於存在遮蔽圖案層1〇8的緣故，這些開口 1〇3具有高 深寬比，例如大於3· 5，因此後續在金屬線1〇4間填入介電 層來作為金屬線1 〇4間的隔離層時，易於介電層内部形成 縫隙而使元件可靠度降低。因此，在本實施例中，在填入 介電層前’會去除遮蔽圖案層1〇8。接下來，請參照第4 圖’在島狀的遮蔽圖案層108上形成一光阻層112且填入開 口 1 03 内。 、 接下來，請參照第5 a圖，利用抗反射圖案層1 8作為 餘刻終止層，並以化學機械研磨（chemical mechanicai polishing，CMP)法來去除抗反射圖案層1〇8上方之光阻 層112及遮蔽圖案層1〇8，而在開口 1〇3内形成餘留之光阻 層112a。因此，餘留之光阻層112&表面會大體齊平於抗反 射圖案層106表面。接著，請參照第7圖，剝除餘留之光阻548789 V. Description of the invention (4) Next, please refer to FIG. 2 to form a photoresist pattern layer 110 by a conventional lithography process. Next, using the photoresist pattern layer u0 as a mask, the masking layer 108 is etched to form a masking pattern layer Kg having a plurality of openings 10m, and the surface of the anti-reflection layer 106 is exposed. Next, please refer to FIG. 3. After the patterned photoresist layer 1 1 0 is stripped, the masking pattern layer 108 is used as a hard mask to dry the anti-reflection layer 1 06 and the metal layer. 104 to form the anti-reflection pattern layer 106 and the metal pattern layer 104 to expose the surface of the dielectric layer 102 and form a plurality of openings 103. The metal pattern layer 104 serves as a metal line connecting semiconductor elements (not shown). In addition, due to the effect of dry etching, the masking pattern layer 108 formed by a high-density plasma oxide layer is island-shaped, as shown in the figure. Because of the presence of the shielding pattern layer 108, these openings 103 have a high aspect ratio, for example, greater than 3.5, so a dielectric layer is subsequently filled in between the metal lines 104 as the metal lines 104. When an isolation layer is used, it is easy to form a gap inside the dielectric layer and reduce the reliability of the device. Therefore, in this embodiment, the masking pattern layer 108 is removed before the dielectric layer is filled. Next, referring to FIG. 4 ', a photoresist layer 112 is formed on the island-shaped masking pattern layer 108 and filled in the opening 103. Next, referring to FIG. 5a, the anti-reflection pattern layer 18 is used as the epitaxial stop layer, and the chemical resistance of the photoresist layer above the anti-reflection pattern layer 108 is removed by a chemical mechanical polishing (CMP) method. Layer 112 and the shielding pattern layer 108, and a remaining photoresist layer 112a is formed in the opening 103. Therefore, the surface of the remaining photoresist layer 112 & will be substantially flush with the surface of the anti-reflection pattern layer 106. Next, please refer to Figure 7 to remove the remaining photoresist
548789 五、發明說明（5) 層112a以完成全屬線1〇4之製作。 接下來，諝參照第5b圖， 遮蔽圖案層1〇8之外，太 /、了上述利用CMP法來去除 驟後，利用乾飯μ i a發月另一做法係在完成第4圖之步 圖案層回㈣光阻層112以露出島狀遮蔽 U2a。 且问樣在開口 103内形成一餘留之光阻層 隨後，請參照第6圖，# 刻劑並藉由旋轉蝕刻法Γ用稀釋.風氣酸（DHF)作為蝕 圖案層108以露+ / (SPln etchlns )來去除島狀遮蔽 光阻層η Λ用反射圖案層m °在㈣期μ，餘留之 ，同二ϊ =以保護金屬層104受到敍刻而損害。接著 線104’之ΙΠ乍、。7圖，剝除餘留之光阻層112a以完成金屬 以無使:硬式罩幕取代光阻，所 的問題。再者，Ϊ阿衫製解析度而造成光阻需薄化 ，所以金屬線之門於利用回蝕光阻的方式來去除硬式罩幕 介電層114時’介電ϋ比，持不變。亦即在後續填入 ，因此不會降低元電件層 會產生縫隙’如第8圖所示 限定發:月已以較佳實施例揭露如上，然其並非用以 神和範圍内，項技藝者’在不脫離本發明之精 當視後附之申與潤飾’因此本發明之保護範圍 T w月專利乾圍所界定者為準。 548789 圖式簡單說明 下文ί ί本發明之上述目的、特徵和優點能更明顯易懂， 下：W舉較佳實施例，並配合所附圖式，作詳細說明如 形成2 \圖係繪示出根據本發明實施例之在一基底上依序 y_二電層、金屬層、抗反射層、遮蔽層、及 面不意圖。 U ,曰 =2圖係繪示出第i圖中經由圖案化光阻層定義遮蔽層 < Μ面示意圖。 P圖係繪示出第2圖中經由遮蔽圖案層依序触刻抗反 射盾及下方之金屬層之剖面示意圖。 成光係繪示出在第3圖中的金屬圖案層上方及其中形 成先阻層之剖面示意圖。 弟5a圖係繪示出去士 及μ 圖中抗反射層上方之光阻層 汉4敝圖案層之剖面示意圖。 阻層：m出另-去除第4圖中抗反射層上方之光 示出第5b^抗反射層上方之遮蔽圖案層 示意圖 ^ 7圖係、’、曰7F出剝除第5a或6圖中餘留的光阻層之剖面 之 剖面Γ意圖圖係。緣示出在第7圖中金屬圖案層中填入介電層 [符號說明]548789 V. Description of the invention (5) The layer 112a is used to complete the production of the line 104. Next, referring to FIG. 5b, in addition to the masking pattern layer 108, the CMP method is used to remove the step, and the dry rice μ ia is used. Another method is to complete the pattern layer in FIG. 4 The photoresist layer 112 is masked to expose U2a in an island shape. In addition, a remaining photoresist layer is formed in the opening 103. Then, please refer to FIG. 6, # etchant and dilute it with a rotary etching method. DHF is used as the etching pattern layer 108 to expose + / (SPln etchlns) to remove the island-shaped masking photoresist layer η Λ with the reflective pattern layer m ° in the period μ, the rest, the same as the two = to protect the metal layer 104 from being damaged by the engraving. Then the line 104 ', the line II. Figure 7 shows the problem of stripping the remaining photoresist layer 112a to complete the metal without using: a hard mask to replace the photoresist. In addition, the photoresist needs to be thinned due to the resolution of the Ϊ-shirt system, so the gate of the metal wire uses the etch-back photoresist to remove the hard mask dielectric layer 114, and the dielectric ratio is unchanged. That is, it will be filled in later, so there will be no gaps in the element layer. 'Limited hair as shown in Figure 8: The month has been exposed as above with a preferred embodiment, but it is not used within the scope of the god. The "application and retouching attached to the present invention shall not be deviated from the essence of the present invention". Therefore, the scope of protection of the present invention is defined by the patent scope. 548789 The drawings briefly explain the following: The above-mentioned objects, features, and advantages of the present invention can be more clearly understood. Next: W give a preferred embodiment, and in conjunction with the attached drawings, make a detailed description, such as the formation of 2 drawings. According to the embodiment of the present invention, it is not intended that a y-two electrical layer, a metal layer, an anti-reflection layer, a shielding layer, and a surface are sequentially on a substrate. U, Y = 2 is a schematic diagram showing the masking layer < M plane defined by the patterned photoresist layer in the i-th figure. Figure P is a schematic cross-sectional view of the anti-reflection shield and the underlying metal layer sequentially touched by the masking pattern layer in Figure 2. The light-forming system is a schematic cross-sectional view showing that a pre-resistance layer is formed on and in the metal pattern layer in FIG. 3. Figure 5a is a schematic cross-sectional view of the photoresist layer Han 4 敝 pattern layer above the anti-reflection layer in the Tu and μ diagrams. Barrier layer: m-out-remove the light above the anti-reflection layer in Figure 4 to show 5b ^ the schematic diagram of the masking pattern layer above the anti-reflection layer ^ Figure 7a, ', 7F, stripping Figure 5a or 6 The cross-section Γ of the remaining photoresist layer is a schematic diagram. The edge shows that the dielectric layer is filled in the metal pattern layer in FIG. 7 [Symbol description]
548789 圖式簡單說明 100〜基底； 1 0 1、1 0 3 〜開口； 102、114〜介電層； 1 0 4〜金屬層； 1 0 6〜抗反射層； 1 0 8〜遮蔽層； 110、112〜光阻層； 1 1 2a〜餘留之光阻層。 HB· 0548-7631TWF(N);90119;spin.ptd 第10頁548789 The diagram briefly illustrates 100 ~ substrate; 1 0 1, 10 3 ~ opening; 102, 114 ~ dielectric layer; 104 ~ metal layer; 106 ~ anti-reflection layer; 108 ~ shielding layer; 110 112 ~ photoresist layer; 1 1 2a ~ remaining photoresist layer. HB0548-7631TWF (N); 90119; spin.ptd Page 10