KR20030003333A - Method for fabricating element in memory device - Google Patents

Method for fabricating element in memory device Download PDF

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KR20030003333A
KR20030003333A KR1020010038655A KR20010038655A KR20030003333A KR 20030003333 A KR20030003333 A KR 20030003333A KR 1020010038655 A KR1020010038655 A KR 1020010038655A KR 20010038655 A KR20010038655 A KR 20010038655A KR 20030003333 A KR20030003333 A KR 20030003333A
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South Korea
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via hole
diffusion barrier
semiconductor device
insulating layer
sidewall
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KR1020010038655A
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Korean (ko)
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KR100753119B1 (en
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이인행
김춘환
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to fill a via hole with tungsten and simplify a fabrication process by performing a plasma nitration process and a diffusion barrier forming process within the same chamber. CONSTITUTION: An interlayer dielectric(3) of HOSP(Hybrid Organic Siloxane Polymer) is formed on a semiconductor substrate including a conductor(2). A via hole for exposing the conductor(2) is formed by etching the interlayer dielectric(3). A surface of a sidewall of the via hole is nitrated by performing a plasma process for the surface of the sidewall of the via hole. The nitration process is performed by using NH3 or N2/H2. A diffusion barrier and an adhesive layer(6) are deposited thereon. A via plug is formed by performing a chemical vapor deposition process.

Description

반도체 소자 제조 방법{Method for fabricating element in memory device}Method for fabricating element in memory device

본 발명은 반도체 소자 제조 방법에 관한 것으로, 보다 상세하게는 RC 시간 지연을 감소시키기 위해 저유전율 절연막을 갖는 다층 금속배선의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a multilayer metal wiring having a low dielectric constant insulating film in order to reduce RC time delay.

반도체 장치의 고집적화에 따라 금속배선의 최소 선폭이 줄어듬과 동시에 금속선(metal line)들 사이의 간격도 줄어들게 되었고, 이에 따라 똑같은 유전율을갖는 층간 절연물을 사용할 때 금속선들 사이의 캐패시턴스가 증가하게 된다. 회로에서의 신호 전달 시간은 RC 시간 지연에 역으로 비례하므로, RC 시간 지연을 감소시켜 회로 성능을 개선시키기 위해서는 금속선들 사이의 절연층에서 유전율을 최소화하는 것이 바람직하다.As the integration of semiconductor devices increases, the minimum line width of the metal lines is reduced and the spacing between the metal lines is also reduced, thereby increasing the capacitance between the metal lines when using an interlayer insulator having the same dielectric constant. Since the signal propagation time in the circuit is inversely proportional to the RC time delay, it is desirable to minimize the dielectric constant in the insulating layer between the metal wires in order to reduce the RC time delay and improve the circuit performance.

RC 지연에 의해 소자의 동작속도가 느려지는 문제점을 해결하는 방법으로 새로운 저유전율 절연물을 층간절연물로 사용하는 시도가 활발히 진행중이다. 이중 HOSP(Hybrid Organic Siloxane Polymer)는 유전률이 약 2.5 이며 열안정성이 뛰어나고 갭 필링(Gap filling) 능력이 좋으며 낮은 스트레스를 가지는 등 많은 장점을 가지고 있어 차세대 반도체 소자의 층간절연층으로 사용되고 있다.Attempts have been made to use new low dielectric insulators as interlayer insulators to solve the problem of slowing the device operation speed due to RC delay. Hybrid organic siloxane polymer (HOSP) has a number of advantages, such as dielectric constant of about 2.5, excellent thermal stability, good gap filling capability, and low stress, and is used as an interlayer insulating layer of next-generation semiconductor devices.

통상, HOSP로 절연된 금속선을 비아를 통해 연결할 때 화학기상증착(Chemical Vapor Deposition, 이하 CVD)을 이용하여 비아에 텅스텐을 매립 한다.In general, when a metal wire insulated with HOSP is connected through a via, tungsten is buried in the via using chemical vapor deposition (CVD).

저유전율(Low-k) 재료중에 하나인 HOSP를 층간절연물로 사용하여 비아를 형성하는 경우 비아의 매립을 CVD을 이용하는 경우에 있어 문제점은 CVD 텅스텐 매립에 사용되는 WF6가스와 HOSP가 서로 접촉하는 경우 반응에 의해 HOSP층에 잠식(encroachment)이 발생한다는 점이다. 즉 텅스텐 증착 전에 진행되는 확산방지막으로 사용하는 베리어 메탈(barrier metal) 증착 공정에서 형성된 TiN이 비아의 측벽에 완벽하게 도포되지 않는 경우에 WF6가 측벽으로 침투하여 HOSP층내로 심한 잠식이 발생되어 안정적인 절연층을 확보하기가 불가능한 문제가 있다.In the case of forming vias using HOSP, one of the low-k materials, as an interlayer insulator, the problem of embedding vias in CVD is that the WF 6 gas used for CVD tungsten buried is in contact with each other. In this case, encroachment occurs in the HOSP layer by the reaction. In other words, when TiN formed in the barrier metal deposition process, which is used as a diffusion barrier before tungsten deposition, is not completely applied to the sidewalls of the vias, WF 6 penetrates into the sidewalls, causing severe erosion into the HOSP layer. There is a problem that it is impossible to secure an insulating layer.

이러한 문제를 해결하기 위하여 제시되는 방법으로, 플라즈마 처리를 통하여 비아 측면(HOSP측면)에 매우 얇은 실리콘 질화물을 형성시켜 WF6의 침투를 방지하는 방법을 사용한다.In order to solve this problem, a method of preventing the penetration of WF 6 by forming a very thin silicon nitride on the via side (HOSP side) through plasma treatment.

상기 문제를 해결하는 종래의 공정 순서를 살펴보면, 먼저 통상적인 반도체 소자의 공정중에서, 비아의 매립을 CVD로 텅스텐 매립하기 전에 , WF6가 비아측벽에 침투 되는 것을 방지하기 위한 실리콘 질화물을 RIE(Reactive Ion Etching) 챔버에서 플라즈마 처리에 의해 형성한다. 이렇게 비아 측면을 실리콘 질화물로 형성한 후 접착층(glue layer)및 확산 방지막으로 Ti/TiN 또는 TiN을 물리기상증착(Physical Vapor Deposition, 이하 PVD)으로 증착하고, 다음으로 CVD로 텅스텐 비아플러그를 형성한다.Referring to a conventional process sequence for solving the above problem, first, silicon nitride is used to prevent WF 6 from penetrating into the via sidewalls during CVD of tungsten via via CVD. Ion Etching) chamber is formed by plasma treatment. After the via side is formed of silicon nitride, Ti / TiN or TiN is deposited by physical vapor deposition (PVD) using a glue layer and a diffusion barrier layer, and then a tungsten via plug is formed by CVD. .

본 발명은 반도체 소자 제조 공정에 있어서, 저유전율 절연막을 갖는 다층 금속배선의 비아 제조 방법중, 층간절연층에서 텅스텐 플러그 형성시 플라즈마 처리에 의해 비아 측벽이 잠식되는 것을 방지시키고 제조 공정을 보다 단순화 하는데 적합한 반도체 소자 제조방법을 제공하는데 그 목적이 있다.The present invention provides a method of manufacturing a via of a multi-layered metal wiring having a low dielectric constant insulating film in a semiconductor device manufacturing process, to prevent via sidewalls from being eroded by plasma treatment when tungsten plug is formed in an interlayer insulating layer, and to simplify the manufacturing process. It is an object of the present invention to provide a method for manufacturing a suitable semiconductor device.

도1 내지 도2는 본 발명에 의한 공정 흐름도.1 to 2 is a process flow diagram according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 유전체 캡핑 레이어2 : 하부금속선1: dielectric capping layer 2: lower metal wire

3 : 층간절연층5 : 비아홀3: interlayer insulating layer 5: via hole

6 : 확산방지막6: diffusion barrier

상기 목적을 달성하기 위한 본 발명의 반도체 소자 제조방법은, 금속선이 형성된기판상에 저유전율 절연층을 형성하는 제1 단계; 상기 절연층을 선택적으로 식각하여 상기 금속선이 노출되는 비아 홀을 형성하는 제2 단계; 상기 비아홀 측벽의 표면을 플라즈마 처리 하여 표면을 질화시키는 제3 단계; 상기 제3 단계가 완료된 후, 상기 제3 단계를 진행한 동일 챔버에서 확산방지막 및 접착층을 증착하는 제4 단계; 및 상기 제4단계가 완료된 후, 상기 제4 단계를 진행한 동일 챔버에서 화학기상증착를 사용하여 비아 플러그 형성하는 제5 단계를 포함하여 이루어진다.The semiconductor device manufacturing method of the present invention for achieving the above object comprises a first step of forming a low dielectric constant insulating layer on a substrate on which a metal line is formed; Selectively etching the insulating layer to form a via hole through which the metal line is exposed; A third step of nitriding the surface of the via hole sidewall by plasma treatment; A fourth step of depositing a diffusion barrier and an adhesive layer in the same chamber where the third step is completed after the third step is completed; And a fifth step of forming via plugs using chemical vapor deposition in the same chamber where the fourth step is completed after the fourth step is completed.

본 발명은 상기의 실리콘 질화물의 형성을 통상의 RIE 챔버에서 진행한 후 PVD로 확산방지막 Ti/TiN을 증착하는 공정 대신, TiCl4을 이용한 CVD로 Ti를 증착 하는 것이다. TiCl4를 이용해서 Ti챔버에서 Ti 증착전 NH3를 이용한 플라즈마 처리로 같은 챔버에서 비아 측벽을 질화신킨 후, Ti를 증착하고 그 위에 TiN을 형성하는 방법이다.The present invention is to deposit Ti by CVD using TiCl 4 instead of the process of depositing the diffusion barrier Ti / TiN by PVD after the silicon nitride is formed in a conventional RIE chamber. TiCl 4 is a method of nitriding via via sidewalls in the same chamber by plasma treatment using NH 3 prior to Ti deposition in the Ti chamber, and then depositing Ti and forming TiN thereon.

TiCl4로Ti를 형성할 때의 경우 플라즈마 인핸스드 화학기상증착법(plasma enhanced chemical vapor deposition, 이하 PECVD)으로 증착할 때, 기체원으로는 TiCl4, TiN 및 H2를 사용한다. TiCl4로Ti를 형성하는 경우에는 표면의 대기중에 산화되는 것을 방지할 목적으로 사용하는 NH3또는 N2/H2등으로 플라즈마 질화 처리를 수행할 수 있다. 따라서 이 공정을 Ti 증착전 비아 측벽(즉 HOSP 측벽)의 플라즈마 질화 처리에 사용하게 되면, 동일 챔버에서 측벽의 질화 처리 및 확산방지막 형성을 연속적으로 처리함으로써 WF6에 의한 잠식(enchroachment)를 효과적으로 방지함과 동시에 공정의 단순화에 기여하게 된다.If at the time of forming the Ti as TiCl 4 to deposit a plasma-enhanced chemical vapor deposition method (plasma enhanced chemical vapor deposition, hereinafter PECVD), a gas source is used for TiCl 4, H 2, and TiN. In the case of forming Ti with TiCl 4 , plasma nitriding may be performed with NH 3 or N 2 / H 2 or the like used for the purpose of preventing oxidation in the atmosphere of the surface. Therefore, if this process is used for plasma nitridation of via sidewalls (ie HOSP sidewalls) prior to Ti deposition, the nitridation and diffusion barrier formation of the sidewalls in the same chamber is continuously performed to effectively prevent encroachment by WF 6 . At the same time, it contributes to the simplification of the process.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도1 내지 도2는 본 발명의 바람직한 실시예에 따른 반도체 제조 방법이다.1 to 2 are semiconductor manufacturing methods according to a preferred embodiment of the present invention.

먼저, 도1을 참조하여 살펴보면, 하부금속선(conduct)(2)과 HOSP의 층간절연층(3),유전체 캐핑레이어(dielectric capping layer)(1) 등의 하부구조를 형성한 다음, 상기 층간절연층(3)을 선택식각하여 상기 하부금속선(2)이 노출되는 비아홀(5)를 형성한다. 이 때 HOSP 위에는 캐핑(capping)층으로 도면에 도시된 것과 같이 PE-TEOS(plasma enhanced Tetra Ethly Orthosilicate)(4)를 형성 할 수 있다.First, referring to FIG. 1, a substructure such as a lower metal conductor 2, an interlayer insulating layer 3 of a HOSP, a dielectric capping layer 1, and the like are formed, and then the interlayer insulating layer is formed. The layer 3 is selectively etched to form a via hole 5 through which the lower metal line 2 is exposed. At this time, as shown in the figure, a capping layer may be formed on the HOSP as plasma enhanced Tetra Ethly Orthosilicate (PE-TEOS) 4.

이어서, 확산방지막의 증착을 위한 TiCl4Ti 챔버에서 NH3를 이용한 플라즈마 처리로 비아홀(5) 측벽의 표면을 질화시킨다(도1의 A부분). 상기 질화처리가 완료된 후 동일 챔버에서 Ti를 증착한다. 다음으로 CVD로 텅스텐의 접착층으로 사용되는 TiN(6)을 증착한다. 이 때 사용되는 TiN은 PVD, 금속 이온 플라즈마(IMP:Ionized metal plasma) 또는 유기메탈 화학기상증착(Matal Organic Chemical Vapor Depositon, 이하 MOCVD)으로 증착할 수 있다.Subsequently, the surface of the sidewall of the via hole 5 is nitrided by plasma treatment using NH 3 in the TiCl 4 Ti chamber for deposition of the diffusion barrier film (part A of FIG. 1). After the nitriding is completed, Ti is deposited in the same chamber. Next, TiN 6 used as an adhesive layer of tungsten is deposited by CVD. The TiN used at this time may be deposited by PVD, ionized metal plasma (IMP) or organic organic chemical vapor deposition (MOCVD).

다음으로 도2을 참조하여 살펴보면, 상기 TiN을 증착한 후에, CVD을 이용해서 텅스텐(7)으로 비아를 매립한다.Next, referring to FIG. 2, after depositing the TiN, vias are filled with tungsten 7 using CVD.

본 발명이 제시하는 또 다른 실시에는, 확산방지막 증착을 TiCl4대신 MOCVD TiN을 사용하여 동일하게 적용 할 수 있다. 즉 MOCVD TiN는 기체원으로 TDMAT(Tetra Di Methyl Titanium)를 사용하여 열분해로 기판에 Ti(O, C, N)을 형성한 후 N2/H2플라즈마 처리를 이용하여 박막내 O, C 농도를 감소시킴으로써 TiN 박막을 얻는 공정이다. 따라서 TiCl4 Ti에서와 마찬가지로 비아를 형성한 후 바로 MOCVD TiN 증착 챔버에서 N2/H2또는 NH3기체를 이용한 플라즈마 처리를 실시한 후 TiN을 동일챔버에서 진행함으로써 TiCl4Ti에서 사용하는 방법과 동일한 효과를 얻을 수 있다.In another implementation proposed by the present invention, diffusion barrier deposition can be equally applied using MOCVD TiN instead of TiCl 4 . That is, MOCVD TiN forms Ti (O, C, N) on the substrate by pyrolysis using TDMAT (Tetra Di Methyl Titanium) as a gas source, and then increases the concentration of O and C in the thin film using N 2 / H 2 plasma treatment. It is a process of obtaining a TiN thin film by reducing. Therefore, the same effect as the method used by the TiCl 4 Ti by forward after the formation of the via, as in TiCl4 Ti and then subjected to a plasma treatment with a N 2 / H 2 or NH 3 gas, just MOCVD TiN deposition chamber TiN in the same chamber Can be obtained.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것을 본 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and the present invention belongs to various permutations, modifications, and changes that can be made without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

본발명에 따르면, 저유전율 재료인 HOSP를 금속층간절연층으로 사용하는 경우, 플라즈마 처리에 의한 비아에서의 잠식을 해결하기 위한 반도체 제조 공정에 있어서, 플라즈마 질화 및 확산방지막 형성을 같은 챔버에서 수행함으로써 비아에 CVD로 텅스텐을 안정적으로 매립하면서 동시에 공정의 단순화에 기여한다.According to the present invention, in the case of using the low dielectric constant material HOSP as the interlayer insulating layer, in the semiconductor manufacturing process for solving the erosion in the vias by plasma treatment, by performing plasma nitride and diffusion barrier film formation in the same chamber Tungsten is reliably buried in via via CVD, while contributing to the simplification of the process.

Claims (5)

금속선이 형성된기판상에 저유전율 절연층을 형성하는 제1 단계;Forming a low dielectric constant insulating layer on the substrate on which the metal line is formed; 상기 절연층을 선택적으로 식각하여 상기 금속선이 노출되는 비아 홀을 형성하는 제2 단계;Selectively etching the insulating layer to form a via hole through which the metal line is exposed; 상기 비아홀 측벽의 표면을 플라즈마 처리 하여 표면을 질화시키는 제3 단계;A third step of nitriding the surface of the via hole sidewall by plasma treatment; 상기 제3 단계가 완료된 후, 상기 제3 단계를 진행한 동일 챔버에서 확산방지막 및 접착층을 증착하는 제4 단계; 및A fourth step of depositing a diffusion barrier and an adhesive layer in the same chamber where the third step is completed after the third step is completed; And 상기 제4단계가 완료된 후, 상기 제4 단계를 진행한 동일 챔버에서 화학기상증착를 사용하여 비아 플러그 형성하는 제5 단계After the fourth step is completed, a fifth step of forming via plugs using chemical vapor deposition in the same chamber in which the fourth step is performed 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 저유전율 절연층으로 HOSP를 사용하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of manufacturing a semiconductor device, characterized in that using the HOSP as the low dielectric constant insulating layer. 제 1 항에 있어서,The method of claim 1, 상기 비아홀 측벽의 표면을 질화시키는 것는 NH3또는 N2/H2를 사용하는 것을 특징으로 하는 반도체 소자 제조 방법.Nitriding the surface of the sidewall of the via hole uses NH 3 or N 2 / H 2 . 제 1 항에 있어서,The method of claim 1, 상기 확산방지막은 TiCl4/H2기체를 이용한 PECVD로 Ti를 증착하는 것을 특징으로 하는 반도체 소자 제조 방법.The diffusion barrier is a semiconductor device manufacturing method, characterized in that for depositing Ti by PECVD using TiCl 4 / H 2 gas. 제 1 항에 있어서,The method of claim 1, 상기 확산방지막은 플라즈마 처리를 이용하는 MOCVD TiN를 이용하는 것을 특징으로 하는 반도체 소자 제조 방법The diffusion barrier is a semiconductor device manufacturing method characterized in that using MOCVD TiN using a plasma treatment
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US7228128B2 (en) 2004-03-31 2007-06-05 Nec Corporation Automatic character code recognition/display system, method, and program using mobile telephone
KR100792605B1 (en) * 2005-06-06 2008-01-09 샤프 가부시키가이샤 Semiconductor device and manufacturing method therefor

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KR100336654B1 (en) * 1995-12-27 2002-12-05 주식회사 하이닉스반도체 Method for forming stacked via hole in semiconductor device
JP3323055B2 (en) * 1996-04-03 2002-09-09 株式会社東芝 Semiconductor device and manufacturing method thereof
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US7228128B2 (en) 2004-03-31 2007-06-05 Nec Corporation Automatic character code recognition/display system, method, and program using mobile telephone
US7720460B2 (en) 2004-03-31 2010-05-18 Nec Corporation Automatic character code recognition/display system, method, and program using mobile telephone
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