KR100753119B1 - Method for fabricating element in memory device - Google Patents

Method for fabricating element in memory device Download PDF

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KR100753119B1
KR100753119B1 KR1020010038655A KR20010038655A KR100753119B1 KR 100753119 B1 KR100753119 B1 KR 100753119B1 KR 1020010038655 A KR1020010038655 A KR 1020010038655A KR 20010038655 A KR20010038655 A KR 20010038655A KR 100753119 B1 KR100753119 B1 KR 100753119B1
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forming
layer
insulating layer
diffusion barrier
plasma treatment
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KR20030003333A (en
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이인행
김춘환
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
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Abstract

본 발명은 반도체 소자 제조 방법에 있어서, 저유전율 절연막을 갖는 다층 금속배선의 비아 제조 방법중, 층간절연층에서 텅스텐 플러그 형성시 플라즈마 처리에 의해 비아 측벽이 잠식되는 것을 방지시키는 제조 공정을 보다 단순화하기 위해 것으로, 이를 위한 본 발명의 반도체 소자 제조 방법은 금속선이 형성된 기판상에 절연층을 형성하는 단계, 상기 절연층을 선택적으로 식각하여 상기 금속선이 노출되는 비아 홀을 형성하는 단계, 상기 비아홀 측벽의 표면을 플라즈마 처리 하여 표면을 질화시키는 단계, 상기 비아홀의 표면을 따라 확산방지막 및 접착층을 증착하는 단계, 상기 확산방지막 및 접착층 상에 화학기상증착을 사용하여 비아 플러그 형성하는 단계를 포함하고 상기 플라즈마 처리 하여 표면을 질화시키는 단계, 상기 확산방지막 및 접착층을 증착하는 단계 및 상기 비아 플러그를 형성하는 단계를 동일 챔버에서 진행하는 것을 포함하여 이루어진다.The present invention relates to a method for manufacturing a semiconductor device, more particularly, to a method for manufacturing a via of a multilayered metal interconnection having a low dielectric constant insulating film, which further simplifies a manufacturing process for preventing a via side wall from being encroached by a plasma treatment in forming an interlayer insulating layer A method of fabricating a semiconductor device of the present invention includes forming an insulating layer on a substrate having a metal line formed thereon, selectively etching the insulating layer to form a via hole through which the metal line is exposed, Forming a via plug by chemical vapor deposition on the diffusion barrier layer and the adhesive layer; forming a via plug on the diffusion barrier layer and the adhesion layer by plasma treatment; Thereby nitriding the surface, The steps of forming the via plug depositing a chakcheung comprising one to progress in the same chamber.

반도체, 비아, 저유전율 층간 절연물,Semiconductors, vias, low dielectric constant interlayer insulators,

Description

반도체 소자 제조 방법{Method for fabricating element in memory device} BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]             

도1 내지 도2는 본 발명에 의한 공정 흐름도.
1 to 2 are process flow diagrams according to the present invention.

* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS

1 : 유전체 캡핑 레이어 2 : 하부금속선1: dielectric capping layer 2: bottom metal line

3 : 층간절연층 5 : 비아홀3: interlayer insulating layer 5: via hole

6 : 확산방지막
6: diffusion barrier

본 발명은 반도체 소자 제조 방법에 관한 것으로, 보다 상세하게는 RC 시간 지연을 감소시키기 위해 저유전율 절연막을 갖는 다층 금속배선의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a multilayered metal wiring having a low dielectric constant insulating film to reduce an RC time delay.

반도체 장치의 고집적화에 따라 금속배선의 최소 선폭이 줄어듬과 동시에 금속선(metal line)들 사이의 간격도 줄어들게 되었고, 이에 따라 똑같은 유전율을 갖는 층간 절연물을 사용할 때 금속선들 사이의 캐패시턴스가 증가하게 된다. 회로에서의 신호 전달 시간은 RC 시간 지연에 역으로 비례하므로, RC 시간 지연을 감소시켜 회로 성능을 개선시키기 위해서는 금속선들 사이의 절연층에서 유전율을 최소화하는 것이 바람직하다.As the semiconductor device is highly integrated, the minimum line width of the metal wiring is reduced and the interval between the metal lines is reduced. Accordingly, the capacitance between the metal lines is increased when the interlayer insulator having the same dielectric constant is used. Since the signal propagation time in the circuit is inversely proportional to the RC time delay, it is desirable to minimize the dielectric constant in the insulating layer between the metal lines in order to reduce the RC time delay and improve circuit performance.

RC 지연에 의해 소자의 동작속도가 느려지는 문제점을 해결하는 방법으로 새로운 저유전율 절연물을 층간절연물로 사용하는 시도가 활발히 진행중이다. 이중 HOSP(Hybrid Organic Siloxane Polymer)는 유전률이 약 2.5 이며 열안정성이 뛰어나고 갭 필링(Gap filling) 능력이 좋으며 낮은 스트레스를 가지는 등 많은 장점을 가지고 있어 차세대 반도체 소자의 층간절연층으로 사용되고 있다. Attempts have been actively made to use a new low dielectric constant insulator as an interlayer insulator as a method for solving the problem that the operation speed of the device is slowed by the RC delay. Hybrid Organic Siloxane Polymer (HOSP) has a dielectric constant of about 2.5 and has many advantages such as excellent thermal stability, good gap filling ability and low stress, and is used as an interlayer insulating layer of a next generation semiconductor device.

통상, HOSP로 절연된 금속선을 비아를 통해 연결할 때 화학기상증착(Chemical Vapor Deposition, 이하 CVD)을 이용하여 비아에 텅스텐을 매립 한다.Typically, tungsten is buried in vias using Chemical Vapor Deposition (CVD) when connecting HOSP-insulated metal lines through vias.

저유전율(Low-k) 재료중에 하나인 HOSP를 층간절연물로 사용하여 비아를 형성하는 경우 비아의 매립을 CVD을 이용하는 경우에 있어 문제점은 CVD 텅스텐 매립에 사용되는 WF6 가스와 HOSP가 서로 접촉하는 경우 반응에 의해 HOSP층에 잠식(encroachment)이 발생한다는 점이다. 즉 텅스텐 증착 전에 진행되는 확산방지막으로 사용하는 베리어 메탈(barrier metal) 증착 공정에서 형성된 TiN이 비아의 측벽에 완벽하게 도포되지 않는 경우에 WF6가 측벽으로 침투하여 HOSP층내로 심한 잠식이 발생되어 안정적인 절연층을 확보하기가 불가능한 문제가 있다. In the case of using a HOSP, which is one of the low-k materials, as the interlayer insulator to form the via hole, the problem of using the CVD for the via filling is that the WF 6 gas and HOSP used for the CVD tungsten buried contact each other In this case, encroachment occurs in the HOSP layer by the reaction. That is, when the TiN formed in the barrier metal deposition process used as the diffusion barrier before the tungsten deposition is not completely applied to the side wall of the via, the WF 6 penetrates into the side wall, causing severe erosion in the HOSP layer, There is a problem that it is impossible to secure an insulating layer.

이러한 문제를 해결하기 위하여 제시되는 방법으로, 플라즈마 처리를 통하여 비아 측면(HOSP측면)에 매우 얇은 실리콘 질화물을 형성시켜 WF6의 침투를 방지하는 방법을 사용한다.In order to solve this problem, a method of preventing the penetration of WF 6 by forming very thin silicon nitride on the side of the via (HOSP side) through plasma treatment is used.

상기 문제를 해결하는 종래의 공정 순서를 살펴보면, 먼저 통상적인 반도체 소자의 공정중에서, 비아의 매립을 CVD로 텅스텐 매립하기 전에 , WF6가 비아측벽에 침투 되는 것을 방지하기 위한 실리콘 질화물을 RIE(Reactive Ion Etching) 챔버에서 플라즈마 처리에 의해 형성한다. 이렇게 비아 측면을 실리콘 질화물로 형성한 후 접착층(glue layer)및 확산 방지막으로 Ti/TiN 또는 TiN을 물리기상증착(Physical Vapor Deposition, 이하 PVD)으로 증착하고, 다음으로 CVD로 텅스텐 비아플러그를 형성한다.
In order to solve the above-mentioned problems, a silicon nitride for preventing WF 6 from penetrating into the via sidewalls before RIE (Reactive Ion Etching) chamber. Ti / TiN or TiN is deposited by Physical Vapor Deposition (PVD) as a glue layer and a diffusion preventing film after the via side is formed of silicon nitride, and then a tungsten via plug is formed by CVD .

본 발명은 반도체 소자 제조 공정에 있어서, 저유전율 절연막을 갖는 다층 금속배선의 비아 제조 방법중, 층간절연층에서 텅스텐 플러그 형성시 플라즈마 처리에 의해 비아 측벽이 잠식되는 것을 방지시키고 제조 공정을 보다 단순화 하는데 적합한 반도체 소자 제조방법을 제공하는데 그 목적이 있다.
The present invention relates to a method of manufacturing a via of a multi-layer metal interconnection having a low dielectric constant insulating film in a semiconductor device manufacturing process, in which the via sidewalls are prevented from being eroded by the plasma treatment when forming the tungsten plug in the interlayer insulating layer, And an object of the present invention is to provide a method of manufacturing a suitable semiconductor device.

상기 목적을 달성하기 위한 본 발명의 반도체 소자 제조방법은, 금속선이 형성된 기판상에 절연층을 형성하는 단계, 상기 절연층을 선택적으로 식각하여 상기 금속선이 노출되는 비아 홀을 형성하는 단계, 상기 비아홀 측벽의 표면을 플라즈마 처리 하여 표면을 질화시키는 단계, 상기 비아홀의 표면을 따라 확산방지막 및 접착층을 증착하는 단계, 상기 확산방지막 및 접착층 상에 화학기상증착을 사용하여 비아 플러그 형성하는 단계를 포함하고 상기 플라즈마 처리 하여 표면을 질화시키는 단계, 상기 확산방지막 및 접착층을 증착하는 단계 및 상기 비아 플러그를 형성하는 단계를 동일 챔버에서 진행하는 것을 포함하여 이루어진다.According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising: forming an insulating layer on a substrate having a metal line; selectively etching the insulating layer to form a via hole through which the metal line is exposed; Forming a via plug by chemical vapor deposition on the diffusion barrier layer and the adhesive layer; and forming a via plug on the diffusion barrier layer and the adhesive layer by chemical vapor deposition, Plasma treatment to nitride the surface, depositing the diffusion barrier and adhesive layer, and forming the via plug in the same chamber.

본 발명은 상기의 실리콘 질화물의 형성을 통상의 RIE 챔버에서 진행한 후 PVD로 확산방지막 Ti/TiN을 증착하는 공정 대신, TiCl4을 이용한 CVD로 Ti를 증착 하는 것이다. TiCl4를 이용해서 Ti챔버에서 Ti 증착전 NH3를 이용한 플라즈마 처리로 같은 챔버에서 비아 측벽을 질화신킨 후, Ti를 증착하고 그 위에 TiN을 형성하는 방법이다. The present invention deposits Ti by CVD using TiCl 4 instead of the process of depositing the diffusion barrier Ti / TiN by PVD after the silicon nitride is formed in a conventional RIE chamber. TiCl 4 is used in the Ti chamber to nitridize the via sidewalls in the same chamber by plasma treatment with NH 3 prior to Ti deposition, followed by depositing Ti and forming TiN thereon.

TiCl4로 Ti를 형성할 때의 경우 플라즈마 인핸스드 화학기상증착법(plasma enhanced chemical vapor deposition, 이하 PECVD)으로 증착할 때, 기체원으로는 TiCl4, TiN 및 H2를 사용한다. TiCl4로 Ti를 형성하는 경우에는 표면의 대기중에 산화되는 것을 방지할 목적으로 사용하는 NH3 또는 N2/H2등으로 플라즈마 질화 처리를 수행할 수 있다. 따라서 이 공정을 Ti 증착전 비아 측벽(즉 HOSP 측벽)의 플라즈마 질화 처리에 사용하게 되면, 동일 챔버에서 측벽의 질화 처리 및 확산방지막 형성을 연속적으로 처리함으로써 WF6에 의한 잠식(enchroachment)를 효과적으로 방지함 과 동시에 공정의 단순화에 기여하게 된다.
With TiCl 4 In the case of forming Ti, TiCl 4 , TiN and H 2 are used as the source of the gas when plasma enhanced chemical vapor deposition (PECVD) is used. With TiCl 4 In the case of forming Ti, plasma nitridation treatment can be performed with NH 3 or N 2 / H 2 used for the purpose of preventing oxidation of the surface in the atmosphere. Therefore, The use of the process of plasma nitriding of Ti deposited before the via sidewalls (i.e. HOSP sidewall), by treatment of the nitriding treatment and the diffusion preventive film formed on the side wall is continuously in the same chamber prevent encroachment (enchroachment) by WF 6 effectively And contributes to the simplification of the process.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in order to facilitate the present invention by those skilled in the art.

도1 내지 도2는 본 발명의 바람직한 실시예에 따른 반도체 제조 방법이다.1 and 2 show a semiconductor manufacturing method according to a preferred embodiment of the present invention.

먼저, 도1을 참조하여 살펴보면, 하부금속선(conduct)(2)과 HOSP의 층간절연층(3),유전체 캐핑레이어(dielectric capping layer)(1) 등의 하부구조를 형성한 다음, 상기 층간절연층(3)을 선택식각하여 상기 하부금속선(2)이 노출되는 비아홀(5)를 형성한다. 이 때 HOSP 위에는 캐핑(capping)층으로 도면에 도시된 것과 같이 PE-TEOS(plasma enhanced Tetra Ethly Orthosilicate)(4)를 형성 할 수 있다. 1, a bottom structure such as a bottom metal conductor 2, an interlayer insulating layer 3 of HOSP, a dielectric capping layer 1 and the like are formed. Then, The layer 3 is selectively etched to form a via hole 5 through which the lower metal line 2 is exposed. At this time, a capped layer on the HOSP may be formed of PE-TEOS (plasma enhanced tetra ethyl orthosilicate) 4 as shown in the figure.

이어서, 확산방지막의 증착을 위한 TiCl4 Ti 챔버에서 NH3를 이용한 플라즈마 처리로 비아홀(5) 측벽의 표면을 질화시킨다(도1의 A부분). 상기 질화처리가 완료된 후 동일 챔버에서 Ti를 증착한다. 다음으로 CVD로 텅스텐의 접착층으로 사용되는 TiN(6)을 증착한다. 이 때 사용되는 TiN은 PVD, 금속 이온 플라즈마(IMP:Ionized metal plasma) 또는 유기메탈 화학기상증착(Metal Organic Chemical Vapor Depositon, 이하 MOCVD)으로 증착할 수 있다.Then, the surface of the side wall of the via hole 5 is nitrided by a plasma treatment using NH 3 in a TiCl 4 Ti chamber for deposition of a diffusion prevention film (part A of FIG. 1). After the nitriding process is completed, Ti is deposited in the same chamber. Next, TiN (6) used as an adhesive layer of tungsten is deposited by CVD. The TiN used in this case can be deposited by PVD, ionized plasma (IMP), or metal organic chemical vapor deposition (MOCVD).

다음으로 도2을 참조하여 살펴보면, 상기 TiN을 증착한 후에, CVD을 이용해서 텅스텐(7)으로 비아를 매립한다. Next, referring to FIG. 2, after depositing the TiN, vias are filled with tungsten (7) by CVD.                     

본 발명이 제시하는 또 다른 실시에는, 확산방지막 증착을 TiCl4 대신 MOCVD TiN을 사용하여 동일하게 적용 할 수 있다. 즉 MOCVD TiN는 기체원으로 TDMAT(Tetra Di Methyl Titanium)를 사용하여 열분해로 기판에 산소, 탄소 및 질소를 함유한 티타늄막 즉, Ti(O, C, N)을 형성한 후 N2/H2 플라즈마 처리를 이용하여 박막내 O, C 농도를 감소시킴으로써 TiN 박막을 얻는 공정이다. 따라서 TiCl4 Ti에서와 마찬가지로 비아를 형성한 후 바로 MOCVD TiN 증착 챔버에서 N2/H2 또는 NH3기체를 이용한 플라즈마 처리를 실시한 후 TiN을 동일챔버에서 진행함으로써 TiCl4 Ti에서 사용하는 방법과 동일한 효과를 얻을 수 있다.In another embodiment proposed by the present invention, diffusion barrier film deposition can be equally applied using MOCVD TiN instead of TiCl 4 . I.e., MOCVD TiN, after forming the gas source as TDMAT (Tetra Di Methyl Titanium) a titanium film That is, Ti (O, C, N) contains oxygen, carbon and nitrogen on a substrate by thermal decomposition using the N 2 / H 2 Is a step of obtaining a TiN thin film by reducing O and C concentration in the thin film by using a plasma treatment. Therefore, the same effect as the method used by the TiCl 4 Ti by forward after the formation of the via, as in TiCl4 Ti and then subjected to a plasma treatment with a N 2 / H 2 or NH 3 gas, just MOCVD TiN deposition chamber TiN in the same chamber Can be obtained.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것을 본 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be apparent to those of ordinary skill in the art.

본발명에 따르면, 저유전율 재료인 HOSP를 금속층간절연층으로 사용하는 경우, 플라즈마 처리에 의한 비아에서의 잠식을 해결하기 위한 반도체 제조 공정에 있어서, 플라즈마 질화 및 확산방지막 형성을 같은 챔버에서 수행함으로써 비아에 CVD로 텅스텐을 안정적으로 매립하면서 동시에 공정의 단순화에 기여한다.
According to the present invention, in the case of using HOSP, which is a low dielectric constant material, as a metal interlayer insulating layer, plasma nitridation and diffusion prevention film formation are performed in the same chamber in a semiconductor manufacturing process for solving the vias in vias by plasma treatment Tungsten can be stably buried in the via by CVD and at the same time contributes to simplification of the process.

Claims (5)

금속선이 형성된 기판상에 절연층을 형성하는 단계;Forming an insulating layer on a substrate having a metal line formed thereon; 상기 절연층을 선택적으로 식각하여 상기 금속선이 노출되는 비아 홀을 형성하는 단계;Forming a via hole through which the metal line is exposed by selectively etching the insulating layer; 상기 비아홀 측벽의 표면을 플라즈마 처리 하여 표면을 질화시키는 단계; Nitriding the surface of the side wall of the via hole by plasma treatment; 상기 비아홀의 표면을 따라 확산방지막 및 접착층을 증착하는 단계; 및Depositing a diffusion barrier layer and an adhesive layer along the surface of the via hole; And 상기 확산방지막 및 접착층 상에 화학기상증착을 사용하여 비아 플러그 형성하는 단계Forming a via plug using chemical vapor deposition on the diffusion barrier layer and the adhesive layer 를 포함하고 상기 플라즈마 처리 하여 표면을 질화시키는 단계, 상기 확산방지막 및 접착층을 증착하는 단계 및 상기 비아 플러그를 형성하는 단계를 동일 챔버에서 진행하는 것을 포함하는 반도체 소자 제조 방법. And the step of nitriding the surface by the plasma treatment comprises depositing the diffusion barrier layer and the adhesive layer and forming the via plug in the same chamber. 제 1 항에 있어서,The method according to claim 1, 상기 절연층으로 HOSP(Hybrid Organic Siloxane Polymer)를 사용하는 것을 특징으로 하는 반도체 소자 제조 방법.Wherein a HOSP (Hybrid Organic Siloxane Polymer) is used as the insulating layer. 제 1 항에 있어서,The method according to claim 1, 상기 비아홀 측벽의 표면을 질화시키는 것는 NH3 또는 N2/H2를 사용하는 것을 특징으로 하는 반도체 소자 제조 방법.Wherein NH 3 or N 2 / H 2 is used for nitriding the surface of the side wall of the via hole. 제 1 항에 있어서,The method according to claim 1, 상기 확산방지막은 TiCl4/H2 기체를 이용한 PECVD로 Ti를 증착하는 것을 특징으로 하는 반도체 소자 제조 방법.Wherein the diffusion barrier layer is formed by depositing Ti by PECVD using TiCl 4 / H 2 gas. 제 1 항에 있어서, The method according to claim 1, 상기 확산방지막은 플라즈마 처리를 이용하는 MOCVD TiN를 이용하는 것을 특징으로 하는 반도체 소자 제조 방법Wherein the diffusion preventing film is made of MOCVD TiN using a plasma process.
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