KR20030002647A - Method for fabricating SRAM device - Google Patents
Method for fabricating SRAM device Download PDFInfo
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- KR20030002647A KR20030002647A KR1020010038327A KR20010038327A KR20030002647A KR 20030002647 A KR20030002647 A KR 20030002647A KR 1020010038327 A KR1020010038327 A KR 1020010038327A KR 20010038327 A KR20010038327 A KR 20010038327A KR 20030002647 A KR20030002647 A KR 20030002647A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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Abstract
Description
본 발명은 에스램소자의 제조방법에 관한 것으로서, 보다 상세하게는 Vss콘택형성시에 P웰 픽업을 동시에 형성하여 주므로써 웰저항을 낮출수 있는 에스램소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing an SRAM device, and more particularly, to a method for manufacturing an SRAM device capable of lowering well resistance by simultaneously forming a P well pickup at the time of forming a Vss contact.
최근에 개발되고 있는 8M 또는 4M 슬로우 에스램의 경우에, 웰이 래치업(latch up)과 SER 특성을 개선하기 위하여, 매립 N웰구조로 형성되어 있다.In the case of the recently developed 8M or 4M slow SRAM, the wells are formed with buried N well structures in order to improve latch up and SER characteristics.
이러한 종래기술에 따른 에스램소자의 제조방법을 도 1 내지 도 3을 참조하여 설명하면 다음과 같다.The method of manufacturing the SRAM device according to the related art will be described with reference to FIGS. 1 to 3 as follows.
도 1은 종래 기술에 따른 에스램소자의 제조방법에 있어서, 매립 N웰을 적용한 경우와 적용하지 않은 경우에 따른 P웰의 저항변화를 도시한 그래프이다.1 is a graph illustrating a resistance change of a P well according to a case in which a buried N well is applied or not, according to the related art.
도 2는 종래기술에 따른 에스램소자의 제조방법에 있어서, 매립N웰을 적용한 경우와 적용하지 않은 경우에 따른 전압에 대한 액세스 트랜지스터의 전류변화를 도시한 그래프이다.FIG. 2 is a graph illustrating a change in current of an access transistor with respect to a voltage according to whether a buried N well is applied or not, according to the related art.
도 3은 종래기술에 따른 에스램소자의 제조방법에 있어서, 에스램소자의 레이아웃도이다.3 is a layout diagram of an SRAM device in the method of manufacturing an SRAM device according to the related art.
종래기술에 따른 에스램소자의 제조방법에 있어서는, 도 1에 도시된 바와같이, 매립 N웰을 적용하지 않은 경우에는 P웰이 P형 기판내에 형성되어 있어, P웰저항이 상대적으로 낮아 문제가 되지 않았으나, 매립 N웰을 적용하는 경우에는 P웰의 저항이 증가하게 되었다.In the method of manufacturing the SRAM device according to the prior art, as shown in FIG. 1, when the buried N well is not applied, the P well is formed in the P-type substrate, so that the P well resistance is relatively low. However, when the embedded N well is applied, the resistance of the P well is increased.
또한, 셀 블럭내부에는 P웰 픽업(pick-up)이 존재하지 않으므로 컬럼 (column) 방향의 셀중 가운데 부분의 P웰 저항은 상당히 높아지게 된다.In addition, since there is no P well pick-up inside the cell block, the P well resistance of the center portion of the cell in the column direction becomes considerably higher.
한편, 도 2에 도시된 바와같이, 전압 대 전류 측정시에 P웰 저항에 10 KΩ을 추가하여 웰 저항 증가에 따른 영향을 알 수 있다.On the other hand, as shown in Figure 2, it can be seen that the effect of increasing the well resistance by adding 10 KΩ to the P well resistance when measuring voltage vs. current.
그리고, 도 3에 도시된 바와같이, 에스램소자의 레이아웃도에서, P웰영역상에서 Vss 콘택부가 소자분리영역상에 있지 않고 활성영역상에 배치되어 있고, N웰영역상에서 Vcc 콘택부가 활성영역상에 배치되어 있다.3, in the layout diagram of the SRAM element, in the P well region, the Vss contact portion is disposed on the active region instead of the element isolation region, and the Vcc contact portion on the N well region is on the active region. Is placed on.
따라서, 종래기술에 있어서는 P웰 저항이 높아지면 매립 웰을 적용한 경우에 6 V 이하에서 스냅 백 (snap back) 현상이 발생하게 되어 디바이스의 높은 Vcc 패일(fail)을 유발시키는 원인이 된다.Therefore, in the related art, when the P well resistance is increased, a snap back phenomenon occurs at 6 V or less when the buried well is applied, which causes a high Vcc fail of the device.
현재, 셀어레이 내부에는 P웰 픽업이 존재하지 않아 P웰 저항이 최대가 되는 지역에서는 상기와 같은 현상의 발생이 우려된다.At present, there is a concern that such a phenomenon occurs in an area where P well pickup does not exist inside the cell array and P well resistance is maximized.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 셀 Vss콘택 형성시에 P웰 픽업을 동시에 형성하므로써 셀크기의 증가없이 P웰 저항을 감소시킬 수 있는 에스램소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, the method of manufacturing an SRAM device that can reduce the P well resistance without increasing the cell size by simultaneously forming the P well pickup at the time of forming the cell Vss contact The purpose is to provide.
도 1은 종래 기술에 따른 에스램소자의 제조방법에 있어서, 매립 N웰을 적용한 경우와 적용하지 않은 경우에 따른 P웰의 저항변화를 도시한 그래프이다.1 is a graph illustrating a resistance change of a P well according to a case in which a buried N well is applied or not, according to the related art.
도 2는 종래기술에 따른 에스램소자의 제조방법에 있어서, 매립N웰을 적용한 경우와 적용하지 않은 경우에 따른 전압에 대한 액세스 트랜지스터의 전류변화를 도시한 그래프이다.FIG. 2 is a graph illustrating a change in current of an access transistor with respect to a voltage according to whether a buried N well is applied or not, according to the related art.
도 3은 종래기술에 따른 에스램소자의 제조방법에 있어서, 에스램소자의 레이아웃도이다.3 is a layout diagram of an SRAM device in the method of manufacturing an SRAM device according to the related art.
도 4는 본 발명에 따른 에스램소자의 제조방법에 있어서, 에스램소자의 레이아웃도이다.4 is a layout diagram of an SRAM device in the method of manufacturing an SRAM device according to the present invention.
도 5 내지 도 8은 본 발명에 따른 에스램소자의 제조방법을 설명하기 위한 공정단면도로서, 도 4의 Ⅴ-Ⅴ선에 따른 단면도이다.5 to 8 are cross-sectional views taken along line VV of FIG. 4 as a cross-sectional view illustrating a method of manufacturing an SRAM device according to the present invention.
[도면부호의설명][Description of Drawing Reference]
11 : 반도체기판 13 : P웰11: semiconductor substrate 13: P well
15 : N웰 17 : 트렌치15: N well 17: trench
19, 27 : P+영역 21 : N+ 영역19, 27: P + region 21: N + region
23 : 제1 감광막패턴 25a : 제2감광막패턴23: first photosensitive film pattern 25a: second photosensitive film pattern
29 : 층간절연막 31 : 제3감광막패턴29: interlayer insulating film 31: third photosensitive film pattern
33a : 제1콘택홀 33b : 제2콘택홀33a: first contact hole 33b: second contact hole
상기 목적을 달성하기 위한 본 발명에 따른 에스램소자의 제조방법은, 제1도전형 웰과 제2도전형 웰 및 이들 경계부분에 소자분리영역이 형성된 반도체기판을 제공하는 단계와; 상기 제1도전형웰내에 제1도전형 불순물과 제2도전형 불순물을 이온주입하여 제1도전형 제1활성영역과 제2도전형 활성영역을 형성하는 단계; 상기 제2도전형 웰내에 제1도전형 불순물을 이온주입하여 제1도전형 제2활성영역을 형성하는 단계; 상기 전체 구조의 상면에 층간절연막을 형성하는 단계; 상기 층간절연막상에 상기 제1도전형 웰과 소자분리영역의 경계부분과 함께 상기 제2도전형 웰의 일부분에 대응하는 부분을 노출시키는 감광막패턴을 형성하는 단계; 및 상기 감광막패턴을 마스크로 상기 층간절연막과 소자분리영역을 선택적으로 제거하여 상기 제1도전형 제1활성영역을 노출시키는 제1콘택홀과 상기 제1도전형 제2활성영역의 상면을 노출시키는 제2콘택홀을 형성하는 단계;를 포함하여 구성되는 것을 특징으로한다.According to another aspect of the present invention, there is provided a method of manufacturing an SRAM device, including: providing a first conductive well, a second conductive well, and a semiconductor substrate on which a device isolation region is formed; Ion-implanting a first conductive impurity and a second conductive impurity into the first conductive well to form a first conductive type first active region and a second conductive type active region; Implanting a first conductive type impurity into the second conductive well to form a first conductive type second active region; Forming an interlayer insulating film on an upper surface of the entire structure; Forming a photoresist pattern on the interlayer insulating layer to expose a portion corresponding to a portion of the second conductive well together with a boundary between the first conductive well and the isolation region; And selectively removing the interlayer insulating layer and the device isolation region using the photoresist pattern as a mask to expose a top surface of the first contact hole exposing the first conductive type first active region and the top surface of the first conductive type second active region. Forming a second contact hole; characterized in that comprises a.
이하, 본 발명에 따른 반도체소자의 에스램소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing an SRAM device of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 4는 본 발명에 따른 에스램소자의 제조방법에 있어서, 에스램소자의 레이아웃도이다.4 is a layout diagram of an SRAM device in the method of manufacturing an SRAM device according to the present invention.
도 5 내지 도 8은 본 발명에 따른 에스램소자의 제조방법을 설명하기 위한 공정단면도로서, 도 4의 Ⅴ-Ⅴ선에 따른 단면도이다.5 to 8 are cross-sectional views taken along line VV of FIG. 4 as a cross-sectional view illustrating a method of manufacturing an SRAM device according to the present invention.
본 발명에 따른 에스램소자의 제조방법에 있어서, 도 4에 도시된 바와같이, P웰영역상에서 Vss 와 P웰 픽업 부분이 소자분리영역과 활성영역상에 걸쳐 배치되어 있고, N웰영역상에서 Vcc는 활성영역상에만 배치되어 있다.In the method for manufacturing the SRAM device according to the present invention, as shown in FIG. 4, Vss and P well pick-up portions are arranged on the P well region and across the element isolation region and the active region, and Vcc on the N well region. Is placed only on the active area.
한편, 본 발명에 따른 에스램소자의 제조방법은, 먼저 도 5에 도시된 바와같이, 반도체기판(11)내에 P웰(13)과 N웰(15)을 형성하고, 상기 P웰(13) 및 N웰(15)사이에는 트렌지 소자분리막(17)을 형성한다.Meanwhile, in the method of manufacturing the SRAM device according to the present invention, as shown in FIG. 5, the P well 13 and the N well 15 are formed in the semiconductor substrate 11, and the P well 13 is formed. And a trench isolation layer 17 is formed between the N wells 15.
그다음, 상기 전체 구조의 상면에 제1감광막(미도시)을 도포하고, 상기 제1감광막(미도시)을 포토리소그래피공정기술을 이용한 노광 및 현상공정을 통해 선택적으로 제거하여 상기 P웰(13)부분을 노출시키는 제1감광막패턴(23)을 형성한다.Next, a first photoresist film (not shown) is applied to the upper surface of the entire structure, and the first photoresist film (not shown) is selectively removed through an exposure and development process using a photolithography process technology to form the P well 13. The first photoresist pattern 23 exposing the portion is formed.
이어서, 상기 제1감광막패턴(19)을 마스크로 상기 P웰(13)내에 P+ 불순물과 N+ 불순물을 순차적으로 이온주입하여 제1P+영역(21)과 N+영역(23)을 각각 형성한다.Subsequently, P + impurities and N + impurities are sequentially ion-implanted into the P well 13 using the first photoresist pattern 19 as a mask to form the first P + region 21 and the N + region 23, respectively.
그다음, 도 6에 도시된 바와같이, 제1감광막패턴(23)을 제거하고, 상기 전체 구조의 상면에 제2감광막(25)을 도포하고, 상기 제1감광막(25)을 포토리소그래피공정기술을 이용한 노광 및 현상공정을 통해 선택적으로 제거하여 상기 N웰(15)부분을 노출시키는 제1감광막패턴(25a)을 형성한다.Next, as shown in FIG. 6, the first photoresist layer pattern 23 is removed, the second photoresist layer 25 is coated on the upper surface of the entire structure, and the first photoresist layer 25 is subjected to a photolithography process technique. The first photoresist layer pattern 25a exposing the N well 15 may be formed by selectively removing the same through the exposure and development processes.
이어서, 도 7에 도시된 바와같이, 상기 제1감광막패턴(25a)을 마스크로 상기 N웰(15)내에 P+ 불순물을 이온주입하여 제2P+영역(27)을 형성한다.Subsequently, as illustrated in FIG. 7, P + impurities are implanted into the N well 15 using the first photoresist pattern 25a as a mask to form a second P + region 27.
그다음, 도 8에 도시된 바와같이, 제2감광막패턴(25)을 제거하고, 상기 전체 구조의 상면에 층간절연막(29)을 증착하고, 상기 층간절연막(29)상에 제3감광막(미도시)을 도포한다.Next, as shown in FIG. 8, the second photoresist film pattern 25 is removed, an interlayer insulating film 29 is deposited on the upper surface of the entire structure, and a third photoresist film (not shown) is formed on the interlayer insulating film 29. ) Is applied.
이어서, 상기 제3감광막(미도시)을 포토리소그래피공정기술을 이용한 노광및 현상공정을 통해 선택적으로 제거하여 상기 P웰(13)과 트렌치소자분리영역(17)의 경계부분과 함께 상기 N웰(15)의 일부분을 각각 노출시키는 제3감광막패턴(31)을 형성한다.Subsequently, the third photoresist film (not shown) may be selectively removed through an exposure and development process using a photolithography process technology to form the N wells together with the boundary portions of the P well 13 and the trench isolation region 17. A third photoresist pattern 31 is formed to expose a portion of the substrate 15, respectively.
그다음, 상기 제3감광막패턴(31)을 마스크로 상기 층간절연막(29)을 선택적으로 제거하여 제1콘택홀(33a)과 제2콘택홀(33b)을 동시에 형성한다. 이때, 상기 제1콘택홀(33a) 형성시에 상기 트렌치 소자분리영역(17)의 일부분도 동시에 제거되어 상기 P웰(13)내에 형성된 P+영역(21)이 노출된다.Next, the interlayer insulating layer 29 is selectively removed using the third photoresist pattern 31 as a mask to simultaneously form the first contact hole 33a and the second contact hole 33b. At this time, when the first contact hole 33a is formed, a portion of the trench isolation region 17 is also simultaneously removed to expose the P + region 21 formed in the P well 13.
이어서, 도면에 도시하지는 않았지만, 상기 제1콘택홀(33a)과 제2콘택홀(33b)내에 도전층(미도시)을 형성하고, 이를 선택적으로 패터닝하여 Vss배선(미도시)과 Vcc배선(미도시)을 형성한다.Subsequently, although not shown in the drawing, a conductive layer (not shown) is formed in the first contact hole 33a and the second contact hole 33b, and selectively patterned to form a Vss wiring (not shown) and a Vcc wiring ( Not shown).
한편, 본 발명에 따른 다른 실시예로서, Vss콘택과 P웰 픽업을 동시에 형성하는 경우외에 Vcc콘택과 N웰 픽업을 동시에 형성하여 N웰 저항을 감소시킬 수도 있따.On the other hand, in another embodiment according to the present invention, in addition to forming the Vss contact and the P well pickup at the same time, the Vcc contact and the N well pickup may be formed at the same time to reduce the N well resistance.
상기에서 설명한 바와같이, 본 발명에 따른 에스램소자의 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the method of manufacturing the SRAM device according to the present invention has the following effects.
본 발명에 따른 에스램소자의 제조방법에 있어서는, 상기 Vss배선이 금속으로 연결되어 있기 때문에 P웰도 같은 포텐셜로 묶여 셀 어레이내에서 위치와 관계없이 균일하고 낮은 웰 저향을 유지할 수가 있다.In the method of manufacturing the SRAM device according to the present invention, since the Vss wiring is connected to the metal, P wells are also tied in the same potential to maintain uniform and low well traverse regardless of the position in the cell array.
또한, N웰과 Vcc배선도 같은 포텐셜을 가지므로 Vss 콘택과 마찬가지로 좁은콘택면적으로도 활성영역과 소자분리영역에 걸치게 콘택을 형성할 수 있으므로 Vcc 콘택과 N웰 픽업을 동시에 형성하여 N웰 저항을 감소시킬 수도 있다.In addition, since N well and Vcc wiring have the same potential, as in the Vss contact, a narrow contact area can form a contact over an active region and an isolation region, so that a Vcc contact and an N well pickup are simultaneously formed to form an N well resistance. It can also be reduced.
따라서, 셀 Vss배선 콘택 형성시에 P웰 픽업을 동시에 형성할 수 있어, 셀크기의 증가없이도 P웰픽업을 셀블럭내부에 형성하여 P웰 저향을 감소시킬 수 있으며, 균일성을 증가시키며 여분의 웰 픽업이 불필요하게 되므로써 칩 크기를 효과적으로 감소시킬 수 있다.Therefore, P well pick-up can be simultaneously formed at the time of cell Vss wiring contact, and P well pick-up can be formed inside the cell block without increasing cell size, thereby reducing P well deflection, increasing uniformity, and providing extra By eliminating the well pickup, chip size can be effectively reduced.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
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| KR100825815B1 (en) * | 2007-06-07 | 2008-04-28 | 삼성전자주식회사 | Semiconductor device including active pattern with channel recess, and method of fabricating the same |
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| KR100230426B1 (en) * | 1996-06-29 | 1999-11-15 | 윤종용 | Static random access memory device with improved integrated ratio |
| KR19990055799A (en) * | 1997-12-27 | 1999-07-15 | 김영환 | Contact formation method of semiconductor device |
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