KR20020086098A - a contact structure for interconnecting multi-level wires and a method for forming the same - Google Patents
a contact structure for interconnecting multi-level wires and a method for forming the same Download PDFInfo
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- KR20020086098A KR20020086098A KR1020010025813A KR20010025813A KR20020086098A KR 20020086098 A KR20020086098 A KR 20020086098A KR 1020010025813 A KR1020010025813 A KR 1020010025813A KR 20010025813 A KR20010025813 A KR 20010025813A KR 20020086098 A KR20020086098 A KR 20020086098A
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 229910052751 metal Inorganic materials 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 11
- 239000011229 interlayer Substances 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910000838 Al alloy Inorganic materials 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000007517 polishing process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 49
- 239000000126 substance Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000779 smoke Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 다층 배선의 콘택(contact) 구조 및 그 형성 방법에 관한 것으로서, 보다 상세하게는 서로 다른 층에 위치하는 실리콘 기판과 배선, 또는 배선과 배선을 비아 홀(via hole)을 통하여 전기적으로 연결시켜 주기 위한 콘택 구조 및 그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact structure of a multilayer wiring and a method for forming the same. More particularly, a silicon substrate and wiring located on different layers, or an electrical connection between the wiring and the wiring through via holes. A contact structure and a method of forming the same are provided.
최근, 반도체 집적회로가 고집적화 됨에 따라 제한된 면적 내에서 배선과 배선을 효과적으로 연결하는 방법들이 제시되고 있다. 그 중, 집적 회로에서의 배선을 다층화하는 다층 배선 방법이 주로 사용되고 있는데, 반도체 소자간에 배선이 통과되는 공간을 고려할 필요가 없기 때문에 반도체 소자의 크기를 작게 가져갈 수 있다. 이러한 다층 배선 구조에서는 각 층 간에 존재하는 콘택 또는 비아의 수가 매우 많으며, 이들은 서로 도통하므로, 아주 낮은 콘택 저항값을 가지는 것이 요구된다.Recently, as semiconductor integrated circuits are highly integrated, methods for effectively connecting wirings and wirings within a limited area have been proposed. Among them, a multilayer wiring method for multilayering wiring in an integrated circuit is mainly used. Since it is not necessary to consider a space through which wiring passes between semiconductor elements, the size of the semiconductor element can be reduced. In such a multi-layered wiring structure, the number of contacts or vias existing between the layers is very large, and since they are conductive with each other, it is required to have a very low contact resistance value.
그러면, 도 1a 내지 도 1d를 참고로 하여 종래의 기술에 따른 콘택 형성 방법에 대하여 설명한다. 여기서는 편의상, 배선 간의 연결부인 비아(via)를 콘택의 범위에 포함시켜 콘택으로 지칭하여 설명하겠다.Next, a contact forming method according to the related art will be described with reference to FIGS. 1A to 1D. For convenience, a via, which is a connection portion between wirings, is included in a range of a contact and will be referred to as a contact.
먼저, 도 1a에서 보는 바와 같이, 규소 기판(10) 위에 제1 배선층(20)을 형성하고, 그 위에 TEOS(thetraethyle orthosilicate)막 및/또는 BPSG막 등으로 층간 절연막(30)을 형성한 다음, 층간 절연막(30)을 패터닝하여 제1 배선층(20)의 일정 영역이 드러나도록 콘택 홀(contact hole)을 형성한다.First, as shown in FIG. 1A, a first wiring layer 20 is formed on a silicon substrate 10, and an interlayer insulating layer 30 is formed thereon with a tetraethyle orthosilicate (TEOS) film and / or a BPSG film. The interlayer insulating layer 30 is patterned to form contact holes so that a predetermined region of the first wiring layer 20 is exposed.
이후, 도 1b에 도시한 바와 같이, 콘택 홀 내부의 접촉 저항을 최소화하기 위하여 티타늄(Ti)/질화티타늄(TiN)을 증착하여 베리어(barrier) 금속층(40)을 형성하고, 알루미늄 또는 알루미늄 합금보다 스텝 커버리지(step coverage)가 우수한 플러그(plug)용 금속막인 텅스텐막(50)을 연속적으로 형성하여 한다.Then, as shown in Figure 1b, in order to minimize the contact resistance inside the contact hole by depositing a titanium (Ti) / titanium nitride (TiN) to form a barrier (layer) metal layer 40, than aluminum or aluminum alloy The tungsten film 50, which is a plug metal film having excellent step coverage, is formed continuously.
다음, 도 1c에 도시한 바와 같이, 콘택 홀 내에만 텅스텐을 남기기 위해 베리어 금속층(40)이 드러날 때까지 기계 화학적 연마(chemical mechanical polishing)를 실시하여 플러그(51)를 형성한다.Next, as shown in FIG. 1C, the plug 51 is formed by performing chemical mechanical polishing until the barrier metal layer 40 is exposed so as to leave tungsten only in the contact hole.
이어, 도 1d에 도시한 바와 같이, 기판(10)의 상부에 저저항을 가지는 알루미늄막(60)을 적층하고 패터닝하여 제1 배선층(20)과 연결되는 제2 배선층(60)을 형성한다.Subsequently, as illustrated in FIG. 1D, the second wiring layer 60 connected to the first wiring layer 20 is formed by stacking and patterning an aluminum film 60 having a low resistance on the substrate 10.
그러나, 이러한 종래의 콘택 구조 및 그 제조 방법에서는 앞에서 설명한 바와 같이 콘택 홀의 저항을 줄이기 위해 베리어 금속층(40)을 형성해야 하며, 알루미늄 또는 알류미늄 합금은 콘택 홀을 완전히 채울 수 없어 콘택 홀의 저항을 해결하기 위해 텅스텐막(50)을 적층하고, 고비용의 기계 화학적 연마를 실시해야 하므로 제조 공정이 복잡하고 생산 비용이 증가하게 된다. 또한, 이와 같이 진행하더라도 콘택 홀에 이물질이 잔류하거나 기계 화학적 연마에 의해 콘택 홀이 균일하게 드러나지 않을 경우에는 콘택 홀의 콘택 저항을 균일하게 관리하기 어려운 문제점이 있다.However, in the conventional contact structure and manufacturing method thereof, as described above, the barrier metal layer 40 must be formed to reduce the resistance of the contact hole, and aluminum or aluminum alloy cannot completely fill the contact hole, thereby solving the resistance of the contact hole. In order to stack the tungsten film 50 and perform expensive mechanical chemical polishing, the manufacturing process is complicated and the production cost increases. In addition, even in this case, when foreign matter remains in the contact hole or when the contact hole is not uniformly exposed by mechanical chemical polishing, it is difficult to uniformly manage the contact resistance of the contact hole.
본 발명은 이러한 문제점을 해결하기 위한 것으로서, 콘택 홀의 콘택 저항을 최소화하는 동시에 콘택 저항을 균일하고 안정적으로 관리할 수 있는 콘택 구조 및 그 제조 방법을 제공하는 것이다.The present invention has been made to solve the above problems, and to provide a contact structure and a method of manufacturing the same that can minimize and minimize the contact resistance of the contact hole and manage the contact resistance uniformly and stably.
본 발명의 다른 과제는 제조 공정을 단순화하고 제조 비용을 절감할 수 있는 콘택 구조 및 그 제조 방법을 제공하는 것이다.Another object of the present invention is to provide a contact structure and a method of manufacturing the same, which can simplify the manufacturing process and reduce the manufacturing cost.
도 1a 및 도 1d는 종래의 기술에 따른 다층 배선의 콘택 형성 방법을 공정 순서에 따라 도시한 단면도이고,1A and 1D are cross-sectional views illustrating a method for forming a contact of a multilayer wiring according to a prior art according to a process sequence;
도 2는 본 발명의 실시예에 따른 다층 배선의 콘택 구조를 도시한 단면도이고,2 is a cross-sectional view showing a contact structure of a multilayer wiring according to an embodiment of the present invention;
도 3a 내지 도 3d는 본 발명의 실시예에 따른 다층 배선의 콘택 형성 방법을 도시한 단면도이다.3A to 3D are cross-sectional views illustrating a method for forming a contact for a multilayer wiring according to an exemplary embodiment of the present invention.
이러한 과제를 해결하기 위해서, 본 발명에 따른 다층 배선의 콘택 형성 방법에서는 배선부와 볼록한 요철의 콘택부를 가지는 제1 배선층을 형성한다. 이어, 제1 배선층을 덮는 절연막을 적층하고 콘택부가 드러날 때까지 절연막을 연마한다.이어, 제1 배선층과 전기적으로 연결되는 제2 배선층을 형성한다.In order to solve this problem, in the contact formation method of the multilayer wiring which concerns on this invention, the 1st wiring layer which has a wiring part and the convex uneven contact part is formed. Next, an insulating film covering the first wiring layer is laminated and the insulating film is polished until the contact portion is exposed. A second wiring layer electrically connected to the first wiring layer is then formed.
여기서, 제1 배선층을 형성하기 위해서, 우선 도전층을 형성하고, 배선부용 감광막 패턴을 마스크로 도전층을 식각하여 배선부를 형성한다. 이어, 콘택부용 감광막 패턴을 마스크로 도전층의 일부 두께만 식각하여 콘택부를 형성한다.In order to form the first wiring layer, the conductive layer is first formed, and then the conductive layer is etched using the photosensitive film pattern for the wiring portion as a mask to form the wiring portion. Subsequently, only a partial thickness of the conductive layer is etched using the photoresist pattern for the contact portion as a mask to form the contact portion.
이때, 배선부용 감광막 패턴과 콘택부용 감광막 패턴은 음성의 감광성 물질로 형성하는 것이 바람직하다.At this time, the photosensitive film pattern for the wiring portion and the photosensitive film pattern for the contact portion are preferably formed of a negative photosensitive material.
이러한 형성 방법을 통하여 콘택 구조에서는, 배선부와 배선부 위에 볼록한 요철의 콘택부를 가지는 제1 배선층이 형성되어 있으며, 배선부를 덮고 있으며 콘택부를 드러내는 층간의 절연막 상부에는 제2 배선층이 형성되어 있다. 여기서, 제1 배선층과 상기 제2 배선층은 직접 접하고 있다.Through this formation method, in the contact structure, a first wiring layer having convex and concave contact portions is formed on the wiring portion and the wiring portion, and a second wiring layer is formed on the insulating film between the layers covering the wiring portion and exposing the contact portion. Here, the first wiring layer and the second wiring layer are in direct contact with each other.
그러면, 첨부한 도면을 참고로 하여 본 발명의 실시예에 따른 다층 배선의 콘택 구조 및 그 형성 방법을 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세하게 설명한다.Then, the contact structure and the method of forming the multilayer wiring according to an embodiment of the present invention with reference to the accompanying drawings will be described in detail to be easily carried out by those skilled in the art.
우선, 도 2를 참조하여 본 발명의 실시예에 따른 다층 배선의 콘택 구조에 대하여 구체적으로 설명하기로 한다.First, a contact structure of a multilayer wiring according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 2.
도 2는 본 발명의 실시예에 따른 다층 배선의 콘택 구조를 도시한 단면도이다.2 is a cross-sectional view illustrating a contact structure of a multilayer wiring according to an embodiment of the present invention.
도 2에서 보는 바와 같이, 기판(11)의 상부에 알루미늄 또는 알루미늄 합금 등과 같이 저저항을 가지는 도전 물질로 이루어진 제1 배선층(21)이 형성되어 있다. 이때, 제1 배선층(21)은 하부의 배선부(211)와 배선부(211)보다 좁은 폭을 가지며 볼록한 요철을 가지는 모양으로 형성되어 있는 콘택부(212)로 이루어져 있다. 또한, 기판(11)의 상부에는 제1 배선층(21)을 덮으며 콘택부(212)를 드러내는 콘택 홀(311)을 가지는 층간 절연막(31)이 형성되어 있으며, 층간 절연막(31)의 상부에서 콘택 홀(311)에서 제1 배선층(21)과 직접 접촉하여 제1 배선층(21)과 전기적으로 연결되어 있는 제2 배선층(61)이 형성되어 있다.As shown in FIG. 2, a first wiring layer 21 made of a conductive material having a low resistance, such as aluminum or an aluminum alloy, is formed on the substrate 11. At this time, the first wiring layer 21 is formed of a contact portion 212 formed in a shape having a narrower width than the wiring portion 211 and the wiring portion 211 and convex irregularities. In addition, an interlayer insulating film 31 having a contact hole 311 covering the first wiring layer 21 and exposing the contact portion 212 is formed on the substrate 11. In the contact hole 311, a second wiring layer 61 is formed in direct contact with the first wiring layer 21 and electrically connected to the first wiring layer 21.
그러면, 이러한 본 발명의 실시예에 다층 배선의 콘택 구조의 제조 방법을 도 2 및 도 3a 내지 도 3d를 참조하여 구체적으로 설명하기로 한다.Next, a method of manufacturing a contact structure of a multilayer wiring in this embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3A to 3D.
도 3a 내지 도 3d는 본 발명의 실시예에 따른 다층 배선의 콘택 형성 방법을 그 공정 순서에 따라 도시한 단면도이다.3A to 3D are cross-sectional views illustrating a method for forming a contact for a multilayer wiring according to an exemplary embodiment of the present invention according to a process sequence thereof.
먼저, 도 3a에서 보는 바와 같이, 규소 기판(11)의 상부에 저저항을 가지는 알루미늄 또는 알루미늄 합금의 도전층을 충분한 두께로 적층하고, 그 상부에 제1 배선용 마스크를 이용한 사진 공정으로 배선부용 감광막 패턴(100)을 형성하고, 배선부용 감광막 패턴(100)으로 도전층을 패터닝하여 제1 배선층(21)을 형성한다.First, as shown in FIG. 3A, a conductive layer of aluminum or an aluminum alloy having a low resistance is laminated on the silicon substrate 11 to a sufficient thickness, and the photosensitive film for the wiring portion is formed by a photolithography process using the first wiring mask thereon. The pattern 100 is formed and the first wiring layer 21 is formed by patterning the conductive layer with the photosensitive film pattern 100 for the wiring portion.
이어, 도 3b에서 보는 바와 같이, 배선부용 감광막 패턴(100)을 제거하고, 기판(11)의 상부에 감광막을 도포하고 콘택부용 마스크를 이용한 사진 공정으로 감광막을 노광하여 콘택부용 감광막 패턴(200)을 형성한다. 여기서, 배선부용 감광막 패턴(100)을 음성의 감광성 물질로 형성하는 경우에는 배선부용 감광막 패턴(100)을 콘택부용 마스크로 노광하고 현상하여 콘택부용 감광막 패턴(200)을 형성할 수 있다.Subsequently, as shown in FIG. 3B, the photoresist pattern 100 for the wiring part is removed, the photoresist film is applied on the upper portion of the substrate 11, and the photoresist film is exposed by a photo process using a mask for the contact part to expose the photoresist pattern 200 for the contact part. To form. Here, when the photosensitive film pattern 100 for the wiring part is formed of a negative photosensitive material, the photosensitive film pattern 100 for the wiring part may be exposed and developed using a mask for the contact part to form the photosensitive film pattern 200 for the contact part.
이어, 도 3c에서 보는 바와 같이, 감광막 패턴(100)을 식각 마스크로 하여제1 배선층(21)의 일부 두께를 식각하여 제1 배선층(21)이 상부에 볼록한 요철을 가지도록 하여 배선부(211)보다 좁은 폭을 가지며 배선부(211)와 일체인 콘택부(212)를 형성한다. 이렇게 하면, 콘택 홀을 형성하는 공정을 생략하고 배선부(211)와 같이 저저항의 도전 물질로 콘택부(212)를 형성할 수 있다. 또한, 하나의 배선용 도전층으로 배선부(211)와 콘택부(212)를 동시에 형성할 수 있어, 종래의 기술에서와 같이 베리어 금속층을 형성하거나 콘택 홀을 채워 플러그를 형성하는 공정 및 고비용의 기계 화학적 연마 공정을 생략할 수 있다.Subsequently, as shown in FIG. 3C, a portion of the first wiring layer 21 is etched using the photosensitive film pattern 100 as an etching mask so that the first wiring layer 21 has convex and convexities on the upper portion. The contact portion 212 having a narrower width than and integrally formed with the wiring portion 211 is formed. In this case, the step of forming the contact hole may be omitted, and the contact part 212 may be formed of a conductive material having a low resistance, such as the wiring part 211. In addition, since the wiring portion 211 and the contact portion 212 can be formed simultaneously with one wiring conductive layer, a process of forming a barrier metal layer or filling a contact hole to form a plug as in the related art, and a high-cost machine The chemical polishing process can be omitted.
이어, 도 3d에서 보는 바와 같이, 기판(11)의 상부에 화학 기상 증착 방법을 통하여 질화 규소 또는 산화 규소 또는 TEOS막 또는 BPSG막 등을 적층하여 층간 절연막(31)을 형성한다. 이어, 제1 배선층(21)의 콘택부(211)가 드러날 때까지 연마 공정으로 평탄화를 실시하여 층간 절연막(31) 일부를 제거한다.Subsequently, as shown in FIG. 3D, an interlayer insulating film 31 is formed by stacking silicon nitride, silicon oxide, TEOS film, BPSG film, or the like on the substrate 11 through a chemical vapor deposition method. Subsequently, a part of the interlayer insulating layer 31 is removed by planarization by a polishing process until the contact portion 211 of the first wiring layer 21 is exposed.
이어, 도 2에서 보는 바와 같이, 층간 절연막(31)의 상부에 알루미늄 또는 알루미늄 합금을 다시 적층하고 제2 배선용 마스크를 이용한 사진 식각 공정으로 패터닝하여 제2 배선층(61)을 형성한다.Subsequently, as shown in FIG. 2, aluminum or an aluminum alloy is further stacked on the interlayer insulating layer 31 and patterned by a photolithography process using a second wiring mask to form a second wiring layer 61.
본 발명의 실시예에서는 도 2에서 보는 바와 같이 제1 배선층(21)을 기판(11) 상부 형성하는 제조 방법 및 그에 따른 구조로 한정하여 설명하였지만, 제1 배선층(21)의 하부에는 콘택부를 통하여 제1 배선층(21)과 전기적으로 연결되어 있는 다른 배선층이 기판(11)을 대신하여 형성될 수 있다.In the exemplary embodiment of the present invention, as shown in FIG. 2, the first wiring layer 21 is limited to a manufacturing method and a structure according to the upper portion of the substrate 11, but the lower portion of the first wiring layer 21 is disposed through a contact portion. Another wiring layer electrically connected to the first wiring layer 21 may be formed in place of the substrate 11.
이상에서와 같이, 본 발명에서는 저저항의 도전 물질로 배선층을 형성하면서그 일부를 콘택부를 형성하고 콘택 홀을 형성하는 공정을 생략하여 콘택 홀의 콘택 저항을 최소화하는 동시에 콘택 저항을 균일하고 안정적으로 관리할 수 있으며, 베이어 금속층 및 연막 공정을 생략할 수 있어 제조 공정을 단순화하고 제조 비용을 절감할 수 있다.As described above, in the present invention, a step of forming a contact layer and forming a contact hole while forming a wiring layer using a conductive material having a low resistance is omitted to minimize the contact resistance of the contact hole and to manage the contact resistance uniformly and stably. In addition, the Bayer metal layer and the smoke screen process can be omitted, thereby simplifying the manufacturing process and reducing the manufacturing cost.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020010025813A KR20020086098A (en) | 2001-05-11 | 2001-05-11 | a contact structure for interconnecting multi-level wires and a method for forming the same |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020010025813A KR20020086098A (en) | 2001-05-11 | 2001-05-11 | a contact structure for interconnecting multi-level wires and a method for forming the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101150605B1 (en) * | 2010-04-07 | 2012-06-12 | 에스케이하이닉스 주식회사 | Semiconductor device and method for manufacturing the same |
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| KR19990060819A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Metal wiring formation method of semiconductor device |
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| JPH04303943A (en) * | 1991-03-30 | 1992-10-27 | Nec Corp | Manufacture of semiconductor device |
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| JPH08306787A (en) * | 1995-03-06 | 1996-11-22 | Sanyo Electric Co Ltd | Semiconductor device and its fabrication |
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| KR101150605B1 (en) * | 2010-04-07 | 2012-06-12 | 에스케이하이닉스 주식회사 | Semiconductor device and method for manufacturing the same |
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