KR20020048646A - Method for cleaning in semiconductor device - Google Patents

Method for cleaning in semiconductor device Download PDF

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Publication number
KR20020048646A
KR20020048646A KR1020000077858A KR20000077858A KR20020048646A KR 20020048646 A KR20020048646 A KR 20020048646A KR 1020000077858 A KR1020000077858 A KR 1020000077858A KR 20000077858 A KR20000077858 A KR 20000077858A KR 20020048646 A KR20020048646 A KR 20020048646A
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KR
South Korea
Prior art keywords
cleaning
semiconductor device
polysilicon
chemical mechanical
mechanical polishing
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KR1020000077858A
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Korean (ko)
Inventor
안기철
Original Assignee
박종섭
주식회사 하이닉스반도체
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Priority to KR1020000077858A priority Critical patent/KR20020048646A/en
Publication of KR20020048646A publication Critical patent/KR20020048646A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H01L21/67046—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly scrubbing means, e.g. brushes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

PURPOSE: A cleaning method of semiconductor devices is provided to effectively remove metal impurities contained in slurry without using a wet chemical, such as HF. CONSTITUTION: After forming a polysilicon layer on a semiconductor substrate, the polysilicon layer is polished by a CMP(Chemical Mechanical Polishing)(31). The polishing residues are removed by a cleaning equipment mounted a blush using NH4OH(32). Metal impurities remaining on the surface of the semiconductor substrate are removed by a wet bath using HF or BOE(33).

Description

반도체소자의 세정 방법{METHOD FOR CLEANING IN SEMICONDUCTOR DEVICE}METHODS FOR CLEANING IN SEMICONDUCTOR DEVICE

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 화학적기계적연마 (Chemical Mechanical Polishing; CMP)후 슬러리(Slurry)내 함유된 금속불순물 (Metal impurity)을 제거하기 위한 반도체소자의 세정 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for cleaning a semiconductor device for removing metal impurity contained in a slurry after chemical mechanical polishing (CMP).

일반적으로 화학적기계적연마(Chemical Mechanical Polishing; CMP) 공정은 웨이퍼를 연마하기 위한 연마제인 슬러리(Slurry) 용액 내의 화학적 성분 및 웨이퍼를 연마하는 패드와 연마제의 물리적 성분에 의하여 웨이퍼의 표면을 화학적기계적으로 연마하여 평탄화를 실시하는 방법으로서, 리플로우(Reflow) 공정이나 에치백(Etch back) 공정으로 달성할 수 없는 넓은 공간 영역의 평탄화 및 저온 평탄화를 달성할 수 있다는 장점 때문에 차세대 반도체 소자에서 유력한 평탄화 기술로 대두되고 있다.In general, the chemical mechanical polishing (CMP) process chemically polishes the surface of the wafer by chemical components in a slurry solution, which is an abrasive for polishing the wafer, and pads and polishing agents. Planarization is a method of planarization, which is advantageous in next-generation semiconductor devices because of the advantage of achieving planarization and low temperature planarization of a large space area which cannot be achieved by a reflow process or an etch back process. It is emerging.

그러나, 슬러리 용액에는 H2O2, KIO3, pH 조절을 위한 각종 산 또는 염기 등이 포함되어 있으며, 연마제의 주성분은 Al2O3, 실리카(Silica) 등이기 때문에 연마 과정에서 금속이온, 연마제 입자 등의 오염 물질이 흡착될 뿐 아니라 심각하게 손상을 입는 층이 발생되기도 한다. 이와 같이 중금속 오염 입자를 포함하는 오염 물질층과 손상 막질을 제거하기 위해서 화학적기계적연마(CMP) 공정 후 세정 공정을 필히 진행하고 있다.However, the slurry solution contains H 2 O 2 , KIO 3 , various acids or bases for pH adjustment, and the main components of the abrasive are Al 2 O 3 , silica, etc. Not only are contaminants, such as particles, adsorbed, but also seriously damaged layers are generated. Thus, in order to remove the contaminant layer containing the heavy metal contaminant particles and the damaged film quality, the cleaning process is required after the chemical mechanical polishing (CMP) process.

이는 웨이퍼 표면에 오염물질 오염입자가 존재할 경우, 후속 공정시 패턴불량 또는 브릿지(Bridge) 등을 유발시켜 반도체 소자의 수율을 저하시키기 때문이다.This is because when contaminant contaminants are present on the wafer surface, pattern defects or bridges are caused in subsequent processes, thereby lowering the yield of semiconductor devices.

최근에는 반도체소자의 제조 공정 중 화학적기계적연마(CMP)후 슬러리내 함유된 금속불순물을 제거하기 위해 연마장치와 일체화된 세정장치에서 HF와 같은 습식케미컬(Wet chemical)을 이용하여 웨이퍼 표면의 금속불순물을 제거하며, 산화막을 화학적기계적연마하는 경우 이러한 방법을 이용하고 있다.Recently, metal impurities on the surface of the wafer using wet chemicals such as HF in a cleaning device integrated with a polishing apparatus to remove metal impurities contained in the slurry after chemical mechanical polishing (CMP) during the semiconductor device manufacturing process. This method is used for chemical mechanical polishing of the oxide film.

특히, 폴리실리콘 플러그를 형성하는 공정에서, 폴리실리콘을 화학적기계적연마한 후, 연마장치와 일체화된 브러시가 장착된 세정 장치에서 HF와 같은 습식 케미컬을 이용하여 금속불순물을 세정할 경우, 웨이퍼의 전면에 다수의 결함(Defect)이 잔류하며(도 1a 참조), 이러한 결함들은 경우에 따라서 눌린 듯한 형상(A)을 갖고 웨이퍼 표면에 존재함을 알 수 있다(도 1b 참조).Particularly, in the process of forming the polysilicon plug, after cleaning the polysilicon by chemical mechanical polishing and cleaning the metallic impurities using a wet chemical such as HF in the cleaning apparatus equipped with a brush integrated with the polishing apparatus, the front surface of the wafer It can be seen that a number of defects remain at (see FIG. 1A), and these defects are present on the wafer surface with a pressed shape A in some cases (see FIG. 1B).

상술한 것처럼, 종래기술에서는 후세정 공정에서 금속불순물을 제거하기 위해 HF를 사용하는데, 폴리실리콘의 표면이 소수성화되어 웨이퍼 표면의 파티클이 탈착되기 보다는 오히려 브러시에 묻어 있던 파티클이 흡착되는 문제점이 있다.As described above, in the prior art, HF is used to remove metal impurities in the post-cleaning process, and the surface of the polysilicon becomes hydrophobic so that particles on the surface of the wafer are adsorbed, rather than desorbed particles on the surface of the wafer. .

본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 슬러리내 금속불순물을 제거하기 위한 브러시 세정 공정시 HF를 사용함에 따른 파티클 흡착을 방지하는데 적합한 반도체소자의 세정 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, the object of the present invention is to provide a method for cleaning a semiconductor device suitable for preventing particle adsorption by using HF during the brush cleaning process for removing metal impurities in the slurry. have.

도 1a는 종래기술에 따라 웨이퍼 전면에 결함이 발생된 상태를 나탄낸 도면,Figure 1a is a view showing a state in which a defect occurs on the front surface of the wafer according to the prior art,

도 1b는 종래기술에 따른 눌린 형상을 갖는 결함을 도시한 도면,Figure 1b shows a defect having a pressed shape according to the prior art,

도 2a 내지 도 2b는 본 발명의 실시예에 따른 폴리실리콘 플러그의 형성 방법을 도시한 도면,2a to 2b is a view showing a method of forming a polysilicon plug according to an embodiment of the present invention,

도 3은 본 발명의 실시예에 따른 반도체소자의 세정 방법을 도시한 공정 흐름도.3 is a process flowchart illustrating a method of cleaning a semiconductor device according to an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체기판 22 : 워드라인21: semiconductor substrate 22: word line

23 : 스페이서 24 : 불순물 접합층23 spacer 24 impurity bonding layer

25 : 층간절연막 26 : 폴리실리콘 플러그25 interlayer insulating film 26 polysilicon plug

상기의 목적을 달성하기 위한 본 발명의 반도체소자의 세정 방법은 소정 공정이 완료된 반도체기판상에 폴리실리콘을 형성하는 단계, 상기 폴리실리콘을 화학적기계적연마하는 단계, 상기 화학적기계적연마후 발생된 연마부산물을 NH4OH를 이용하여 제거하는 단계, 및 상기 반도체기판의 표면에 잔류하는 금속불순물을 습식용기에서 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.The cleaning method of the semiconductor device of the present invention for achieving the above object comprises the steps of forming polysilicon on a semiconductor substrate having a predetermined process, chemical mechanical polishing of the polysilicon, polishing by-products generated after the chemical mechanical polishing Removing using NH 4 OH, and removing the metallic impurities remaining on the surface of the semiconductor substrate in a wet container.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2b는 본 발명의 실시예에 따른 폴리실리콘 플러그의 형성 방법을 도시한 도면이며, 도 3은 본 발명의 실시예에 따른 폴리실리콘의 화학적기계적연마후 세정 방법을 도시한 공정 흐름도이다.2A to 2B are views illustrating a method of forming a polysilicon plug according to an embodiment of the present invention, and FIG. 3 is a process flowchart illustrating a method of cleaning polysilicon after chemical mechanical polishing according to an embodiment of the present invention. .

도 2a에 도시된 바와 같이, 반도체기판(21)상에 다수의 워드라인(22)을 형성한 후, 워드라인(22)을 포함한 전면에 측벽용 절연막을 증착 및 식각하여 워드라인(22)의 양측벽에 접하는 스페이서(23)를 형성한다. 워드라인(22) 및 스페이서(23)을 이용한 마스크로 이용한 불순물 이온주입으로 반도체기판(21)에 불순물접합층(24)을 형성한다.As shown in FIG. 2A, after forming a plurality of word lines 22 on the semiconductor substrate 21, a sidewall insulating film is deposited and etched on the entire surface including the word lines 22 to form the word lines 22. A spacer 23 is formed in contact with both side walls. The impurity junction layer 24 is formed on the semiconductor substrate 21 by implantation of impurity ions used as a mask using the word line 22 and the spacer 23.

워드라인(22)을 포함한 반도체기판(21)상에 층간절연막(25)을 증착한 후 층간절연막(24)을 화학적기계적연마하여 평탄화한다.After the interlayer insulating film 25 is deposited on the semiconductor substrate 21 including the word line 22, the interlayer insulating film 24 is chemically mechanically polished and planarized.

도 2b에 도시된 바와 같이, 평탄화된 층간절연막(25)을 선택적으로 식각하여 불순물접합층(23)이 노출되는 플러그용 콘택홀을 형성한 후, 콘택홀을 포함한 전면에 폴리실리콘을 증착한다. 폴리실리콘을 화학적기계적연마하여 콘택홀에 매립되며불순물접합층(23)에 접하는 폴리실리콘 플러그(26)를 형성한다.As shown in FIG. 2B, the planarized interlayer insulating film 25 is selectively etched to form a plug contact hole through which the impurity bonding layer 23 is exposed, and then polysilicon is deposited on the entire surface including the contact hole. The polysilicon is chemically polished to form a polysilicon plug 26 embedded in the contact hole and in contact with the impurity bonding layer 23.

도 3에 도시된 바와 같이, 폴리실리콘을 화학적기계적연마하여 폴리실리콘 플러그(26)를 형성한 후(31), 브러시가 장착된 세정장치에서 연마후 발생된 부산물을 NH4OH를 이용하여 제거하고(32), 후속 습식용기(Wet bath)에서 BOE 또는 HF를 이용하여 웨이퍼 표면에 잔존하는 금속불순물을 제거한다(33).As shown in FIG. 3, after the polysilicon has been chemically mechanically polished to form the polysilicon plug 26 (31), the by-products generated after polishing in the cleaning apparatus equipped with a brush are removed using NH 4 OH. (32), metal impurities remaining on the wafer surface are removed using BOE or HF in a subsequent wet bath (33).

금속불순물을 제거할 때 웨이퍼 표면의 산화막은 100Å∼150Å 두께로 제거된다.When the metal impurities are removed, the oxide film on the wafer surface is removed to a thickness of 100 kPa to 150 kPa.

본 발명의 실시예에서는 폴리실리콘을 화학적기계적연마하는 경우에 대해 설명하였지만, 폴리실리콘이 포함된 도전막, 금속막을 화학적기계적연마 공정을 이용한 반도체소자의 제조 공정에 적용할 수 있다.In the exemplary embodiment of the present invention, a case of chemical mechanical polishing of polysilicon has been described, but a conductive film and a metal film containing polysilicon may be applied to a manufacturing process of a semiconductor device using a chemical mechanical polishing process.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같은 본 발명의 반도체소자의 세정 방법은 화학적기계적연마 공정을 이용하여 폴리실리콘 플러그를 형성할 때 브러시를 이용한 후세정 공정시 HF를 사용하지 않고 후속 습식용기에서 금속불순물을 제거하므로써, 브러시 세정시 파티클 흡착을 억제하여 수율을 향상시킬 수 있는 효과가 있다.The cleaning method of the semiconductor device of the present invention as described above is a brush by removing the metallic impurities from the subsequent wet container without using HF during the post-cleaning process using a brush when forming a polysilicon plug using a chemical mechanical polishing process There is an effect that can improve the yield by suppressing particle adsorption at the time of cleaning.

Claims (4)

반도체소자의 세정 방법에 있어서,In the cleaning method of a semiconductor element, 소정 공정이 완료된 반도체기판상에 폴리실리콘을 형성하는 단계;Forming polysilicon on the semiconductor substrate where a predetermined process is completed; 상기 폴리실리콘을 화학적기계적연마하는 단계;Chemical mechanical polishing the polysilicon; 상기 화학적기계적연마후 발생된 연마부산물을 NH4OH를 이용하여 제거하는 단계; 및Removing the byproducts generated after the chemical mechanical polishing using NH 4 OH; And 상기 반도체기판의 표면에 잔류하는 금속불순물을 습식용기에서 제거하는 단계Removing metal impurities remaining on the surface of the semiconductor substrate in a wet container; 를 포함하여 이루어짐을 특징으로 하는 반도체소자의 세정 방법.Method for cleaning a semiconductor device, characterized in that comprises a. 제 1 항에 있어서,The method of claim 1, 상기 연마부산물을 제거하는 단계는,Removing the abrasive by-products, 브러시가 장착된 세정장치에서 이루어지는 것을 특징으로 하는 반도체소자의 세정 방법.A cleaning method for a semiconductor device, comprising a cleaning device equipped with a brush. 제 1 항에 있어서,The method of claim 1, 상기 금속불순물을 제거하는 단계는,Removing the metal impurities, 상기 습식용기에서 HF 또는 BOE 중 어느 하나를 이용하여 이루어지는 것을 특징으로 하는 반도체소자의 세정 방법.The cleaning method of a semiconductor device, characterized in that using one of HF or BOE in the wet container. 제 1 항에 있어서,The method of claim 1, 상기 금속불순물 제거시, 100Å∼150Å 두께의 산화막이 제거되는 것을 특징으로 하는 반도체소자의 세정 방법.When the metal impurities are removed, an oxide film having a thickness of 100 kV to 150 kV is removed.
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