KR20070001487A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20070001487A
KR20070001487A KR1020050057005A KR20050057005A KR20070001487A KR 20070001487 A KR20070001487 A KR 20070001487A KR 1020050057005 A KR1020050057005 A KR 1020050057005A KR 20050057005 A KR20050057005 A KR 20050057005A KR 20070001487 A KR20070001487 A KR 20070001487A
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South Korea
Prior art keywords
semiconductor device
tungsten
interlayer insulating
deposition
manufacturing
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KR1020050057005A
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Korean (ko)
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신종한
김찬배
유철휘
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주식회사 하이닉스반도체
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Priority to KR1020050057005A priority Critical patent/KR20070001487A/en
Publication of KR20070001487A publication Critical patent/KR20070001487A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

A method for manufacturing a semiconductor device is provided to improve interface characteristics between a landing plug contact and a storage node contact by employing a selective chemical vapor deposition for gap-filling a tungsten in a storage node contact hole. A landing plug(52) is formed on a semiconductor substrate(51). A first interlayer dielectric(53) is formed on the semiconductor substrate where the landing plug is formed. A bit line pattern(54) is formed on the first interlayer dielectric. A second interlayer dielectric(55) is formed on the semiconductor substrate where the second interlayer dielectric. A hard mask layer is formed on the second interlayer dielectric. The hard mask and the second interlayer dielectric are etched to form a storage node contact hole(57) where the landing plug is exposed. Tungsten gap-fills the storage node contact hole by a selective chemical vapor deposition. A chemical mechanical polishing is performed on a surface of the semiconductor substrate to expose the second interlayer dielectric.

Description

반도체 소자의 제조방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자 제조 방법을 설명하기 위한 공정 단면도.1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2c는 본 발명의 바람직한 실시예에 따른 반도체 소자 제조 방법을 설명하기 위한 공정 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

51 : 반도체 기판 52 : 랜딩플러그(LPC)51 semiconductor substrate 52 landing plug (LPC)

53 : 제1 층간절연막 54 : 비트라인패턴53: first interlayer insulating film 54: bit line pattern

55 : 제2 층간절연막 56 : 하드마스크55: second interlayer insulating film 56: hard mask

57 : 스토리지노트콘택홀 58 : 스토리지노드콘택스페이서57: storage note contact hole 58: storage node contact spacer

59 : 스토리지노드콘택플러그 59: storage node contact plug

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 스토리지노드콘택(Storage Node Contact : SNC)플러그(Plug) 형성에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to forming a storage node contact (SNC) plug.

반도체 소자의 고집적화에 따른 콘택저항을 줄이기 위해 SNC플러그로서 텅스텐을 이용하고 있다.Tungsten is used as an SNC plug to reduce contact resistance due to high integration of semiconductor devices.

도 1a 내지 도 1c는 종래기술에 따른 SNC플러그 형성에 관한 공정 단면도 이다. 이하, 좌측의 공정 단면도는 비트라인에 수직방향을 도시한 것이고, 우측의 공정 단면도는 게이트에 수직방향을 도시한 것이다.1A to 1C are cross-sectional views illustrating a SNC plug forming according to the prior art. Hereinafter, the process cross section on the left shows the vertical direction to the bit line, and the process cross section on the right shows the vertical direction to the gate.

도 1a에 도시된 바와 같이, 반도체 기판(21)상에 랜딩플러그콘택(Landing Plug Contact:LPC)(22)을 형성하고, 그 위에 제1 층간절연막(23)를 형성한다. 상기 제1 층간절연막(23)상에 비트라인(24)을 형성하고, 그 위에 제2 층간절연막(25)을 증착한다. 상기 제2 층간절연막(25)을 평탄화 한 후, 하드마스크폴리실리콘(26)을 증착한다.As shown in FIG. 1A, a landing plug contact (LPC) 22 is formed on a semiconductor substrate 21, and a first interlayer insulating film 23 is formed thereon. A bit line 24 is formed on the first interlayer insulating film 23, and a second interlayer insulating film 25 is deposited thereon. After the planarization of the second interlayer insulating film 25, a hard mask polysilicon 26 is deposited.

이어서, 도 1b에 도시된 바와 같이, SNC홀을 형성하기 위한 마스크 및 식각공정으로 상기 하드마스크폴리실리콘(26)과 상기 제2 층간절연막을 패터닝하여 상기 랜딩플러그콘택(22)가 노출되도록 SNC홀(27)을 형성하고, SNC홀(27) 측벽에 스페이서(Spacer)(28)를 형성하고, 상기 SNC홀(27)이 충분히 매립되도록 텅스텐을 증착한다. 이때 텅스텐은 SNC홀 내부 이외에 바트라인(24)의 상부영역까지, 즉 기판 전체구조 상에 형성된다.Subsequently, as shown in FIG. 1B, the hard mask polysilicon 26 and the second interlayer insulating layer are patterned by a mask and an etching process for forming the SNC holes so that the landing plug contacts 22 are exposed. (27) is formed, spacers (28) are formed on the sidewalls of the SNC holes (27), and tungsten is deposited to sufficiently fill the SNC holes (27). At this time, tungsten is formed in the upper region of the bar line 24 in addition to the inside of the SNC hole, that is, on the entire structure of the substrate.

도 1c에 도시된 바와 같이, 상기 텅스텐을 에치백(etchback)하고, 하드마스크폴리실리콘(26)의 제거를 위한 에치백공정을 진행한다. As shown in FIG. 1C, the tungsten is etched back, and an etch back process for removing the hard mask polysilicon 26 is performed.

상술한 바와 같이, 종래 기술은 텅스텐의 에치백공정이 수반되는데, 이때 식각 선택비에 의해 제2 층간절연막(25)의 표면이 일부 손실되어진다. 이로 인해 화학적기계연마(Chemical Mechanical Polishing:CMP) 공정을 더 수행해야 하고, CMP공정을 하지 않을 경우, 콘택 브릿지(Contact Bridge)형성이나, 콘택저항이 증가될 수 있다.As described above, the prior art involves an etch back process of tungsten, in which part of the surface of the second interlayer insulating film 25 is lost due to the etching selectivity. For this reason, the chemical mechanical polishing (CMP) process should be further performed, and if the CMP process is not performed, the contact bridge may be formed or the contact resistance may be increased.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 콘택저항을 감소시키면서, SNC플러그공정을 단순화 하는 반도체 소자 제조 방법을 제공하는데 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device that simplifies the SNC plug process while reducing contact resistance.

상기 목적을 달성하기 위한 본 발명의 반도체소자 제조 방법은 기판상에 랜딩플러그콘택을 형성하는 단계, 상기 랜딩플러그콘택이 형성된 기판 상에 제1 층간절연막을 형성하는 단계, 상기 제1 층간절연막 상에 비트라인패턴을 형성하는 단계, 상기 비트라인 패턴이 형성된 기판 상에 제2 층간절연막을 형성하는 단계, 상기 제2 층간절연막 상에 하드마스크층을 형성하는 단계, 상기 하드마스크층과 상기 제2 층간절연막을 식각하여 상기 랜딩플러그콘택이 노출된 스토리지노드콘택홀을 형성하는 단계, 상기 스토리지노드콘택홀 내부에 선택적 화학기상증착법으로 텅스텐을 매립하는 단계, 제2 층간절연막이 드러나도록 기판 표면을 부분화학적기계연 마하는 단계를 포함하는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a landing plug contact on a substrate, forming a first interlayer insulating film on the substrate on which the landing plug contact is formed, on the first interlayer insulating film Forming a bit line pattern, forming a second interlayer insulating film on the substrate on which the bit line pattern is formed, forming a hard mask layer on the second interlayer insulating film, between the hard mask layer and the second interlayer Etching the insulating layer to form a storage node contact hole in which the landing plug contact is exposed, buried tungsten by a selective chemical vapor deposition method in the storage node contact hole, and partially chemically treating the surface of the substrate to expose the second interlayer insulating layer. And mechanical grinding.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도 2a 내지 도 2c는 본 발명의 바람직한 실시예에 따른 반도체 소자 제조 방법에 대한 공정 단면도이다. 이하, 좌측의 공정 단면도는 비트라인에 수직방향을 도시한 것이고, 우측의 공정 단면도는 게이트에 수직방향을 도시한 것이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. Hereinafter, the process cross section on the left shows the vertical direction to the bit line, and the process cross section on the right shows the vertical direction to the gate.

도 2a에 도시된 바와 같이, 반도체 기판(51)상에 랜딩플러그(52)를 형성한다. 이때, 랜딩플러그(52)는 텅스텐(Tungsten:W)이나 폴리(Poly)중 어느 하나로 사용할 수 있다. 상기 랜딩플러그(52)상에 제1 층간절연막(53)을 형성하고, 그 위에 비트라인(54)를 형성한다. 이때, 비트라인은 배리어 메탈과 글루TiN(54a), 비트라인W(54b), 비트라인하드마스크질화막(54c)로 이루어 질 수 있다. As shown in FIG. 2A, a landing plug 52 is formed on the semiconductor substrate 51. In this case, the landing plug 52 may be used as either tungsten (W) or poly (Poly). A first interlayer insulating layer 53 is formed on the landing plug 52, and a bit line 54 is formed thereon. In this case, the bit line may include a barrier metal, a glue TiN 54a, a bit line W 54b, and a bit line hard mask nitride film 54c.

상기 비트라인상에 제2 층간절연막(55)을 증착하고 평탄화 한다. 이때 제2 층간절연막(55)은 고밀도플라즈마(High Density Plasma:HDP) 또는 BPSG막 중에서 어느 하나의 물질을 사용하고, 4000~7000Å의 두께로 증착할 수 있다. 상기 제2 층간절연막(55)상에 SNC 식각을 위한 하드마스크폴리실리콘막(56)을 증착하여 패터닝한다. 이때, 하드마스크폴리실리콘막(56)은 500~1500Å의 두께로 증착할 수 있다.A second interlayer insulating layer 55 is deposited and planarized on the bit line. In this case, the second interlayer insulating film 55 may be formed of any one of a high density plasma (HDP) or a BPSG film, and may be deposited to a thickness of 4000 to 7000 Å. A hard mask polysilicon layer 56 for SNC etching is deposited on the second interlayer insulating layer 55 to be patterned. At this time, the hard mask polysilicon film 56 may be deposited to a thickness of 500 ~ 1500Å.

도 2b에 도시된 바와 같이, 상기 패터닝된 하드마스크폴리실리콘막(56)을 배리어로 하여 제2 층간절연막(55)을 식각하므로써 랜딩플러그(52)가 노출되도록 SNC홀(57)을 형성하고, SNC홀(57)의 측면에 스페이서(58)을 형성한다.As shown in FIG. 2B, the SNC hole 57 is formed to expose the landing plug 52 by etching the second interlayer insulating layer 55 using the patterned hard mask polysilicon layer 56 as a barrier. The spacer 58 is formed on the side of the SNC hole 57.

상기 랜딩플러그콘택(52)이 노출되도록 형성된 SNC홀(57)에 선택적화학기상증착법(Selective Chemical Vapor Deposition)으로 텅스텐(W)을 성장시켜 SNC플러그(59)를 형성한다. 이때, 상기 텅스텐은 H2가스를 운반가스로 사용하고, SiH4가스와 WF6를 이용하여 200~350℃의 온도에서 선택적으로 증착하되, SNC홀의 80%이상을 매립하도록 한다. 특히, 상기 텅스텐 증착은 표면상태가 매우 중요하기 때문에 전세정 공정을 잘 해주어야 한다. 전세정 공정으로 H2SO4 + H2O2와 희석된 HF로 세정하여 산화막(Oxide)을 제거해주고, 상기 텅스텐의 증착을 위한 챔버(Chamber)에서 인시튜(insitu)방식으로 플라즈마처리를 하여 표면에 존재하는 자연산화막(Native Oxide) 및 손상된레이어(Damaged Layer)를 제거해준다. 상기 텅스텐 증착 후에는 500~600℃의 온도에서 열처리를 통해 잔존하는 가스를 제거할 수 있다.The SNC plug 59 is formed by growing tungsten (W) in the SNC hole 57 formed to expose the landing plug contact 52 by selective chemical vapor deposition. At this time, the tungsten is used as a carrier gas H 2 gas, and selectively deposited at a temperature of 200 ~ 350 ℃ using SiH 4 gas and WF 6 , to fill more than 80% of the SNC holes. In particular, the tungsten deposition has to be well-precleaned because the surface state is very important. In the pre-cleaning process, H 2 SO 4 + H 2 O 2 and diluted with HF to remove the oxide (Oxide), and the plasma treatment in situ (Insitu) method in the chamber (Chamber) for the deposition of the tungsten It removes the native oxide and damaged layer existing on the surface. After the tungsten deposition, the remaining gas may be removed by heat treatment at a temperature of 500 ~ 600 ℃.

도 2c에 도시된 바와 같이, 부분화학적기계연마(Touch CMP)공정을 통해, 하드마스크폴리실리콘막(56)을 제거하여 제2 층간절연막이 노출되도록 한다. 이때, 상기 연마공정은 pH를 9~12로 하고, 퓸드실리카(Fumed Silica) 또는 콜로이드실리카(colloidal Silica)계열의 그룹에서 어느 하나의 물질을 연마입자로 사용할 수 있다. 특히, 상기 연마공정은 하드마스크폴리실리콘을 완전히 제거하고 폴리와 금속의 선택비를 이용하여 SNC플러그(59)의 손실을 최소화하도록 실시한다.As illustrated in FIG. 2C, the hard mask polysilicon layer 56 is removed through a partial chemical mechanical polishing (Touch CMP) process to expose the second interlayer dielectric layer. In this case, in the polishing process, the pH is set to 9 to 12, and any one material in the group of fumed silica or colloidal silica may be used as the abrasive particles. In particular, the polishing process is performed to completely remove the hard mask polysilicon and to minimize the loss of the SNC plug 59 by using the selectivity of poly and metal.

상기 연마공정 후에는 SC-1 세정 및 NH4OH + HF세정으로 잔류물을 제거할 수 있다. 또한, 플로린 계열 또는 하이드록시라민(Hydroxylamine)계열 중 어느하나의 용매를 이용한 세정으로 상기 SNC플러그상에 존재하는 잔류물 및 산화물을 제거한 다.After the polishing process, the residue may be removed by washing with SC-1 and washing with NH 4 OH + HF. In addition, by using a solvent of any of the florin-based or hydroxylamine-based to remove the residues and oxides present on the SNC plug.

진술한 바와 같이, 본 발명은 선택적 화학기상증착법으로 텅스텐을 매립하여 SNC플러그를 형성한 것으로써, 에치백 및 화학적기계연마공정을 대신하여 부분화학적기계연마(Touch CMP)공정만을 진행함으로 기존의 SNC플러그분리공정을 단순화시키고, SNC홀을 매립하는 물질로 텅스텐을 사용하여 콘택저항을 감소시킬 수 있는 장점을 가지고 있다.As stated, the present invention is to form an SNC plug by embedding tungsten by selective chemical vapor deposition, and instead of the etch back and chemical mechanical polishing processes, only the partial chemical mechanical polishing (Touch CMP) process is performed. Simplify the plug separation process and use tungsten as a material to fill the SNC hole, which has the advantage of reducing the contact resistance.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상으이 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명에 의한 반도체 소자 제조 방법은 랜딩플러그콘택과 SNC 계면특성을 향상시키고, 콘택저항 감소와, 소자의 신뢰성 및 수율을 향상시킬 수 있는 효과가 있다.The semiconductor device manufacturing method according to the present invention described above has the effect of improving the landing plug contact and SNC interface characteristics, reducing contact resistance, and improving the reliability and yield of the device.

Claims (10)

기판상에 랜딩플러그를 형성하는 단계;Forming a landing plug on the substrate; 상기 랜딩플러그가 형성된 기판 상에 제1 층간절연막을 형성하는 단계;Forming a first interlayer insulating film on the substrate on which the landing plug is formed; 상기 제1 층간절연막 상에 비트라인패턴을 형성하는 단계;Forming a bit line pattern on the first interlayer insulating film; 상기 비트라인 패턴이 형성된 기판 상에 제2 층간절연막을 형성하는 단계;Forming a second interlayer insulating film on the substrate on which the bit line pattern is formed; 상기 제2 층간절연막 상에 하드마스크층을 형성하는 단계;Forming a hard mask layer on the second interlayer insulating film; 상기 하드마스크층과 상기 제2 층간절연막을 식각하여 상기 랜딩플러그가 노출된 스토리지노드콘택홀을 형성하는 단계;Etching the hard mask layer and the second interlayer insulating layer to form a storage node contact hole to which the landing plug is exposed; 상기 스토리지노드콘택홀 내부에 선택적 화학기상증착법으로 텅스텐을 매립하는 단계; 및Filling tungsten in the storage node contact hole by selective chemical vapor deposition; And 상기 제2 층간절연막이 드러나도록 기판 표면을 화학적기계연마하는 단계Chemical mechanical polishing the surface of the substrate to expose the second interlayer dielectric layer 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제 1항에 있어서,The method of claim 1, 상기 텅스텐 증착전에, H2SO4 + H2O2와 희석된 HF로 세정하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.Before the tungsten deposition, further comprising the step of cleaning with HF diluted with H 2 SO 4 + H 2 O 2 . 제 1항 또는 제 2항에 있어서,The method according to claim 1 or 2, 상기 텅스텐의 증착을 위한 챔버(Chamber)에서 인시튜(insitu)방식으로 플라즈마처리를 하여 세정하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.The semiconductor device manufacturing method further comprises the step of cleaning by plasma treatment in situ (Insitu) method in the chamber (Chamber) for the deposition of tungsten. 제 1항에 있어서,The method of claim 1, 상기 화학적기계연마 공정 후에, SC-1 세정 및 NH4OH + HF세정으로 잔여물을 제거하는 것을 특징으로 하는 반도체 소자 제조 방법.After the chemical mechanical polishing process, the residue is removed by SC-1 cleaning and NH 4 OH + HF cleaning. 제 1항 또는 제 4항에 있어서,The method according to claim 1 or 4, 상기 화학적기계연마 공정 후에, 플로린 계열 또는 하드록시라민(Hydroxylamine)계열 중 어느 하나의 용매를 이용한 세정으로 잔류물 및 산화물을 제거하는 것을 특징으로 하는 반도체 소자 제조 방법.After the chemical mechanical polishing step, by using a solvent of any of the florin-based or hydroxyxamine-based solvents to remove the residues and oxides, characterized in that the manufacturing method. 제 1항 또는 제 2항에 있어서,The method according to claim 1 or 2, 상기 텅스텐의 증착은 H2를 운반가스로 사용하고, SiH4 및 WF6가스를 사용하는 것을 특징으로 하는 반도체 소자 제조 방법.The deposition of tungsten uses H 2 as a carrier gas, and SiH 4 and WF 6 gas using a semiconductor device manufacturing method characterized in that. 제 6항에 있어서,The method of claim 6, 상기 텅스텐의 증착은 200~350℃의 온도에서 진행하는 것을 특징으로 하는 반도체 소자 제조 방법.The deposition of the tungsten is a semiconductor device manufacturing method, characterized in that proceeding at a temperature of 200 ~ 350 ℃. 제 7항에 있어서,The method of claim 7, wherein 상기 텅스텐의 증착 후에 500~600℃의 온도에서 열처리로 잔존하는 가스를 제거하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of manufacturing a semiconductor device, characterized in that to remove the gas remaining by heat treatment at a temperature of 500 ~ 600 ℃ after the deposition of the tungsten. 제 1항에 있어서,The method of claim 1, 상기 화학적기계연마(CMP) 공정은 pH 9~12, 퓸드실리카(Fumed Silica) 또는 콜로이드실리카(Colloidal Silica) 계열의 그룹에서 어느 하나의 물질을 연마입자로 사용하는 것을 특징으로 하는 반도체 소자 제조 방법.The chemical mechanical polishing (CMP) process is a method for manufacturing a semiconductor device, characterized in that any one of the materials in the group of pH 9-12, Fumed Silica or Colloidal Silica-based group as the abrasive particles . 제 1항에 있어서,The method of claim 1, 상기 하드마스크층은 500~1500Å 두께의 폴리실리콘임을 특징으로 하는 반도체 소자 제조 방법.The hard mask layer is a semiconductor device manufacturing method, characterized in that the polysilicon of 500 ~ 1500 ~ thickness.
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Cited By (1)

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Publication number Priority date Publication date Assignee Title
US7709367B2 (en) 2006-06-30 2010-05-04 Hynix Semiconductor Inc. Method for fabricating storage node contact in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7709367B2 (en) 2006-06-30 2010-05-04 Hynix Semiconductor Inc. Method for fabricating storage node contact in semiconductor device

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