KR20090100536A - Method for manufacturing of semiconductor device - Google Patents

Method for manufacturing of semiconductor device Download PDF

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KR20090100536A
KR20090100536A KR1020080025779A KR20080025779A KR20090100536A KR 20090100536 A KR20090100536 A KR 20090100536A KR 1020080025779 A KR1020080025779 A KR 1020080025779A KR 20080025779 A KR20080025779 A KR 20080025779A KR 20090100536 A KR20090100536 A KR 20090100536A
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South Korea
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film
cmp
forming
semiconductor device
tungsten
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KR1020080025779A
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Korean (ko)
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임지민
황경호
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주식회사 하이닉스반도체
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Priority to KR1020080025779A priority Critical patent/KR20090100536A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A manufacturing method of the semiconductor device is provided to prevent the electrical characteristic degradation of the semiconductor device by the cleaning process without the loss of the exposed tungsten film. CONSTITUTION: The gate(114) including gate conductive films(108,110) of the tungsten is formed. The hole pattern for forming a plurality of the landing plug is formed in the semiconductor substrate(100) in which the interlayer insulating film is formed. The electric conduction film for plug(118) is formed by filing each hole pattern. The electric conduction film for plug filled in each hole pattern is electrically separated by the CMP(Chemical Mechanical Polishing). The protective film is formed in the surface of the gate conductive film consisting of the tungsten exposed by CMP. The semiconductor substrate is cleaned.

Description

반도체 소자의 제조 방법{Method for manufacturing of semiconductor device}Method for manufacturing a semiconductor device

본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 보다 상세하게는, 랜딩 플러그 형성을 위한 CMP 포스크 클리닝 시 발생하는 게이트의 텅스텐막 손실을 방지할 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing tungsten film loss of a gate generated during CMP fossil cleaning for forming a landing plug.

반도체 기판의 접합 영역을 포함한 하부 도전층과 상부 도전층 사이의 전기적 연결은 콘택 플러그에 의해 이루어지는데, 반도체 소자의 고집적화가 진행됨에 따라, 상기 콘택 플러그의 형성을 위한 공정 마진(Margin) 및 콘택 면적이 감소하고 있다. 이에, 상기 상부 도전층과 하부 도전층 간의 전기적 연결을 용이하게 하기 위한 다양한 기술들이 제안되었으며, 그 예로서, 캐패시터 및 비트 라인과 접합 영역 간의 용이한 전기적 콘택을 위하여 자기정렬콘택(Self Alinged Contact : 이하, SAC) 공정이 적용되고 있다. The electrical connection between the lower conductive layer and the upper conductive layer, including the junction region of the semiconductor substrate, is made by contact plugs. As the integration of semiconductor devices increases, the process margin and contact area for forming the contact plugs are increased. This is decreasing. Accordingly, various techniques for facilitating electrical connection between the upper conductive layer and the lower conductive layer have been proposed. For example, a self-aligned contact may be provided for easy electrical contact between the capacitor and the bit line and the junction region. Hereinafter, the SAC) process is applied.

이하에서는 종래 기술에 따른 SAC 공정을 포함하여 반도체 소자의 제조방법을 간략하게 설명하도록 한다.Hereinafter, a method of manufacturing a semiconductor device, including a SAC process according to the prior art, will be briefly described.

반도체 기판 내에 활성 영역을 정의하는 소자분리 구조를 형성한 후, 상기 소자분리 구조가 형성된 반도체 기판 상에 다수의 게이트를 형성한다. 상기 게이트는 게이트 절연막과 게이트 도전막 및 게이트 하드마스크막의 적층 구조로 형성하며, 상기 게이트 도전막은 금속막, 예컨대, 텅스텐막을 포함한다. 상기 게이트들 사이의 반도체 기판 표면 내에 접합 영역을 형성한다. After forming an isolation structure defining an active region in the semiconductor substrate, a plurality of gates are formed on the semiconductor substrate on which the isolation structure is formed. The gate is formed in a stacked structure of a gate insulating film, a gate conductive film, and a gate hard mask film, and the gate conductive film includes a metal film, for example, a tungsten film. A junction region is formed in the surface of the semiconductor substrate between the gates.

상기 게이트와 접합 영역이 형성된 반도체 기판 상에 상기 게이트를 덮도록 층간절연막을 형성하고, 상기 층간절연막을 식각하여 게이트들 및 상기 게이트들 사이의 접합 영역을 동시에 노출시키는 콘택홀을 형성한다. 상기 콘택홀이 형성된 반도체 기판과 층간절연막 상에 상기 콘택홀이 매립되도록 도전막, 예컨대, 폴리실리콘막을 증착한다. 상기 폴리실리콘막에 대해 상기 게이트가 노출될 때까지 CMP(Chemical Mechanical Polishing) 공정을 수행하여 랜딩 플러그를 형성한다. An interlayer insulating layer is formed on the semiconductor substrate on which the gate and the junction region are formed to cover the gate, and the interlayer insulating layer is etched to form contact holes for simultaneously exposing the gates and the junction regions between the gates. A conductive film, for example, a polysilicon film is deposited on the semiconductor substrate on which the contact hole is formed and the interlayer insulating film so as to fill the contact hole. A landing plug is formed on the polysilicon layer by performing a chemical mechanical polishing (CMP) process until the gate is exposed.

한편, 상기 랜딩 플러그를 형성하기 위한 CMP 공정에서는 패턴 밀도 차이로 인해 상대적으로 패턴 밀도가 낮은 주변회로 영역에서는 과도 식각에 의한 부식 현상으로 상기 게이트의 텅스텐막이 노출된다. 또한, 상기 CMP 공정 후 노출되는 산화막, 폴리실리콘막 및 질화막과 같은 서로 다른 두 가지 이상의 물질이 노출되는 경우 유발되는 잔류 입자에 의한 결함(Defect)이 발생한다. On the other hand, in the CMP process for forming the landing plug, the tungsten film of the gate is exposed due to excessive etching in the peripheral circuit region having a relatively low pattern density due to the difference in pattern density. In addition, defects caused by residual particles caused when two or more different materials such as an oxide film, a polysilicon film, and a nitride film exposed after the CMP process are exposed are generated.

상기 CMP 공정 후에는 SC-1(Standard Clean-1) 용액을 이용한 CMP 포스트(Post) 클리닝 공정이 수행되며, 상기 SC-1 용액은 상기 클리닝 공정 및 상기 결함의 제거에 매우 효과적이다.After the CMP process, a CMP post cleaning process using a Standard Clean-1 (SC-1) solution is performed, and the SC-1 solution is very effective for the cleaning process and removal of the defect.

그러나, 상기 CMP 포스트 클리닝시 상기 노출된 텅스텐 부분은 상기 SC-1 용액에 의하여 손실되며, 이에 따라, 반도체 소자의 전기적 특성이 저하된다. However, during the CMP post cleaning, the exposed tungsten portion is lost by the SC-1 solution, thereby degrading the electrical characteristics of the semiconductor device.

또한, 상기 텅스텐막의 손실을 방지하기 위하여 SC-1 용액을 사용하지 않을 경우, 상기 결함을 CMP 포스트 클리닝시 효과적으로 제거하기 어렵다.In addition, when the SC-1 solution is not used to prevent the loss of the tungsten film, it is difficult to effectively remove the defect during CMP post cleaning.

본 발명은 랜딩 플러그 형성을 위한 CMP 포스크 클리닝 시 발생하는 게이트의 텅스텐막 손실을 방지할 수 있는 반도체 소자의 제조 방법을 제공한다.  The present invention provides a method of manufacturing a semiconductor device capable of preventing tungsten film loss of a gate generated during CMP fossil cleaning for forming a landing plug.

본 발명에 따른 반도체 소자의 제조 방법은, 텅스텐으로 이루어진 게이트 도전막을 포함하는 게이트들이 구비되고, 층간절연막이 형성된 반도체 기판에 다수의 랜딩 플러그 형성용 홀 패턴을 형성하는 단계; 상기 각 홀 패턴이 매립되도록 플러그용 도전막을 형성하는 단계; 상기 플러그용 도전막을 CMP(Chemical Mechanical Polishing)하여 상기 각 홀 패턴에 매립된 플러그용 도전막을 전기적으로 분리하는 단계; 상기 CMP로 노출되는 텅스텐으로 이루어진 게이트 도전막의 표면에 보호막을 형성하는 단계; 및 상기 반도체 기판을 클리닝하는 단계를 포함한다.According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a plurality of landing plug-forming hole patterns on a semiconductor substrate having gates including a gate conductive film made of tungsten and having an interlayer insulating film formed thereon; Forming a plug conductive film to fill the hole patterns; Electrically separating the plug conductive film embedded in each of the hole patterns by CMP (Chemical Mechanical Polishing) of the plug conductive film; Forming a protective film on a surface of the gate conductive film made of tungsten exposed to the CMP; And cleaning the semiconductor substrate.

상기 플러그용 도전막은 폴리실리콘으로 형성한다.The plug conductive film is made of polysilicon.

상기 CMP는 실리카계 슬러리 또는 세리아계 슬러리로 수행한다.The CMP is performed with a silica slurry or a ceria slurry.

상기 CMP 단계 후, 그리고, 상기 보호막을 형성하는 단계 전, 상기 반도체 기판을 탈이온수로 세정하는 단계를 더 포함한다.And cleaning the semiconductor substrate with deionized water after the CMP step and before the forming of the passivation layer.

상기 CMP 및 세정은 인-시튜(In-Situ)로 수행한다.The CMP and cleaning are performed in-situ.

상기 보호막을 형성하는 단계는, 상기 반도체 기판의 노출된 텅스텐막의 표 면에 산성 수용액을 접촉시켜 상기 텅스텐막의 표면을 산화시키는 방법으로 수행한다.The forming of the protective film may be performed by contacting an acidic aqueous solution to the exposed surface of the tungsten film of the semiconductor substrate by oxidizing the surface of the tungsten film.

상기 산성 수용액은 H2O2를 포함한다.The acidic aqueous solution includes H 2 O 2 .

상기 보호막은 WO2, W2O5, WO3을 포함한다.The protective film includes WO 2 , W 2 O 5 , WO 3 .

상기 클리닝하는 단계는 SC-1 용액을 이용하여 수행한다.The cleaning step is performed using an SC-1 solution.

본 발명은 랜딩 플러그를 형성하기 위한 CMP 포스트 클링닝 전에 상기 CMP로 노출된 텅스텐막의 표면에 보호막을 형성하고, 그 후에 SC-1 용액을 이용한 CMP 포스트 클리닝 공정을 수행함으로써 노출된 텅스텐막의 손실 없이 클리닝 공정을 수행할 수 있어 반도체 소자의 전기적 특성 저하를 방지할 수 있다.The present invention forms a protective film on the surface of the tungsten film exposed to the CMP before the CMP post-cleaning to form a landing plug, and then cleans without loss of the exposed tungsten film by performing a CMP post cleaning process using an SC-1 solution. The process may be performed to prevent deterioration of electrical characteristics of the semiconductor device.

본 발명은 랜딩 플러그를 형성 공정의 CMP 포스트 클링닝 시, 게이트의 텅스텐막 손실을 방지하기 위하여 CMP로 노출된 텅스텐막의 표면만을 선택적으로 산화시켜 CMP 포스트 클리닝에서 사용되는 SC-1 용액으로 CMP 과정에서 발생하는 잔류 입자를 제거함과 아울러 텅스텐막의 손실을 방지한다.The present invention selectively oxidizes only the surface of the tungsten film exposed to CMP to prevent the loss of the tungsten film of the gate during the CMP post-cleaning of the landing plug forming process, the SC-1 solution used in the CMP post cleaning in the CMP process In addition to removing residual particles generated, loss of tungsten film is prevented.

자세하게, 종래 랜딩 플러그를 형성하기 위한 CMP 포스트 클링닝 시 SC-1 용액에 의해 발생하는 게이트의 노출된 텅스텐막 손실은 SC-1 용액에 포함된 NH4OH가 염기성 pH를 갖기 때문에 상기 NH4OH에 접촉된 텅스텐막의 표면에서 상기 SC-1 용액에 용해될 수 있는 이온을 형성하기 때문이다.In detail, the exposed tungsten film loss of the gate caused by the SC-1 solution during CMP post cycling Turning to form a conventional landing plug is because the NH 4 OH included in the SC-1 solution has a basic pH the NH 4 OH This is because ions that can be dissolved in the SC-1 solution are formed on the surface of the tungsten film in contact with the.

이에, 본 발명은 랜딩 플러그를 형성하기 위한 CMP 공정 직후, H2O2 와 같은 산화제를 포함하는 산성용액으로 상기 노출된 텅스텐막을 선택적으로 표면 처리하여 상기 텅스텐막의 표면을 WO2, W2O5, WO3을 포함하는 형태로 변형시켜 상기 텅스텐막의 표면을 패시베이션(Passivation) 시킨다. 그런 다음, SC-1 용액을 이용하여 CMP 공정시 발생된 잔류 입자를 제거하는 CMP 포스트 클리닝 고정을 수행한다.Thus, the present invention selectively surface-treated the exposed tungsten film with an acidic solution containing an oxidizing agent such as H 2 O 2 immediately after the CMP process for forming a landing plug, thereby making the surface of the tungsten film WO 2 , W 2 O 5 , The surface of the tungsten film is passivated by deformation into a form including WO 3 . Then, CMP post-cleaning fixation is performed to remove residual particles generated in the CMP process using the SC-1 solution.

따라서, 상기 노출된 텅스텐막의 표면을 패시베이션 시킨 상태로 CMP 포스트 클리닝 공정을 수행함으로써 노출된 텅스텐막의 손실 없이 클리닝 공정을 수행할 수 있어 반도체 소자의 전기적 특성 저하를 방지할 수 있다.Therefore, by performing the CMP post-cleaning process with the exposed surface of the tungsten film passivated, the cleaning process can be performed without loss of the exposed tungsten film, thereby preventing deterioration of electrical characteristics of the semiconductor device.

이하에서는, 도 1a 내지 도 1e를 참조하여, 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 상세히 설명하도록 한다.Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1E.

도 1a를 참조하면, 셀 영역 및 주변 영역을 포함하는 반도체 기판(100)의 각 영역 내에 활성 영역(102)을 한정하는 소자분리막(104)을 형성한 후, 상기 반도체 기판(100) 상에 게이트(114)를 형성한다. 상기 게이트(114)는 게이트 절연막(106), 제1게이트 도전막(108), 제2게이트 도전막(110) 및 하드마스크막(112)의 적층 구조로 이루어진다. 상기 제2게이트 도전막(110)은 반도체 소자의 고집적화에 따라, 바람직하게, 전기적인 특성을 향상시키기 위하여 텅스텐막으로 이루어진다. Referring to FIG. 1A, after forming an isolation layer 104 defining an active region 102 in each region of a semiconductor substrate 100 including a cell region and a peripheral region, a gate is formed on the semiconductor substrate 100. Form 114. The gate 114 has a stacked structure of a gate insulating layer 106, a first gate conductive layer 108, a second gate conductive layer 110, and a hard mask layer 112. The second gate conductive film 110 may be formed of a tungsten film, in order to improve electrical characteristics according to high integration of semiconductor devices.

도 1b를 참조하면, 상기 게이트(114)가 형성된 반도체 기판(100) 상에 상기 게이트(114)를 덮도록 산화막으로 이루어진 층간절연막(116)을 형성한 후, 상기 게이트(114) 상부의 하드마스크막(112)이 노출되도록 CMP(Chemical mechanical polishing) 공정으로 상기 층간절연막(116)을 평탄화한다. Referring to FIG. 1B, an interlayer insulating layer 116 made of an oxide layer is formed on the semiconductor substrate 100 on which the gate 114 is formed, and then a hard mask on the gate 114. The interlayer insulating film 116 is planarized by a chemical mechanical polishing (CMP) process to expose the film 112.

도 1c를 참조하면, 상기 게이트(114) 및 상기 층간절연막(116) 상에 랜딩 플러그가 형성된 부분을 노출시키는 마스크패턴(미도시)을 형성한 후, 상기 노출된 층간절연막(116) 부분을 식각하여 상기 셀 영역에 다수의 랜딩 플러그 형성용 제1홀(H1)들을 형성함과 아울러 상기 주변 영역에 상기 제1홀(H1)들 보다 패턴 밀도가 낮은 다수의 제2홀(H2)을 형성한다. Referring to FIG. 1C, after forming a mask pattern (not shown) exposing a portion where a landing plug is formed on the gate 114 and the interlayer insulating layer 116, the portion of the exposed interlayer insulating layer 116 is etched. By forming a plurality of landing plug-forming first holes H1 in the cell region, a plurality of second holes H2 having a lower pattern density than the first holes H1 are formed in the peripheral region. .

도 1d를 참조하면, 상기 마스크패턴을 제거한 후, 상기 제1 및 제2홀(H1, H2)이 형성된 상기 반도체 기판(100)의 상기 게이트(114) 및 층간절연막(116) 상에 상기 제1 및 제2홀(H1, H2)이 매립되도록 폴리실리콘으로 이루어진 랜딩 플러그용 도전막(118)을 형성한다.Referring to FIG. 1D, after removing the mask pattern, the first and second holes H1 and H2 are formed on the gate 114 and the interlayer insulating layer 116 of the semiconductor substrate 100. And a landing film conductive film 118 made of polysilicon so as to fill the second holes H1 and H2.

그런 다음, 상기 각 제1 및 제2홀(H1, H2)의 내부에 매립된 상기 랜딩 플러그용 도전막(118)을 분리하기 위하여 상기 랜딩 플러그용 도전막(118)에 실리카계 슬러리 또는 세리아계 슬러리를 이용한 CMP 공정을 수행한다. 이때, 상기 CMP시, 상기 셀 영역과 주변 영역에 형성된 게이트(114)와 같은 패턴의 밀도 차이에 의해 패턴 밀도가 낮은 주변 영역에서는 과도 식각에 의한 부식 현상으로 상기 게이트(114)의 텅스텐막(110)이 노출된다. 또한, 상기 층간절연막(116)을 구성하는 산화막, 랜딩 플러그용 도전막(118)을 구성하는 폴리실리콘 및 상기 게이트(114)의 하드마스크막(112)을 구성하는 질화막과 같이 서로 다른 물성을 갖는 막들의 노출에 의해 입자들이 표면에 잔류하는 결함이 발생하게 된다.Then, in order to separate the landing plug conductive film 118 embedded in each of the first and second holes H1 and H2, a silica slurry or a ceria-based slurry is formed on the conductive film 118 for the landing plug. A CMP process with a slurry is performed. At this time, in the CMP, the tungsten film 110 of the gate 114 may be corroded due to excessive etching in the peripheral region having a low pattern density due to the difference in the density of the pattern such as the gate 114 formed in the cell region and the peripheral region. ) Is exposed. In addition, they have different physical properties, such as an oxide film constituting the interlayer insulating film 116, polysilicon constituting the conductive film 118 for landing plugs, and a nitride film constituting the hard mask film 112 of the gate 114. Exposure of the films results in defects in which the particles remain on the surface.

이후, 상기 랜딩 플러그용 도전막(118)이 형성된 반도체 기판(100)을 탈이온 수를 이용하여 세정한다. 상기 세정은 상기 CMP 공정이 수행되는 플래튼(Platen)에서 상기 CMP와 인-시튜(In-Situ)로 수행할 수 있으며, 외부의 버핑 패드(Buffing pad)에서 수행할 수 있다.Thereafter, the semiconductor substrate 100 on which the landing plug conductive film 118 is formed is cleaned using deionized water. The cleaning may be performed in-situ with the CMP in a platen where the CMP process is performed, and may be performed in an external buffing pad.

도 1e를 참조하면, 상기 세정 공정이 수행된 반도체 기판(100)의 상기 노출된 게이트의 제2게이트 도전막(110), 즉, 텅스텐막 표면을 H2O2를 포함하는 산성 수용액으로 표면 처리하여 상기 노출된 제2게이트 도전막(110)의 표면에 보호막(120)을 형성한다. 상기 산성 수용액에는 연마제가 포함되지 않기 때문에 더 이상의 연마는 진행되지 않으며, 상기 산성 수용액을 이용한 표면 처리는 플래튼에서 수행되거나 버핑 패드에서 수행할 수 있다. 상기 산성 수용액으로 처리된 상기 제2게이트 도전막(110)의 표면은 WO2, W2O5, WO3을 포함하는 형태로 변형되어 상기 제2게이트 도전막(110)의 노출된 표면을 패시베이션(Passivation) 시킨다.Referring to FIG. 1E, the surface of the second gate conductive film 110 of the exposed gate of the semiconductor substrate 100 on which the cleaning process is performed, that is, the tungsten film surface is treated with an acidic aqueous solution containing H 2 O 2 . As a result, the passivation layer 120 is formed on the exposed surface of the second gate conductive layer 110. Since the acidic aqueous solution does not include an abrasive, no further polishing is performed, and the surface treatment using the acidic aqueous solution may be performed on a platen or a buffing pad. The surface of the second gate conductive film 110 treated with the acidic aqueous solution is modified to include WO 2 , W 2 O 5 , and WO 3 to passivate the exposed surface of the second gate conductive film 110. (Passivation)

상기 제2게이트 도전막(110), 즉, 텅스텐막은, 도 2에 도시된 전위 도표(Pourbaix diagram)와 같이, 산성 수용액과 같이 pH가 낮은 수용액과 접촉하는 경우 산화되어 WO2, W2O5, WO3을 포함하는 형태로 상이 변형되며, 상기 제2게이트 도전막(110)이 WO2, W2O5, WO3의 형태로 변형되어도 반도체 소자의 동작에는 문제가 없다. The second gate conductive film 110, i.e., a tungsten film, as in the potential diagram (Pourbaix diagram) shown in Figure 2, the pH, such as the acidic aqueous solution is oxidized when in contact with the lower aqueous WO 2, W 2 O 5 , The phase is deformed to include WO 3 , and the second gate conductive layer 110 is deformed to WO 2 , W 2 O 5 , or WO 3 , but there is no problem in the operation of the semiconductor device.

그런 다음, 상기 CMP로 노출된 텅스텐막(110)막 상에 보호막(120)이 형성된 반도체 기판(100)에 SC-1(Standard Clean-1) 용액을 이용한 CMP 포스트 클리닝 공정을 수행하여 상기 CMP 공정 후 잔류하고 있는 잔류 입자를 제거한다. Next, the CMP process is performed by performing a CMP post-cleaning process using a SC-1 (Standard Clean-1) solution on the semiconductor substrate 100 on which the protective film 120 is formed on the tungsten film 110 exposed by the CMP. The remaining residual particles are then removed.

이상에서와 같이, 본 발명은 랜딩 플러그를 형성하기 위한 CMP 공정 직후, H2O2 와 같은 산화제를 포함하는 산성용액으로 상기 노출된 텅스텐막을 선택적으로 표면 처리하여 상기 텅스텐막의 표면에 보호막을 형성하여 텅스텐막의 표면을 패시베이션(Passivation) 시킨다.As described above, the present invention selectively surface-treated the exposed tungsten film with an acid solution containing an oxidizing agent such as H 2 O 2 immediately after the CMP process for forming a landing plug to form a protective film on the surface of the tungsten film The surface of the tungsten film is passivated.

따라서, 상기 노출된 텅스텐막의 표면에 보호막을 형성한 후 CMP 포스트 클리닝 공정을 수행함으로써 노출된 텅스텐막의 손실 없이 클리닝 공정을 수행할 수 있어 반도체 소자의 전기적 특성 저하를 방지할 수 있다.Thus, by forming a protective film on the exposed surface of the tungsten film and performing a CMP post-cleaning process, the cleaning process can be performed without losing the exposed tungsten film, thereby preventing deterioration of electrical characteristics of the semiconductor device.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정별 도면.1A to 1E are process-specific diagrams for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2는 텅스텐에 대한 전위 도표를 도시한 도면.2 shows a potential plot for tungsten.

Claims (9)

텅스텐으로 이루어진 게이트 도전막을 포함하는 게이트들이 구비되고, 층간절연막이 형성된 반도체 기판에 다수의 랜딩 플러그 형성용 홀 패턴을 형성하는 단계;Forming a plurality of landing plug-forming hole patterns on a semiconductor substrate having gates including a gate conductive film made of tungsten and having an interlayer insulating film formed thereon; 상기 각 홀 패턴이 매립되도록 플러그용 도전막을 형성하는 단계;Forming a plug conductive film to fill the hole patterns; 상기 플러그용 도전막을 CMP(Chemical Mechanical Polishing)하여 상기 각 홀 패턴에 매립된 플러그용 도전막을 전기적으로 분리하는 단계;Electrically separating the plug conductive film embedded in each of the hole patterns by CMP (Chemical Mechanical Polishing) of the plug conductive film; 상기 CMP로 노출되는 텅스텐으로 이루어진 게이트 도전막의 표면에 보호막을 형성하는 단계; 및Forming a protective film on a surface of the gate conductive film made of tungsten exposed to the CMP; And 상기 반도체 기판을 클리닝하는 단계;Cleaning the semiconductor substrate; 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 플러그용 도전막은 폴리실리콘으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The plug conductive film is formed of polysilicon. 제 1 항에 있어서,The method of claim 1, 상기 CMP는 실리카계 슬러리 또는 세리아계 슬러리로 수행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The CMP is a method of manufacturing a semiconductor device, characterized in that carried out with a silica-based slurry or a ceria-based slurry. 제 1 항에 있어서,The method of claim 1, 상기 CMP 단계 후, 그리고, 상기 보호막을 형성하는 단계 전, 상기 반도체 기판을 탈이온수로 세정하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.And cleaning the semiconductor substrate with deionized water after the CMP step and before the forming of the passivation layer. 제 4 항에 있어서,The method of claim 4, wherein 상기 CMP 및 세정은 인-시튜(In-Situ)로 수행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The CMP and the cleaning method of manufacturing a semiconductor device, characterized in that performed in-situ (In-Situ). 제 1 항에 있어서,The method of claim 1, 상기 보호막을 형성하는 단계는, 상기 반도체 기판의 노출된 텅스텐막의 표면에 산성 수용액을 접촉시켜 상기 텅스텐막의 표면을 산화시키는 방법으로 수행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The forming of the passivation layer may be performed by contacting an acidic aqueous solution to a surface of the exposed tungsten film of the semiconductor substrate by oxidizing the surface of the tungsten film. 제 6 항에 있어서,The method of claim 6, 상기 산성 수용액은 H2O2를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.The acidic aqueous solution is a method for manufacturing a semiconductor device characterized in that it comprises H 2 O 2 . 제 1 항에 있어서,The method of claim 1, 상기 보호막은 WO2, W2O5, WO3을 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 제조 방법.The protective film is characterized in that it comprises WO 2 , W 2 O 5 , WO 3 The manufacturing method of the semiconductor element. 제 1 항에 있어서,The method of claim 1, 상기 클리닝하는 단계는 SC-1(Standard Clean-1) 용액을 이용하여 수행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The cleaning step is a method of manufacturing a semiconductor device, characterized in that performed using a SC-1 (Standard Clean-1) solution.
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