KR200150506Y1 - 세라믹 패키지 - Google Patents

세라믹 패키지 Download PDF

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Publication number
KR200150506Y1
KR200150506Y1 KR2019920028312U KR920028312U KR200150506Y1 KR 200150506 Y1 KR200150506 Y1 KR 200150506Y1 KR 2019920028312 U KR2019920028312 U KR 2019920028312U KR 920028312 U KR920028312 U KR 920028312U KR 200150506 Y1 KR200150506 Y1 KR 200150506Y1
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KR
South Korea
Prior art keywords
chip
lead
attached
ceramic
ceramic package
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KR2019920028312U
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English (en)
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KR940017874U (ko
Inventor
홍성학
Original Assignee
김영환
현대전자산업주식회사
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Priority to KR2019920028312U priority Critical patent/KR200150506Y1/ko
Publication of KR940017874U publication Critical patent/KR940017874U/ko
Application granted granted Critical
Publication of KR200150506Y1 publication Critical patent/KR200150506Y1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Wire Bonding (AREA)

Abstract

본 고안은 세락믹 패키지로써, 쎄라믹베이스에 칩을 부착시키고, 칩과 리드프레임의 내부리드 부위에는 테이프를 어태치시키고 칩의 중간부위에 형성한 패드와 와이어 본딩하여 구성된 것이며 세락믹 패키지에서 칩이 커짐에 따라 와이어 본딩시 어려운점을 칩위에 내부리드가 오도록하여 와이어 본딩 문제를 해결할 수 있다.

Description

세라믹 패키지
제1도는 종래의 단면도.
제2도는 본 고안의 제조설명도.
제3도는 본 고안에 사용되는 세라믹베이스 평면도.
제4도는 본 고안의 단면도이다.
* 도면의 주요부분에 대한 부호의 설명
10 : 세라믹 베이스 11 : 칩
12 : 테이프 13 : 패드
14 : 와이어 20 : 리드프레임
21 : 내부리드
본 고안은 세라믹 패키지에 관한 것으로, 세라믹 베이스에 부착한 칩위에 내부리드가 어태치되고 칩 중앙에서 와이어본딩되도록 한 세라믹 패키지에 관한 것이다.
종래의 세라믹 패키지는 제 1도와 같이 세라믹베이스(1)에 페이스트(6)를 도포하여 칩(4)을 어태치하고, 리드프레임(3)을 접착제(7)로 고정시킨 상태에서 칩(4)의 패드(7')와 리드프레임(3)의 리드는 와이어(5)로 와이어 본딩하며, 다시 접착제(7)를 도포하여 세라믹캡(2)을 부착결합시켜 세라믹 패키지를 제조하였다.
이경우 칩(4)이 이전과 같이 작은 경우에는 별 문제가 없으나 점차 대용량화 되어감에 따라 칩(4)도 커지고 있는 추세에 따라, 칩(4)이 커질수록 세라믹베이스(1)의 외경은 그대로이므로 리드프레임(3)의 내부리드 부위만 작아지게 되고, 이에따라 와이어본딩할 부위가 너무작아 와이어 본딩이 어렵게 되는 단점이 있다.
본 고안은 이를 해결하고자 세라믹베이스에 부착한 칩위로 리드프레임이 위치되도록하여 와이어본딩 문제를 해결하게함을 특징으로 한다.
즉, 세라믹베이스에 칩을 부착시키고, 칩과 리드프레임의 내부리드 부위에는 테이프를 어태치시켜 칩의 중간부위에 형성한 패드와 와이어본딩하여 구성된 것이다.
이하 도면을 참조하여 상세히 설명하면 다음과 같다.
본 고안은 세라믹베이스(10)에 칩(11)을 부착시키고, 칩(11)과 리드프레임(20)의 내부리드(21) 부위는 테이프(12)로 어태치시키고, 칩(11)의 중간부위에 형성한 패드(13)와 와이어(14) 본딩하여 구성된 것이다. (15)는 버스바이고, (16)는 외부리드이며, (17)는 댐버이다.
즉, 세라믹베이스(10)에 칩(11)을 어태치하고 칩(11)과 리드프레임(20)의 내부리드(21) 부위를 테이프(12)로 부착시키고, 내부리드(21)와 패드(13)를 와이어(14)본딩하여, 이를 제 4도와 같이 접착제(7)를 사용하여 세라믹캡(2)을 붙여 완성한다.
이경우 칩(11)위에 내부리드(21)가 직접 붙게되므로 칩(11)의 사이즈가 커져도 와이어본딩의 문제가 없게 된다.
이는 제 2도 및 제 4도에 보인 바와 같이 칩(11)의 패드(13)를 중앙부위에 위치케하여 와이어본딩을 용이하게 하기 때문이다. 따라서 세라믹 패키지에도 리드온칩(LOC) 형태를 적용하여 칩의 크기가 커짐에 따른 와이어본딩의 문제를 해결할 수 있다.
이상과 같이 본 고안은 세라믹 패키지에서 칩이 커짐에 따라 와이어본딩이 어려운점을 칩위에 내부리드가 오도록하여 와이어본딩 문제를 해결할 수 있다.

Claims (1)

  1. 세라믹 베이스(10)에는 내측에 패드(13)를 구비한 칩(11)이 부착되어 있고, 상기 칩(11)상에 리드프레임(20)의 내부리드(21)가 부착되어 있으며, 또한 상기 리드프레임(20)의 내부리드(21)가 상기 패드(13)와 와이어 본딩되어 있는 것을 특징으로 하는 세라믹 패키지.
KR2019920028312U 1992-12-31 1992-12-31 세라믹 패키지 KR200150506Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019920028312U KR200150506Y1 (ko) 1992-12-31 1992-12-31 세라믹 패키지

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019920028312U KR200150506Y1 (ko) 1992-12-31 1992-12-31 세라믹 패키지

Publications (2)

Publication Number Publication Date
KR940017874U KR940017874U (ko) 1994-07-28
KR200150506Y1 true KR200150506Y1 (ko) 1999-07-01

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KR2019920028312U KR200150506Y1 (ko) 1992-12-31 1992-12-31 세라믹 패키지

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8381225B2 (en) 2003-04-30 2013-02-19 International Business Machines Corporation Automated processor reallocation and optimization between logical partitions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8381225B2 (en) 2003-04-30 2013-02-19 International Business Machines Corporation Automated processor reallocation and optimization between logical partitions

Also Published As

Publication number Publication date
KR940017874U (ko) 1994-07-28

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