KR20010077140A - Method for forming interconnection in semiconductor device - Google Patents
Method for forming interconnection in semiconductor device Download PDFInfo
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- KR20010077140A KR20010077140A KR1020000004724A KR20000004724A KR20010077140A KR 20010077140 A KR20010077140 A KR 20010077140A KR 1020000004724 A KR1020000004724 A KR 1020000004724A KR 20000004724 A KR20000004724 A KR 20000004724A KR 20010077140 A KR20010077140 A KR 20010077140A
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 230000004888 barrier function Effects 0.000 claims abstract description 36
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010936 titanium Substances 0.000 claims abstract description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract 2
- 238000010438 heat treatment Methods 0.000 claims description 16
- 230000008569 process Effects 0.000 abstract description 21
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052721 tungsten Inorganic materials 0.000 abstract description 8
- 239000010937 tungsten Substances 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 238000005240 physical vapour deposition Methods 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 238000004140 cleaning Methods 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 3
- 238000004151 rapid thermal annealing Methods 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 장치에 관한 것으로 특히, 고온에 대한 열적 안정성을 갖는 반도체 장치의 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for forming a wiring of a semiconductor device having thermal stability against high temperature.
일반적으로, 반도체 소자의 집적화가 진행됨에 따라 필연적으로 소자의사이즈가 작아지면서 소자의 스피드 또한 중요한 문제로 부각되고 있다. 대부분의 반도체 소자는 씨오비(COB:Capacitor Over Bit line)구조를 갖기 때문에 텅스텐 비트라인을 채용한 기술을 적용하기 위해서는 800℃이상의 고온 열처리 공정에서 텅스텐 비트라인이 열적으로 안정적이어야 한다.In general, as the integration of semiconductor devices proceeds, the size of the devices inevitably decreases, and the speed of the devices also becomes an important problem. Since most semiconductor devices have a COB (Capacitor Over Bit line) structure, the tungsten bit line must be thermally stable in a high temperature heat treatment process of 800 ° C. or higher in order to apply the technology using the tungsten bit line.
그리고 후속의 열처리 공정에서도 열적 안정성을 갖기 위해서는 베리어(barrier)막이 완벽하게 베리어 자체의 역할을 할 수 있어야 한다.And in order to have thermal stability in the subsequent heat treatment process, the barrier film must be able to function as the barrier itself.
통상, COB구조를 갖는 텅스텐 비트라인의 경우 주로 메인 메모리부의 커패시터에 전하를 전달하거나 저장된 전하를 읽는 기능을 담당하게 되므로 소자의 스피드를 좌우하게 된다.In general, a tungsten bit line having a COB structure mainly plays a function of transferring charge to a capacitor of a main memory unit or reading a stored charge, thereby controlling the speed of the device.
따라서, 실리콘과 접하는 액티브 영역에서의 낮은 콘택저항값과 낮은 정션 리키지 전류(low junction leakage current)값은 매우 중요한 문제이다.Therefore, low contact resistance and low junction leakage current in the active region in contact with silicon are very important problems.
이하, 첨부된 도면을 참조하여 종래 기술에 따른 반도체 장치의 배선 형성방법을 설명하기로 한다.Hereinafter, a wiring forming method of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 1d는 종래 기술에 따른 반도체 장치의 배선 형성방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a wiring of a semiconductor device according to the prior art.
도 1a에 도시된 바와 같이, 반도체 기판(11)상에 절연층(12)을 형성한 후, 절연층(12)상에 포토레지스트(도시되지 않음)를 도포한다. 노광 및 현상 공정을 이용하여 포토레지스트를 패터닝하고, 패터닝된 포토레지스트를 마스크로 이용한 식각 공정으로 도 1b에 도시된 바와 같이, 절연층(12)을 선택적으로 제거하여 콘택홀(13)을 형성한다.As shown in FIG. 1A, after forming the insulating layer 12 on the semiconductor substrate 11, a photoresist (not shown) is applied on the insulating layer 12. The photoresist is patterned using an exposure and development process, and the contact layer 13 is formed by selectively removing the insulating layer 12 as shown in FIG. 1B by an etching process using the patterned photoresist as a mask. .
도 1c에 도시된 바와 같이, 콘택홀(13)을 포함한 절연층(12)상에 베리어층(14)을 형성한 후, 고속 열처리 장치(RTP:Rapid Thermal Process)를 이용하여 열처리 공정을 진행한다. 여기서, 베리어층(14)은 티타늄(Ti)/티타늄 나이트라이드(TiN)의 적층막이다.As shown in FIG. 1C, after the barrier layer 14 is formed on the insulating layer 12 including the contact hole 13, a heat treatment process is performed by using a rapid thermal process (RTP). . Here, the barrier layer 14 is a laminated film of titanium (Ti) / titanium nitride (TiN).
이후, 도 1d에 도시된 바와 같이, 상기 베리어층(14)상에 텅스텐을 증착한 후, 평탄화 공정을 진행하여 텅스텐 비트라인(15)을 형성하면 종래 기술에 따른 반도체 장치의 배선 형성공정이 완료된다.Thereafter, as shown in FIG. 1D, after the tungsten is deposited on the barrier layer 14, the planarization process is performed to form the tungsten bit line 15, thereby completing the wiring forming process of the semiconductor device according to the related art. do.
그러나 상기와 같은 종래 반도체 장치의 배선 형성방법은 다음과 같은 문제점이 있었다.However, the wiring forming method of the conventional semiconductor device as described above has the following problems.
콘택홀을 형성함에 있어서 티타늄과 디퓨젼(diffusion)베리어인 티타늄 나이트라이드막을 증착한 후 고속 열처리 공정을 진행하는데, 이때 티타늄과 실리콘이 반응하여 티타늄실리사이드(TiSi2)가 형성된다. 하지만, 티타늄실리사이드막은 고온 열처리 공정을 진행함에 따라 표면 에너지(surface energy)를 줄이기 위하여 티타늄실리사이드막은 응집작용이 일어난다. 따라서, 티타늄실리사이드막의 표면이 불균일하게 된다. 이는 소자의 특성중의 하나인 정션 리키지 커런트를 유발시키게 되며, 콘택 저항을 악화시키는 요인으로 작용한다.In forming the contact hole, a titanium nitride film, which is a titanium and a diffusion barrier, is deposited and then subjected to a high-speed heat treatment. At this time, titanium and silicon react to form titanium silicide (TiSi 2 ). However, as the titanium silicide film is subjected to a high temperature heat treatment process, the titanium silicide film is coagulated to reduce surface energy. Therefore, the surface of the titanium silicide film becomes uneven. This causes the junction liquid current, which is one of the characteristics of the device, and deteriorates the contact resistance.
또한, 텅스텐 비트라인을 형성함에 따라 WF96가스를 사용하는데, 상기 WF6가스가 디퓨젼 베리어층인 티타늄 나이트라이드막에 침투하여 티타늄과 실리콘 경계면에 축적되고, 이로인해 티타늄과 WF6의 반응에 의하여 생성된 TiF3화합물은 베리어층의 접착력을 악화시키는 주요인으로 작용하므로 베리어층 증착시 문제점으로 나타나고 있다. 따라서 콘택 저항 및 정션 리키지 전류 특성이 더욱 악화된다.In addition, WF 96 gas is used as the tungsten bit line is formed, and the WF 6 gas penetrates into the titanium nitride film, which is a diffusion barrier layer, and accumulates at the titanium and silicon interface, thereby reacting the reaction between titanium and WF 6 . TiF 3 compound produced by the acts as a major factor to deteriorate the adhesion of the barrier layer has appeared to be a problem when the barrier layer deposition. As a result, the contact resistance and junction leakage current characteristics are further deteriorated.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로 콘택저항 및 정션 리키지 커런트 특성을 향상시킬 수 있도록 열정 안정성을 확보한 반도체 장치의 배선 형성방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a method for forming a wiring of a semiconductor device with a passionate stability to improve contact resistance and junction liquid current characteristics.
도 1a 내지 1d는 종래 기술에 따른 반도체 장치의 배선 형성방법을 설명하기 위한 공정단면도1A to 1D are cross-sectional views illustrating a method of forming wirings in a semiconductor device according to the prior art.
도 2a 내지 2d는 본 발명 반도체 장치의 배선 형성방법을 설명하기 위한 공정단면도2A through 2D are cross-sectional views illustrating a method of forming wirings in a semiconductor device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
21 : 반도체 기판 22 : 절연층21 semiconductor substrate 22 insulating layer
23 : 콘택홀 24 : 제 1 베리어층23: contact hole 24: the first barrier layer
25 : 티타늄실리사이드층 26 : 제 2 베리어층25: titanium silicide layer 26: second barrier layer
27 : 비트라인27: bit line
상기의 목적을 달성하기 위한 본 발명 반도체 장치의 배선 형성방법은 반도체층상에 상기 반도체층이 소정부분 노출되도록 콘택홀을 갖는 절연층을 형성하는 공정과, 상기 콘택홀을 포함한 절연층상에 제 1 베리어층을 형성하는 공정과, 상기 제 1 베리어층상에 제 2 베리어층을 형성하는 공정과, 상기 제 2 베리어층상에 금속배선층을 형성하는 공정을 포함하여 이루어진다.The wiring forming method of the semiconductor device of the present invention for achieving the above object is a step of forming an insulating layer having a contact hole to expose a predetermined portion of the semiconductor layer on the semiconductor layer, and a first barrier on the insulating layer including the contact hole A step of forming a layer, a step of forming a second barrier layer on the first barrier layer, and a step of forming a metal wiring layer on the second barrier layer.
이하, 본 발명 반도체 장치의 배선 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a wiring forming method of the semiconductor device of the present invention will be described with reference to the accompanying drawings.
먼저, 본 발명은 티타늄막과 티타늄나이트라이드막을 차례로 형성한 후, 고속 열처리 공정을 진행하고, 상기 티타늄나이트라이드막상에 베리어층인 티타늄나이트라이드막을 다시 증착함으로써, 후속 열처리 공정에서도 열적, 구조적으로 안정하도록 한 반도체 장치의 배선 형성방법이다.First, the present invention sequentially forms a titanium film and a titanium nitride film, and then proceeds with a high-speed heat treatment process, and again deposits a titanium nitride film as a barrier layer on the titanium nitride film, thereby thermally and structurally stable in a subsequent heat treatment process. It is a wiring forming method of a semiconductor device.
이를 도 2a 내지 2d를 참조하여 보다 상세하게 설명하면 다음과 같다.This will be described in more detail with reference to FIGS. 2A to 2D.
도 2a 내지 2d는 본 발명 반도체 장치의 배선 형성방법을 설명하기 위한 공정단면도이다.2A to 2D are cross-sectional views for explaining the wiring forming method of the semiconductor device of the present invention.
도 2a에 도시한 바와 같이, 반도체 기판(22) 또는 반도체층상에 절연층(22)을 형성한다. 절연층(22)상에 포토레지스트(도시하지 않음)를 도포한 후, 노광 및 현상 공정을 이용하여 패터닝하고, 패터닝된 포토레지스트를 마스크로 이용한 식각 공정으로 도 2b에 도시한 바와 같이, 절연층(22)을 선택적으로 제거하여 콘택홀(23)을 형성한다.As shown in FIG. 2A, the insulating layer 22 is formed on the semiconductor substrate 22 or the semiconductor layer. After applying a photoresist (not shown) on the insulating layer 22, it is patterned using an exposure and development process, an etching process using the patterned photoresist as a mask, as shown in Figure 2b, The contact hole 23 is formed by selectively removing the 22.
이어, 노출된 반도체 기판 또는 반도체층상에 형성된 자연산화막(도시하지 않음)을 제거하기 위해 클리닝(cleaning)을 실시한다.Subsequently, cleaning is performed to remove the native oxide film (not shown) formed on the exposed semiconductor substrate or the semiconductor layer.
이어, 도 2c에 도시한 바와 같이, 제 1 베리어층(24)을 형성한 후, 질소(N2)분위기에서 고속 열처리 공정을 수행한다.Subsequently, as shown in FIG. 2C, after the first barrier layer 24 is formed, a high speed heat treatment process is performed in a nitrogen (N 2 ) atmosphere.
이때, 상기 제 1 베리어층(24)은 티타늄층과 티타늄나이트라이드층의 적층막이며 대기중에 노출시키지 않고 연속하여 증착한다.In this case, the first barrier layer 24 is a laminated film of a titanium layer and a titanium nitride layer and is continuously deposited without being exposed to the atmosphere.
그리고, 티타늄층과 티타늄나이트라이드층은 PVD(Physical Vapor Deposition) 또는 CVD(Chemical Vapor Deposition)법으로 증착한다.The titanium layer and the titanium nitride layer are deposited by PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition).
여기서, 상기 티타늄나이트라이드층은 이후에 티타늄실리사이드층을 형성에 따른 콘택저항이 증가되는 것을 방지하기 위한 것으로, 티타늄실리사이드층을 형성하기 이전에 대기중에 산소와 같은 불순물이 존재할 경우 티타늄실리사이드층의 응집력이 악화되므로 이를 방지하기 위해 형성한다.Here, the titanium nitride layer is to prevent the increase in contact resistance due to the subsequent formation of the titanium silicide layer, the cohesion force of the titanium silicide layer when an impurity such as oxygen in the atmosphere before forming the titanium silicide layer It will deteriorate and thus form to prevent it.
한편, 상기 고속 열처리 공정을 수행함에 따라 티타늄층과 반도체 기판(21) 또는 반도체층과의 계면에 티타늄실리사이드층(25)이 형성되며 상기 고속 열처리 온도는 800℃~850℃의 범위에서 실시하며, 열처리는 질소(N2)분위기에서 약20초~30초동안 실시한다.Meanwhile, the titanium silicide layer 25 is formed at the interface between the titanium layer and the semiconductor substrate 21 or the semiconductor layer as the high speed heat treatment process is performed, and the high speed heat treatment temperature is performed in the range of 800 ° C. to 850 ° C., Heat treatment is carried out in a nitrogen (N 2 ) atmosphere for about 20-30 seconds.
이후, 도 2d에 도시한 바와 같이, 상기 제 1 베리어층(24)상에 제 2 베리어층(26)을 형성하고, 상기 제 2 베리어층(26)상에 비트라인 물질을 증착한 후 평탄화하여 비트라인(27)을 형성하면 본 발명 반도체 소자의 배선 형성공정이 완료된다.2D, a second barrier layer 26 is formed on the first barrier layer 24, a bit line material is deposited on the second barrier layer 26, and then planarized. When the bit line 27 is formed, the wiring forming process of the semiconductor device of the present invention is completed.
여기서, 상기 제 2 베리어층(26)은 티타늄나이트라이드층이며, 상기 비트라인(27)은 텅스텐으로 형성한다.Here, the second barrier layer 26 is a titanium nitride layer, and the bit line 27 is formed of tungsten.
이상 상술한 바와 같이 본 발명 반도체 장치의 배선 형성방법은 다음과 같은 효과가 있다.As described above, the wiring forming method of the semiconductor device of the present invention has the following effects.
첫째, 800℃ 이상의 고온 열처리 공정이 수반된다고 하더라도 콘택홀의 구조가 매우 안정적이며, 충분히 고온에서도 견딜 수 있는 베리어층을 얻을 수 있다.First, even if the high temperature heat treatment process is 800 ℃ or more involved, the structure of the contact hole is very stable, it is possible to obtain a barrier layer that can withstand even at a sufficiently high temperature.
둘째, 후속의 고온 열처리 공정후에도 티타늄실리사이드층의 응집작용을 최소화시키면서 정션 리키지 커런트에 의한 문제를 방지할 수 있다.Second, even after the subsequent high temperature heat treatment process, it is possible to prevent the problem caused by the junction liquid current while minimizing the aggregation action of the titanium silicide layer.
셋째, 고온 열처리 공정후에도 콘택구조의 불량없이 낮은 콘택저항을 얻을수 있다.Third, a low contact resistance can be obtained even after the high temperature heat treatment process without the defect of the contact structure.
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