KR20020002973A - Method for forming titanium silicide ohmic contact layer of semiconductor device - Google Patents

Method for forming titanium silicide ohmic contact layer of semiconductor device Download PDF

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KR20020002973A
KR20020002973A KR1020000037352A KR20000037352A KR20020002973A KR 20020002973 A KR20020002973 A KR 20020002973A KR 1020000037352 A KR1020000037352 A KR 1020000037352A KR 20000037352 A KR20000037352 A KR 20000037352A KR 20020002973 A KR20020002973 A KR 20020002973A
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film
layer
titanium
semiconductor device
forming
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KR100626741B1 (en
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엄장웅
손현철
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

PURPOSE: A method for forming a titanium silicide ohmic contact layer of a semiconductor device is provided to prevent the damage of a junction region and a condensing effect in a rapid thermal process for forming a titanium silicide. CONSTITUTION: A contact hole for exposing a source/drain junction region(21) within a silicon substrate(20) is formed by etching selectively an interlayer insulating layer(22). The substrate(20) is cleaned by a cleaning process. A Ti layer(23), and a TiAlN layer(24) are formed on a whole surface of the above structure. A nitrogen ion implantation layer is formed by implanting nitrogen ions into a boundary face between the Ti layer(23) and the TiAlN layer(24). A titanium silicide layer(23A) is formed on the source/drain junction region(21) by performing a rapid thermal process under a temperature of 650 to 900 degrees centigrade and an N2 atmosphere for 10 to 100 seconds. A barrier metal layer(26) and a metal layer(27) are deposited thereon. A metal line is formed by patterning the barrier metal layer(26).

Description

반도체 소자의 티타늄 실리사이드 오믹 콘택층 형성 방법{Method for forming titanium silicide ohmic contact layer of semiconductor device}Method for forming titanium silicide ohmic contact layer of semiconductor device

본 발명은 반도체 소자 제조 분야에 관한 것으로, 특히 티타늄 실리사이드 오믹 콘택층 형성 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method for forming a titanium silicide ohmic contact layer.

반도체 소자는 웨이퍼 상에 여러 소자를 구현하고 각 소자의 상호 연결을 위해 금속배선을 형성한다. 금속배선의 물질 재료로는 주로 Al, W 등이 이용되고 있다.Semiconductor devices implement several devices on a wafer and form metallization for interconnecting each device. Al, W, etc. are mainly used as a material material of metal wiring.

Al은 Si, SiO2등에 대한 접착력이 우수하고, 강하게 도핑된 n+, p+실리콘과 오믹(ohmic) 저항 특성을 가지며, 전기 비저항 값이 타 금속들에 비해 비교적 낮다는 장점들로 인해 반도체 소자의 금속배선 재료로서 가장 널리 사용되어온 재료이다. 그리고 W은 Al에 비해 저항이 크기는 하지만 피복 특성이 양호하여 고집적 반도체 소자의 배선 재료로 각광받고 있다.Al has excellent adhesion to Si, SiO 2, etc., has a strong doped n + , p + silicon and ohmic resistance, and has a relatively low electrical resistivity compared to other metals. Is the most widely used material for metal wiring. W has a higher resistance than Al, but has a good coating property, and thus, W has been spotlighted as a wiring material for highly integrated semiconductor devices.

이러한, Al은 저융점(670 ℃) 금속이라는 특징으로 인해 공정중에 EM(electromigration), SM(stress-migration), 접합파괴(junction spiking) 등의 현상을 유발하여 소자의 신뢰성에 악영향을 미칠 수 있다. EM 현상이란 전자가 Al 배선을 통해 이동할 때 Al 이온과 충돌하여 전자의 운동량(momentum)이 Al 이온에 전달됨으로써 전자의 흐름 방향으로 Al의 질량 유동(mass flux)이 생기는 현상을 말한다. 이러한 Al의 이동은 상온 부근의 온도에서 주로 결정립계를 통해 이동하는데 결정립계의 불균일성으로 인해 Al 유동의 차이(divergence)가 생기면, 배선에 공공(void)을 발생시켜 배선의 단선 불량을 유발하게 된다. 한편, SM 현상이란 Al 배선 주위의 절연막에 의한 응력에 의해 Al 배선에 변형이 발생하여 배선의 단선 불량을 유발하는 현상을 일컫는다. 이러한, EM, SM 현상은 소자가 고집적화됨에 따라 금속배선의 단면적이 감소하고, 전류밀도가 증가되므로 소자의 신뢰성에 악영향을 미치게 된다. 따라서 이러한 현상들을 억제하기 위하여 반도체의 금속배선으로 Al을 사용할 경우에는 수 %의 Cu를 Al 타겟에 첨가하여 Al 합금을 증착하는 것이 일반적이다.Since Al is a low melting point (670 ° C.) metal, it may adversely affect the reliability of devices by causing phenomena such as EM (electromigration), stress-migration (SM), and junction spiking during the process. . EM phenomenon refers to a phenomenon in which the mass flux of Al occurs in the flow direction of electrons because electrons collide with Al ions and the momentum of the electrons is transferred to Al ions when the electrons move through the Al wiring. The movement of Al mainly moves through the grain boundary at a temperature near room temperature. If divergence of Al flow occurs due to the nonuniformity of the grain boundary, voids are generated in the wiring to cause disconnection of the wiring. On the other hand, the SM phenomenon refers to a phenomenon in which deformation occurs in the Al wiring due to stress caused by an insulating film around the Al wiring, causing a disconnection failure of the wiring. As the device is highly integrated, the EM and SM phenomena decrease the cross-sectional area of the metal wiring and increase the current density, which adversely affects the reliability of the device. Therefore, in order to suppress these phenomena, when Al is used as a metal wiring of a semiconductor, it is common to add Al% of Cu to the Al target to deposit an Al alloy.

접합파괴 현상이란 Si와 Al이 상호 확산됨으로 인하여 접합이 파괴되는 현상으로서 이를 방지하기 위하여 Al에 수 %의 Si를 첨가하여 Al막으로 Si가 확산되는 것을 억제하거나 Si과 Al 사이에 확산방지 역할을 하는 장벽금속층(barrier layer)를 형성하는 것이 일반적이다.Bond breakage is a phenomenon in which bonding is broken due to mutual diffusion of Si and Al. In order to prevent this, several percent of Si is added to Al to prevent diffusion of Si into the Al film or to prevent diffusion between Si and Al. It is common to form a barrier metal layer.

장벽금속층으로서는 Ti막이 주로 이용되는데, Ti막과 실리콘 기판을 오믹 콘택(ohmic contact)시키기 위하여 티타늄 실리사이드 오믹 콘택층을 형성한다.As the barrier metal layer, a Ti film is mainly used. A titanium silicide ohmic contact layer is formed to ohmic contact the Ti film and the silicon substrate.

이하, 첨부된 도면 도 1a 및 도 1b를 참조하여 종래 기술에 따른 티타늄 실리사이드 오믹 콘택층 형성 방법을 설명한다.Hereinafter, a method of forming a titanium silicide ohmic contact layer according to the related art will be described with reference to FIGS. 1A and 1B.

도 1a는 트랜지스터 등의 하부구조 형성이 완료된 실리콘 기판(10)을 덮는 층간절연막(12)을 선택적으로 식각하여 실리콘 기판(10) 내의 소오스 또는 드레인 접합영역(11)을 노출시키는 콘택홀을 형성하고, 전체 구조 상에 Ti막(13)을 형성한 상태를 보이고 있다.FIG. 1A shows a contact hole exposing the source or drain junction region 11 in the silicon substrate 10 by selectively etching the interlayer insulating layer 12 covering the silicon substrate 10 on which the substructure of the transistor or the like is completed. The Ti film 13 is formed on the whole structure.

도 1b는 RTP(rapid thermal process) 등과 같은 열처리 공정으로 실리콘 기판(10)과 Ti막(13)을 상호확산시켜 소오스 또는 드레인 접합영역(11) 상에 TiSi2층(13A)을 형성한 것으로 보이고 있다.FIG. 1B shows that the TiSi 2 layer 13A is formed on the source or drain junction region 11 by mutually diffusing the silicon substrate 10 and the Ti film 13 by a heat treatment process such as a rapid thermal process (RTP). have.

전술한 바와 같이 상호확산에 의해 TiSi2층(13A)을 형성하는 과정에서 실리콘 기판(10)의 소모량이 심하여 그에 따라 접합영역(11)이 파괴될 수도 있다. 또한 열처리 공정시 산소가 TiSi2층(13A)으로 침입하여 산화시키므로 TiSi2층(13A) 형성과정에서 응집화를 촉진시켜 콘택저항이 불안정해지고 누설전류가 증가하여 반도체 소자의 특성을 열화시키는 문제점이 있다.As described above, in the process of forming the TiSi 2 layer 13A by interdiffusion, the consumption of the silicon substrate 10 is severe, and thus the junction region 11 may be destroyed. In addition, since oxygen penetrates and oxidizes into the TiSi 2 layer 13A during the heat treatment process, it promotes agglomeration during the formation of the TiSi 2 layer 13A, so that contact resistance becomes unstable and leakage current increases, thereby deteriorating the characteristics of the semiconductor device. have.

상기와 같은 문제점을 해결하기 위한 본 발명은 티타늄 실리사이드 오믹 콘택층 형성 과정에서 실리콘 기판의 과다 소모에 따른 접합영역 파괴를 방지하고, 티타늄 실리사이드 형성을 위한 열처리 과정에서 응집화가 촉진되는 것을 효과적으로 방지할 수 있는 반도체 소자의 티타늄 실리사이드 오믹 콘택층 형성 방법을 제공하는데 그 목적이 있다.The present invention for solving the above problems can be prevented from destroying the junction region due to excessive consumption of the silicon substrate in the process of forming the titanium silicide ohmic contact layer, and effectively prevent the aggregation from being promoted during the heat treatment process for forming the titanium silicide. It is an object of the present invention to provide a method for forming a titanium silicide ohmic contact layer of a semiconductor device.

도 1a 및 도 1b는 종래 기술에 따른 오믹 콘택층 형성 공정 단면도,1A and 1B are cross-sectional views of an ohmic contact layer forming process according to the prior art;

도2 a 내지 도 2d는 본 발명의 실시 예에 따른 반도체 소자의 금속배선 형성 공정 단면도.2A to 2D are cross-sectional views of metal wire forming processes of a semiconductor device in accordance with an embodiment of the present invention.

*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *

23: Ti막 24: TiAl막23: Ti film 24: TiAl film

25: 질소이온주입층 26: 장벽금속층25: nitrogen ion implantation layer 26: barrier metal layer

27: 금속막 23A: 티타늄 실리사이드층27: metal film 23A: titanium silicide layer

상기와 같은 목적을 달성하기 위한 본 발명은 실리콘 기판 상에 티타늄(Ti)막을 형성하는 제1 단계; 상기 티타늄막 상에 산소확산방지막을 형성하는 제2 단계; 상기 티타늄막과 상기 산소확산방지막 계면에 질소를 이온주입하는 제3 단계; 및 열처리 공정을 실시하여 티타늄 실리사이드를 형성함과 동시에 티타늄을 질화시키는 제4 단계를 포함하는 반도체 소자 제조 방법을 제공한다.The present invention for achieving the above object is a first step of forming a titanium (Ti) film on a silicon substrate; Forming an oxygen diffusion barrier on the titanium film; A third step of ion implanting nitrogen at an interface between the titanium film and the oxygen diffusion prevention film; And performing a heat treatment process to form titanium silicide and simultaneously nitride titanium.

또한 상기와 같은 목적을 달성하기 위한 본 발명은, 트랜지스터 형성이 완료된 실리콘 기판 상부에 형성된 층간절연막을 선택적으로 식각하여 상기 실리콘 기판 내에 형성된 소오스 또는 드레인 접합을 노출시키는 콘택홀을 형성하고, 전체 구조 상에 티타늄(Ti)막을 형성하는 제1 단계; 상기 티타늄막 상에 산소확산방지막을 형성하는 제2 단계; 상기 티타늄막과 상기 산소확산방지막 계면에 질소를 이온주입하는 제3 단계; 및 열처리 공정을 실시하여 티타늄 실리사이드를 형성함과 동시에 티타늄을 질화시키는 제4 단계를 포함하는 반도체 소자 제조 방법을 제공한다.In addition, the present invention for achieving the above object, to form a contact hole for selectively exposing the source or drain junction formed in the silicon substrate by selectively etching the interlayer insulating film formed on the silicon substrate is completed transistor formation, the overall structure Forming a titanium (Ti) film on the substrate; Forming an oxygen diffusion barrier on the titanium film; A third step of ion implanting nitrogen at an interface between the titanium film and the oxygen diffusion prevention film; And performing a heat treatment process to form titanium silicide and simultaneously nitride titanium.

본 발명은 실리콘 기판과 접하는 Ti막 상에 상부 장벽층(capping barrier) 즉, 산소확산 방지막으로서 TiAlN막을 증착하고, Ti막과 TiAlN막 계면에 질소를 이온주입법으로 첨가함으로써, 티타늄 실리사이드형성을 위한 열처리 공정시 산소의 침입에 의한 티타늄실리사이드의 응집화를 억제함과 동시에 질소에 의한 티타늄의 질화를 동시에 진행시켜 실리콘 기판의 손실에 의한 소오스 또는 드레인 접합영역의 손상을 감소시키는데 그 특징이 있다. 이에 따라, 콘택저항 및 누설전류를 안정화시킬 수 있다.The present invention provides a heat treatment for forming titanium silicide by depositing a TiAlN film as a capping barrier, that is, an oxygen diffusion prevention film, on a Ti film in contact with a silicon substrate, and adding nitrogen to the Ti film and the TiAlN film interface by ion implantation. It is characterized by reducing the cohesion of titanium silicide due to oxygen intrusion during the process and simultaneously nitriding titanium with nitrogen to reduce damage to the source or drain junction region due to the loss of the silicon substrate. As a result, contact resistance and leakage current can be stabilized.

이하, 첨부된 도면 도2 a 내지 도 2d를 참조하여 본 발명의 실시 예에 따른 반도체 소자의 오믹 콘택층 형성 방법을 설명한다.Hereinafter, a method of forming an ohmic contact layer of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings of FIGS. 2A to 2D.

먼저 도 2a에 도시한 바와 같이 트랜지스터 등의 하부구조 형성이 완료된 실리콘 기판(20)을 덮는 층간절연막(22)을 선택적으로 식각하여 실리콘 기판(20) 내의 소오스 또는 드레인 접합영역(21)을 노출시키는 콘택홀을 형성하고, 세정(cleaning) 공정을 실시한 다음 전체 구조 상에 Ti막(23) 및 TiAlN막(24)을 형성한다. 이때, Ti막(23)은 상온 내지 500 ℃ 온도, 1 mtorr 내지 30 mtorr 압력 조건에서 10 sccm 내지 200 sccm의 Ar을 주입하고 1000 W 내지 4000 W의 DC 전력, 1000 W 내지 3000 W의 RF 전력을 인가하여 이온메탈플라즈마(ion metal plasma, IMP) 스퍼터링 방법으로 증착하며, 콘택홀 하부에서의 Ti막(23) 증착 두께가 30 Å 내지 200 Å이 되도록 한다. 산소확산방지막으로서 역할하는 TiAlN막(24)은 Ti막 증착 후 공기 노출없이 연속하여 TiAl 합금 타겟(target)을 이용한 스퍼터링 방법이나 화학기상증착방법으로 증착하며 콘택홀 하부에서의 TiAlN막(24) 증착두께는 10 Å 내지 200 Å이 되도록 한다.First, as shown in FIG. 2A, the interlayer insulating layer 22 covering the silicon substrate 20 on which the substructure of the transistor or the like is formed is selectively etched to expose the source or drain junction region 21 in the silicon substrate 20. A contact hole is formed, a cleaning process is performed, and then a Ti film 23 and a TiAlN film 24 are formed on the entire structure. At this time, the Ti film 23 injects 10 sccm to 200 sccm Ar at room temperature to 500 ° C. and 1 mtorr to 30 mtorr pressure, and supplies DC power of 1000 W to 4000 W and RF power of 1000 W to 3000 W. It is applied to deposit by an ion metal plasma (IMP) sputtering method, so that the thickness of the Ti film 23 deposited below the contact hole is 30 kPa to 200 kPa. The TiAlN film 24, which serves as an oxygen diffusion barrier, is deposited by sputtering or chemical vapor deposition using a TiAl alloy target after exposure of the Ti film without air exposure, and depositing the TiAlN film 24 under the contact hole. The thickness is 10 kPa to 200 kPa.

이어서 Ti막(23)과 TiAlN막(24) 계면에 질소를 이온주입하여, 도 2b에 도시한 바와 같이 5 Å 내지 30 Å 두께의 질소이온주입층(25)을 형성한다.Subsequently, nitrogen is ion-implanted at the interface of the Ti film 23 and the TiAlN film 24 to form a nitrogen ion injection layer 25 having a thickness of 5 Pa to 30 Pa as shown in FIG. 2B.

다음으로, RTP 등과 같은 급속열처리 공정을 N2분위기, 650 ℃ 내지 900 ℃ 온도 조건에서 10 초 내지 100 초 동안 실시하여 도 2c에 도시한 바와 같이 소오스 또는 드레인 접합영역(21) 상에 티타늄 실리사이드층(23A)을 형성함과 동시에 티타늄을 질화시킨다.Next, a rapid heat treatment process such as RTP is performed for 10 seconds to 100 seconds under an N 2 atmosphere and a temperature of 650 ° C. to 900 ° C., and a titanium silicide layer is formed on the source or drain junction region 21 as shown in FIG. 2C. 23A is formed and titanium is nitrided.

계속하여 전체 구조 상에 TiN 등의 장벽금속층(26)과 W 또는 Al 등의 금속막(27)을 증착한다. 이후 금속막(27) 및 장벽금속층(26)을 패터닝하여 금속배선을 형성한다.Subsequently, a barrier metal layer 26 such as TiN and a metal film 27 such as W or Al are deposited on the entire structure. Thereafter, the metal film 27 and the barrier metal layer 26 are patterned to form metal wiring.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 반도체 소자의 금속배선 형성 공정 중 티타늄막 상에 산소확산방지막을 적층하고 이들의 경계에 질소를 첨가함으로써, 실리사이드 형성을 위한 열처리 공정시 산소 침입에 의한 티타늄 실리사이드의 응집화를 억제함과 동시에 질소에 의한 티타늄의 질화가 진행시킨다. 이에 따라 금속배선 형성시 소오스 또는 드레인 접합영역의 손상되는 것을 방지하여 콘택저항 및 누설전류를 감소시키고, 소자의 신뢰성 향상 등 소자 특성의 안정화에 크게 기여할 것으로 기대된다.According to the present invention as described above, the oxygen diffusion prevention film is deposited on the titanium film during the metallization process of the semiconductor device, and nitrogen is added to the boundary thereof, thereby agglomeration of titanium silicide by oxygen intrusion during the heat treatment process for silicide formation. At the same time, nitriding of titanium by nitrogen proceeds. As a result, it is expected that the formation of the metal wiring will prevent damage to the source or drain junction region, thereby reducing contact resistance and leakage current, and greatly contributing to stabilization of device characteristics such as improved device reliability.

Claims (6)

반도체 소자 제조 방법에 있어서,In the semiconductor device manufacturing method, 실리콘 기판 상에 티타늄(Ti)막을 형성하는 제1 단계;Forming a titanium (Ti) film on the silicon substrate; 상기 티타늄막 상에 산소확산방지막을 형성하는 제2 단계;Forming an oxygen diffusion barrier on the titanium film; 상기 티타늄막과 상기 산소확산방지막 계면에 질소를 이온주입하는 제3 단계; 및A third step of ion implanting nitrogen at an interface between the titanium film and the oxygen diffusion prevention film; And 열처리 공정을 실시하여 티타늄 실리사이드를 형성함과 동시에 티타늄을 질화시키는 제4 단계The fourth step of performing a heat treatment process to form titanium silicide and simultaneously nitride titanium 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 반도체 소자 제조 방법에 있어서,In the semiconductor device manufacturing method, 트랜지스터 형성이 완료된 실리콘 기판 상부에 형성된 층간절연막을 선택적으로 식각하여 상기 실리콘 기판 내에 형성된 소오스 또는 드레인 접합을 노출시키는 콘택홀을 형성하고, 전체 구조 상에 티타늄(Ti)막을 형성하는 제1 단계;Selectively etching an interlayer insulating film formed on the silicon substrate on which the transistor formation is completed, forming a contact hole exposing a source or drain junction formed in the silicon substrate, and forming a titanium (Ti) film on the entire structure; 상기 티타늄막 상에 산소확산방지막을 형성하는 제2 단계;Forming an oxygen diffusion barrier on the titanium film; 상기 티타늄막과 상기 산소확산방지막 계면에 질소를 이온주입하는 제3 단계; 및A third step of ion implanting nitrogen at an interface between the titanium film and the oxygen diffusion prevention film; And 열처리 공정을 실시하여 티타늄 실리사이드를 형성함과 동시에 티타늄을 질화시키는 제4 단계The fourth step of performing a heat treatment process to form titanium silicide and simultaneously nitride titanium 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 산소확산방지막을 TiAlN으로 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.The oxygen diffusion preventing film is formed of TiAlN, characterized in that the semiconductor device manufacturing method. 제 3 항에 있어서,The method of claim 3, wherein 상기 열처리 공정은,The heat treatment step, 650 ℃ 내지 900 ℃ 온도에서 10 초 내지 100 초 동안 실시하는 것을 특징으로 하는 반도체 소자 제조 방법.10 to 100 seconds at a temperature of 650 ℃ to 900 ℃ manufacturing method of a semiconductor device. 제 3 항에 있어서,The method of claim 3, wherein 상기 제1 단계 후,After the first step, 공기중에 노출없이 상기 제2 단계를 실시하는 것을 특징으로 하는 반도체 소자 제조 방법.A method of manufacturing a semiconductor device, characterized in that the second step is carried out without exposure to air. 제 3 항에 있어서,The method of claim 3, wherein 상기 제4 단계 후,After the fourth step, 상기 산소확산방지막 상에 장벽금속층 및 배선 금속층을 형성하고, 패터닝을 실시하여 금속배선을 형성하는 제5 단계를 더 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.And forming a barrier metal layer and a wiring metal layer on the oxygen diffusion barrier, and patterning to form metal wiring.
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KR100971966B1 (en) * 2008-07-16 2010-07-22 주식회사 포스코 System And Method For Controlling Weight Of Turndish At Twin Roll Strip Caster
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KR101286239B1 (en) * 2007-08-24 2013-07-15 삼성전자주식회사 Structure of interconnection having a oxygen trap pattern in semiconductor device and method of fabricating the same
KR100971966B1 (en) * 2008-07-16 2010-07-22 주식회사 포스코 System And Method For Controlling Weight Of Turndish At Twin Roll Strip Caster

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