KR20010068499A - Fabricating method of capacitor - Google Patents

Fabricating method of capacitor Download PDF

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Publication number
KR20010068499A
KR20010068499A KR1020000000448A KR20000000448A KR20010068499A KR 20010068499 A KR20010068499 A KR 20010068499A KR 1020000000448 A KR1020000000448 A KR 1020000000448A KR 20000000448 A KR20000000448 A KR 20000000448A KR 20010068499 A KR20010068499 A KR 20010068499A
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South Korea
Prior art keywords
capacitor
forming
lower electrode
dielectric film
sequentially
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KR1020000000448A
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Korean (ko)
Inventor
강전진
최치선
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000000448A priority Critical patent/KR20010068499A/en
Publication of KR20010068499A publication Critical patent/KR20010068499A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A fabrication method of a capacitor is provided to be capable of suppressing the re-crystallization of polysilicon and the oxidation under a cell plug by heat treatment by implanting ions after forming Ta2O5 dielectric layers. CONSTITUTION: At first, an active area is defined by forming an isolation area(12) on a semiconductor substrate(11), and a lower structure is completed by sequentially forming word lines and bit lines(13). Then, lower electrodes(14) are formed and then silicon surface expansion layers(15) are formed on the lower electrodes(14). Next, Ta2O5 dielectric layer(16) and capacitor upper electrodes(17) are sequentially formed on the lower electrode. Finally, O2, N2 and N2O ions are implanted into the Ta2O5 dielectric layers.

Description

커패시터 제조방법{FABRICATING METHOD OF CAPACITOR}Capacitor Manufacturing Method {FABRICATING METHOD OF CAPACITOR}

본 발명은 커패시터 제조방법에 관한 것으로, 특히 Ta2O5유전막의 후처리에 이온주입을 적용하여 열처리를 실시함에 따른 폴리실리콘의 재결정 및 셀 플러그 하부에서 산화가 진행되는 것을 억제하기에 적당하도록 한 커패시터 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor, and in particular, to apply the ion implantation to the post-treatment of the Ta 2 O 5 dielectric film so as to be suitable for suppressing the re-crystallization of the polysilicon and the progress of oxidation under the cell plug. It relates to a capacitor manufacturing method.

종래의 커패시터 제조방법을 첨부한 도1a 내지 1d에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.If described in detail with reference to the cross-sectional view shown in Figure 1a to 1d attached to the conventional capacitor manufacturing method as follows.

먼저, 도1a에 도시한 바와같이 반도체기판(1) 상에 격리영역(2)을 형성하여 액티브영역을 정의하고, 순차적으로 워드라인(도시되지 않음) 및 비트라인(3)을 형성하여 하부 구조물을 완성한 다음 그 결과물 상에 폴리실리콘 재질의 커패시터의 하부전극(4)을 형성한다. 여기서, 커패시터의 하부전극(4)을 형성하기 위한 수순전개는 일반적으로 잘 알려진 공정을 통해 진행되므로, 상세한 설명을 생략한다.First, as shown in FIG. 1A, an isolation region 2 is formed on a semiconductor substrate 1 to define an active region, and a word line (not shown) and a bit line 3 are sequentially formed to form a lower structure. Then, the lower electrode 4 of the polysilicon capacitor is formed on the resultant. Here, since the procedure for forming the lower electrode 4 of the capacitor proceeds through a well-known process, a detailed description thereof will be omitted.

그리고, 도1b에 도시한 바와같이 상기 커패시터의 하부전극(4)이 형성된 결과물 상에 실리콘 표면확대 공정을 적용하여 실리콘 표면확대층(5)을 형성한다.As shown in FIG. 1B, a silicon surface enlargement layer 5 is formed by applying a silicon surface enlargement process on the resultant product in which the lower electrode 4 of the capacitor is formed.

그리고, 도1c에 도시한 바와같이 상기 실리콘 표면확대층(5)이 형성된 결과물의 상부전면에 Ta2O5유전막(6)을 형성한 다음 N2,O2열처리를 실시한다.As shown in FIG. 1C, a Ta 2 O 5 dielectric film 6 is formed on the upper surface of the resultant layer on which the silicon surface extension layer 5 is formed, followed by N 2 and O 2 heat treatment.

그리고, 도1d에 도시한 바와같이 Ta2O5유전막(6)이 형성된 결과물 상에 커패시터 상부전극(7)을 형성한다.As shown in FIG. 1D, the capacitor upper electrode 7 is formed on the resultant on which the Ta 2 O 5 dielectric film 6 is formed.

그러나, 상기한 바와같은 종래의 커패시터 제조방법은 유전막을 형성한 다음 실시되는 후속 열처리에 의해 표면확대된 폴리실리콘의 재결정이 진행되어 커패시턴스가 감소됨과 아울러 셀 플러그 하부에서 산화가 진행되는 것을 방지하기 위하여 산화방지 질화막 형성등의 불필요한 공정이 요구되는 문제점이 있었다.However, in the conventional capacitor manufacturing method as described above, the recrystallization of the surface-enhanced polysilicon proceeds by the subsequent heat treatment performed after the dielectric film is formed to reduce the capacitance and to prevent the oxidation from proceeding under the cell plug. There was a problem that an unnecessary process such as forming an antioxidant nitride film is required.

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 Ta2O5유전막의 후처리에 이온주입을 적용하여 열처리를 실시함에 따른 폴리실리콘의 재결정 및 셀 플러그 하부에서 산화가 진행되는 것을 억제할 수 있는 커패시터 제조방법을 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to recrystallize polysilicon and to lower cell plugs by applying ion implantation to post-treatment of Ta 2 O 5 dielectric film. It is to provide a capacitor manufacturing method that can suppress the progress of oxidation in the.

도1a 내지 도1d는 종래의 커패시터 제조방법을 보인 수순단면도.Figure 1a to 1d is a cross-sectional view showing a conventional capacitor manufacturing method.

도2a 내지 도2d는 본 발명의 일 실시예를 보인 수순단면도.2A to 2D are cross-sectional views showing an embodiment of the present invention.

***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***

11:반도체기판 12:격리영역11: semiconductor substrate 12: isolation area

13:비트라인 14:하부전극13: bit line 14: lower electrode

15:실리콘 표면확대층 16:Ta2O5유전막15: Silicon surface magnification layer 16: Ta 2 O 5 dielectric film

17:상부전극17: upper electrode

상기한 바와같은 본 발명의 목적을 달성하기 위한 커패시터 제조방법은 반도체기판 상에 격리영역을 형성하여 액티브영역을 정의하고, 순차적으로 워드라인 및 비트라인을 형성하여 하부 구조물을 완성하는 공정과; 상기 결과물 상에 커패시터의 하부전극을 형성한 다음 실리콘 표면확대 공정을 실시하는 공정과; 상기 표면확대된 커패시터 하부전극 상에 Ta2O5유전막과 상부전극을 순차적으로 실시하는 공정으로 이루어지는 커패시터 제조방법에 있어서, 상기 Ta2O5유전막을 형성한 다음 O2, N2및 N2O 이온주입을 실시하는 것을 특징으로 한다.Capacitor manufacturing method for achieving the object of the present invention as described above is to form an isolation region on the semiconductor substrate to define the active region, and sequentially forming a word line and a bit line to complete the lower structure; Forming a lower electrode of the capacitor on the resultant and then performing a silicon surface enlargement process; In the capacitor manufacturing method comprising the step of sequentially performing the Ta 2 O 5 dielectric film and the upper electrode on the surface-expanded capacitor lower electrode, forming the Ta 2 O 5 dielectric film and then O 2 , N 2 and N 2 O It is characterized by performing ion implantation.

상기한 바와같은 본 발명에 의한 커패시터 제조방법을 첨부한 도2a 내지도2d의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of the procedure of Figures 2a to 2d attached to the capacitor manufacturing method according to the present invention as an embodiment in detail as follows.

먼저, 도2a에 도시한 바와같이 반도체기판(11) 상에 격리영역(12)을 형성하여 액티브영역을 정의하고, 순차적으로 워드라인(도시되지 않음) 및 비트라인(13)을 형성하여 하부 구조물을 완성한 다음 그 결과물 상에 폴리실리콘 재질의 커패시터의 하부전극(14)을 형성한다. 여기서, 커패시터의 하부전극(14)을 형성하기 위한 수순전개는 종래와 동일하게 일반적으로 잘 알려진 공정을 통해 진행되므로, 상세한 설명을 생략한다.First, as shown in FIG. 2A, an isolation region 12 is formed on a semiconductor substrate 11 to define an active region, and word lines (not shown) and bit lines 13 are sequentially formed to form a lower structure. Then, the lower electrode 14 of the polysilicon capacitor is formed on the resultant. Here, since the procedure for forming the lower electrode 14 of the capacitor proceeds through a well-known process as in the prior art, a detailed description thereof will be omitted.

그리고, 도2b에 도시한 바와같이 상기 커패시터의 하부전극(14)이 형성된 결과물 상에 실리콘 표면확대 공정을 적용하여 실리콘 표면확대층(15)을 형성한다.As shown in FIG. 2B, the silicon surface enlargement layer 15 is formed by applying a silicon surface enlargement process on the resultant product in which the lower electrode 14 of the capacitor is formed.

그리고, 도2c에 도시한 바와같이 상기 실리콘 표면확대층(15)이 형성된 결과물 상에 Ta2O5유전막(16)을 형성한 다음 N2, O2및 N2O 이온주입을 실시한다.As shown in FIG. 2C, a Ta 2 O 5 dielectric layer 16 is formed on the resultant layer on which the silicon surface extension layer 15 is formed, and then N 2 , O 2, and N 2 O ions are implanted.

그리고, 도2d에 도시한 바와같이 Ta2O5유전막(16)이 형성된 결과물 상에 커패시터 상부전극(17)을 형성한다.As shown in FIG. 2D, the capacitor upper electrode 17 is formed on the resultant on which the Ta 2 O 5 dielectric film 16 is formed.

상기한 바와같은 본 발명에 의한 커패시터 제조방법은 Ta2O5유전막의 후처리에 이온주입을 적용하여 열처리를 실시함에 따른 폴리실리콘의 재결정 및 셀 플러그 하부에서 산화가 진행되는 것을 억제하여 커패시턴스를 확보함과 아울러 불필요한 산화방지 질화막 형성등의 공정을 생략하여 비용절감 및 공정단축에 기여하는 효과가 있다.Capacitor manufacturing method according to the present invention as described above to secure the capacitance by suppressing the re-crystallization of polysilicon and oxidation under the cell plug by applying ion implantation to the post-treatment of Ta 2 O 5 dielectric film. In addition, unnecessary steps such as the formation of an anti-oxidation nitride film can be omitted, thereby contributing to cost reduction and process shortening.

Claims (1)

반도체기판 상에 격리영역을 형성하여 액티브영역을 정의하고, 순차적으로 워드라인 및 비트라인을 형성하여 하부 구조물을 완성하는 공정과; 상기 결과물 상에 커패시터의 하부전극을 형성한 다음 실리콘 표면확대 공정을 실시하는 공정과; 상기 표면확대된 커패시터 하부전극 상에 Ta2O5유전막과 상부전극을 순차적으로 실시하는 공정으로 이루어지는 커패시터 제조방법에 있어서, 상기 Ta2O5유전막을 형성한 다음 O2, N2및 N2O 이온주입을 실시하는 것을 특징으로 하는 커패시터 제조방법.Forming an isolation region on the semiconductor substrate to define an active region, and sequentially forming a word line and a bit line to complete a lower structure; Forming a lower electrode of the capacitor on the resultant and then performing a silicon surface enlargement process; In the capacitor manufacturing method comprising the step of sequentially performing the Ta 2 O 5 dielectric film and the upper electrode on the surface-expanded capacitor lower electrode, forming the Ta 2 O 5 dielectric film and then O 2 , N 2 and N 2 O Capacitor manufacturing method characterized in that the ion implantation.
KR1020000000448A 2000-01-06 2000-01-06 Fabricating method of capacitor KR20010068499A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100728951B1 (en) * 2004-07-01 2007-06-15 주식회사 하이닉스반도체 Phase-change random access memory device and method for manufacturing the same
KR100892975B1 (en) * 2001-08-31 2009-04-10 엘피다 메모리, 아이엔씨. Semiconductor integrated circuit device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100892975B1 (en) * 2001-08-31 2009-04-10 엘피다 메모리, 아이엔씨. Semiconductor integrated circuit device and method of manufacturing the same
KR100728951B1 (en) * 2004-07-01 2007-06-15 주식회사 하이닉스반도체 Phase-change random access memory device and method for manufacturing the same

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