KR20020002902A - Method for fabricating capacitor of semiconductor memory device - Google Patents

Method for fabricating capacitor of semiconductor memory device Download PDF

Info

Publication number
KR20020002902A
KR20020002902A KR1020000037266A KR20000037266A KR20020002902A KR 20020002902 A KR20020002902 A KR 20020002902A KR 1020000037266 A KR1020000037266 A KR 1020000037266A KR 20000037266 A KR20000037266 A KR 20000037266A KR 20020002902 A KR20020002902 A KR 20020002902A
Authority
KR
South Korea
Prior art keywords
film
several
gas
forming
polysilicon
Prior art date
Application number
KR1020000037266A
Other languages
Korean (ko)
Inventor
김경민
박철환
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR1020000037266A priority Critical patent/KR20020002902A/en
Publication of KR20020002902A publication Critical patent/KR20020002902A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: A method for forming capacitor of a semiconductor device is provided to restrain a creation of a natural oxide layer at a surface of a polysilicon layer for a lower electrode by changing a property of a surface of the polysilicon layer. CONSTITUTION: An interlayer dielectric(21) is formed on a semiconductor substrate(20) having a transistor structure. A polysilicon layer for a lower electrode of a capacitor is formed on the interlayer dielectric(21). After doping the polysilicon layer using a PH3 plasma, a first nitride layer is formed on the doped polysilicon layer(22a). The nitride layer is acidified by plasma treating under NH3 gas. A second nitride layer is formed on the acidified nitride layer(23a). An oxide layer is formed on the second nitride layer. A polysilicon layer for an upper electrode is deposited and patterned.

Description

반도체소자의 커패시터 제조방법{Method for fabricating capacitor of semiconductor memory device}Method for fabricating capacitor of semiconductor memory device

본 발명은 반도체소자의 커패시터의 제조방법에 관한 것으로, 특히N/O(Nitride/Oxide) 커패시터의 제조시 하부전극 표면을 개질시켜 자연산화막이 생성되는 것을 방지하므로써, 커패시터의 전기적 특성을 개선시킨 반도체소자의 커패시터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device. In particular, a semiconductor having improved electrical characteristics of a capacitor by preventing a natural oxide film from being formed by modifying a lower electrode surface during the manufacture of an N / O (Nitride / Oxide) capacitor. It relates to a method for manufacturing a capacitor of the device.

최근 반도체기술의 진보에 따라, DRAM의 미세화와 고집적화가 급속히 진행되고 있는데, DRAM의 안정된 소자동작을 위해서는 커패시터의 커패시턴스를 충분히 확보하는 것이 중요시되고 있다.With the recent advances in semiconductor technology, DRAM miniaturization and high integration are rapidly progressing. In order to stabilize DRAM operation of the DRAM, it is important to secure sufficient capacitance of the capacitor.

도 1a 및 도 1b는 종래의 커패시터 제조방법을 나타낸 단면도로서, N/O막을 커패시터의 유전층으로 사용하는 기술에 관한 것이다.1A and 1B are cross-sectional views illustrating a conventional capacitor manufacturing method and related to a technique of using an N / O film as a dielectric layer of a capacitor.

도 1에 도시된 바와 같이, 먼저 반도체기판(10) 위에 게이트전극 및 소오스/드레인 영역 등의 반도체소자를 형성한 후, 이 전체구조물 위에 층간절연막(11)을 형성한 다음 평탄화공정을 수행한다.As shown in FIG. 1, first, a semiconductor device such as a gate electrode and a source / drain region is formed on a semiconductor substrate 10, and then an interlayer insulating film 11 is formed on the entire structure, and then a planarization process is performed.

그 다음, 상기 층간절연막(11) 위에 커패시터의 하부전극으로서 폴리실리콘막(12)을 형성한 후, 세정공정을 실시한다.Next, a polysilicon film 12 is formed on the interlayer insulating film 11 as a lower electrode of the capacitor, and then a cleaning process is performed.

그 다음, PH3를 도우핑한 질화막(13)을 상기 폴리실리콘막(12) 위에 형성하고, 상기 질화막(13) 위에 산화막(14)을 형성하며, 상기 산화막(14) 위에 상부전극으로서의 폴리실리콘막(15)를 형성한다.Then, a nitride film 13 doped with PH 3 is formed on the polysilicon film 12, an oxide film 14 is formed on the nitride film 13, and polysilicon as an upper electrode on the oxide film 14 is formed. The film 15 is formed.

그 다음, 상기 폴리실리콘막(12), 질화막(13), 산화막(14) 및 폴리실리콘막(15)을 패터닝하여, 도 1b에 도시된 바와 같이, 하부전극용의 폴리실리콘막(12a), 질화막(13a), 산화막(14a) 및 상부전극용의 폴리실리콘막(15a)으로 이루어진 커패시터를 형성한다.Next, the polysilicon film 12, the nitride film 13, the oxide film 14 and the polysilicon film 15 are patterned, and as shown in FIG. 1B, the polysilicon film 12a for the lower electrode, A capacitor composed of a nitride film 13a, an oxide film 14a, and a polysilicon film 15a for the upper electrode is formed.

그러나, 전술한 종래의 커패시터 제조방법에 의하면, 하부전극용 폴리실리콘막을 형성한 후 세정공정에서 폴리실리콘막의 표면에 산화막(SiO2)이 형성되어, 유효산화막(Tox : effective oxide thickness)을 증가시켜 커패시턴스를 감소시킬 뿐만 아니라 저항을 증가시켜 전기적 특성에도 악영향을 주었다.However, according to the above-described conventional capacitor manufacturing method, after forming the polysilicon film for the lower electrode, an oxide film (SiO 2 ) is formed on the surface of the polysilicon film in the cleaning process, thereby increasing the effective oxide thickness (Tox) In addition to reducing capacitance, the resistance was also adversely affected by electrical properties.

따라서, N/O 커패시터의 제조시 Tox를 낮추고 커패시턴스를 증가시킬 수 있는 제조방법이 요구되고 있었다.Therefore, there is a demand for a manufacturing method capable of lowering Tox and increasing capacitance in manufacturing N / O capacitors.

따라서, 본 발명은 이와 같은 종래의 문제점을 해결하기 위해 안출한 것으로서, 본 발명의 목적은 N/O 커패시터의 제조시 하부전극 표면을 개질시켜 자연산화막이 생성되는 것을 방지하므로써, 커패시터의 전기적 특성을 개선시킨 반도체소자의 커패시터의 제조방법을 제공하는 것이다.Accordingly, the present invention has been made to solve such a conventional problem, an object of the present invention is to modify the lower electrode surface during the manufacturing of the N / O capacitor to prevent the formation of a natural oxide film, thereby improving the electrical characteristics of the capacitor It is to provide an improved method for manufacturing a capacitor of a semiconductor device.

본 발명의 다른 목적은 커패시터의 하부전극 형성 후 세정공정을 실시하지 않고 한 장비에서 인-시튜(in-situ)로 후속공정을 수행하여 Tox를 낮추고 커패시턴스를 증가시킬 수 있는 반도체소자의 커패시터의 제조방법을 제공하는 것이다.Another object of the present invention is to manufacture a capacitor of a semiconductor device capable of lowering Tox and increasing capacitance by performing a subsequent process in-situ in one equipment without performing a cleaning process after forming a lower electrode of the capacitor. To provide a way.

본 발명의 또다른 목적은 하부전극용 폴리실리콘막의 표면을 NH3에 플라즈마 처리하여 질화막을 형성시키고, 이어서 NH3개스와 O2개스에 플라즈마 처리하여 1차로 진행한 질화막을 산 질화막화 시켜 하부전극용 폴리실리콘막을 개질시키므로써, N/O 커패시터의 전기적 특성을 개선할 수 있는 반도체소자의 커패시터의 제조방법을 제공하는 것이다.Another object of the present invention is to form a nitride film by plasma treatment of the surface of the polysilicon film for the lower electrode to NH 3 , and then to the nitridation of the nitride film advanced to the first electrode by plasma treatment of NH 3 gas and O 2 gas to the lower electrode By modifying the polysilicon film for use, it is to provide a method of manufacturing a capacitor of a semiconductor device that can improve the electrical characteristics of the N / O capacitor.

도 1a 및 도 1b는 종래의 커패시터 제조방법을 나타낸 단면도이다.1A and 1B are cross-sectional views illustrating a conventional capacitor manufacturing method.

도 2a 내지 도 2f는 본 발명에 따른 커패시터 제조방법을 나타낸 단면도이다.2A to 2F are cross-sectional views showing a capacitor manufacturing method according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10,20: 반도체기판 11,21: 소스/드레인영역10,20: semiconductor substrate 11,21: source / drain regions

12,22: 층간절연막 12,15,22,26: 폴리실리콘막12,22: interlayer insulating film 12,15,22,26: polysilicon film

13,23,24: 질화막 23a: 산 질화막13,23,24: nitride film 23a: acid nitride film

14,25: 산화막14,25: oxide film

이와 같은 목적을 달성하기 위한 본 발명은 트랜지스터가 형성된 반도체기판 위에 층간절연막을 형성하는 단계; 상기 층간절연막 위에 하부전극용의 폴리실리콘막을 형성하는 단계; 상기 하부전극용의 폴리실리콘막을 도우핑하는 단계; 상기 도우핑된 폴리실리콘막 위에 제1질화막을 형성하는 단계; 상기 제1질화막을 산 질화막화 시키는 단계; 상기 산 질화막 위에 제2질화막을 형성하는 단계; 상기 제2질화막 위에 산화막을 형성하는 단계; 및 상기 산화막 위에 상부전극용 폴리실리콘막을 증착한 후 패터닝하는 단계로 구성되는 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a semiconductor substrate on which a transistor is formed; Forming a polysilicon film for a lower electrode on the interlayer insulating film; Doping the polysilicon film for the lower electrode; Forming a first nitride film on the doped polysilicon film; Oxidizing the first nitride film; Forming a second nitride film on the oxynitride film; Forming an oxide film on the second nitride film; And patterning after depositing a polysilicon film for the upper electrode on the oxide film.

이하, 본 발명의 실시예를 첨부 도면을 참조하여 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

먼저, 도 2a 내지 도 2f는 본 발명에 따른 커패시터 제조방법을 나타낸 단면도이다.First, FIGS. 2A to 2F are cross-sectional views illustrating a method of manufacturing a capacitor according to the present invention.

도 2a를 참조하면, 반도체기판(20) 위에 게이트전극 및 소오스/드레인 영역을 포함한 트랜지스터를 형성한 후, 이 전체구조물 위에 층간절연막(21)을 형성한 다음 평탄화공정을 수행한다. 그 다음, 상기 층간절연막(21) 위에 커패시터의 하부전극용의 폴리실리콘막(22)을 형성한다.Referring to FIG. 2A, after a transistor including a gate electrode and a source / drain region is formed on the semiconductor substrate 20, an interlayer insulating film 21 is formed on the entire structure, and then a planarization process is performed. Next, a polysilicon film 22 for the lower electrode of the capacitor is formed on the interlayer insulating film 21.

그 다음, 상기 폴리실리콘막(22)의 표면을 개질하기 위하여 PH3플라즈마 도우핑(plasma doping) 처리를 실시하고, 이어서 NH3플라즈마 처리를 실시하여, 질화막(23)을 형성한다.Then, in order to modify the surface of the polysilicon film 22, a PH 3 plasma doping treatment is performed, followed by an NH 3 plasma treatment to form a nitride film 23.

이때, 상기 PH3플라즈마 도우핑 처리공정의 경우에는, PH3개스의 양을 수sccm~수백sccm으로 하고, 수Watt~수백Watt의 고주파 전력(Power)을 인가하며, 압력을 0.1torr~2torr로 유지하고, 처리시간은 수초~수백초로 한다. 또한, 상기 NH3플라즈마 처리공정의 경우에는, NH3개스의 양을 수sccm~수백sccm으로 하고, 전력과 압력 및 처리시간의 조건은 전술한 PH3플라즈마 도우핑 처리공정과 동일하다.In this case, in the case of the PH 3 plasma doping treatment, the amount of PH 3 gas is several sccm to several hundred sccm, a few Watts to several hundred Watts is applied, and the pressure is 0.1torr to 2torr. The processing time is several seconds to several hundred seconds. In the case of the NH 3 plasma treatment step, the amount of NH 3 gas is several sccm to several hundred sccm, and the conditions of power, pressure, and treatment time are the same as the above-described PH 3 plasma doping treatment step.

여기서, 1차로 NH3에 플라즈마 처리하여 상기 질화막(23)을 증착하는 이유는 NH3+ O2개스에 플라즈마 처리했을 때 폴리실리콘과 O2가 반응하여 산화막(SiO2)이 형성되는 것을 억제하기 위한 것이다.The reason why the nitride film 23 is deposited by plasma treatment to NH 3 is primarily to prevent the formation of an oxide film (SiO 2 ) by reacting polysilicon and O 2 when plasma treatment is performed on NH 3 + O 2 gas. It is for.

그 다음, 도 2b에 도시된 바와 같이, NH3+ O2개스에 플라즈마 처리를 실시하여, 상기 질화막(23)을 산 질화막(23a)화 시켜 상기 하부전극용 폴리실리콘막(22)을 개질시킨다. 이때, NH3개스와 O2개스의 양을 수sccm~수백sccm으로 하고, 수Watt~수백Watt의 고주파 전력(Power)을 인가하며, 압력을 0.1torr~2torr로 유지하고, 처리시간은 수초~수백초로 한다. 여기서, 상기 산 질화막(23a)을 형성하기 위하여 O2개스 대신에 N2O 개스를 사용할 수도 있다.Next, as shown in FIG. 2B, a plasma treatment is performed on the NH 3 + O 2 gas to form the oxynitride film 23a to modify the lower silicon polysilicon film 22. . At this time, the amount of NH 3 gas and O 2 gas is a few sccm ~ hundreds sccm, high frequency power of several Watts-several hundred Watts is applied, the pressure is maintained at 0.1torr ~ 2torr, the processing time is several seconds ~ Let hundreds of seconds. Here, in order to form the oxynitride film 23a, N 2 O gas may be used instead of O 2 gas.

전술한 바와 같이 플라즈자 처리에 의하여 형성된 산 질화막(23a)의 두께는 한계가 있기 때문에, 도 2c에 도시된 바와 ??이, NH3+ DCS(Di-Chloro Silene) 분위기에서 퍼니스 어닐링(fuunace annealing)을 실시하여, 질화막(24)을 상기 산 질화막(23a) 위에 형성한다.As described above, since the thickness of the oxynitride film 23a formed by the plasma treatment is limited, as shown in FIG. 2C, the furnace annealing is performed in an NH 3 + Di-Chloro Silene (DCS) atmosphere. The nitride film 24 is formed on the oxynitride film 23a.

그 다음, 도 2d에 도시된 바와 같이, H2+ O2분위기에서 퍼니스 어닐링을 실시하여 상기 질화막(24) 위에 산화막(25)을 형성한다.Next, as shown in FIG. 2D, the furnace annealing is performed in an H 2 + O 2 atmosphere to form an oxide film 25 on the nitride film 24.

그 다음, 도 2e 및 도 2f에 도시된 바와 같이, 상기 산화막(25) 위에 상부전극용 폴리실리콘막(26)을 증착한 후 패터닝하여, 하부전극용 폴리실리콘막(22a), 산 질화막(23b), 질화막(24a), 산화막(25a) 및 상부전극용 폴리실리콘막(26a)으로 이루어진 커패시터를 형성한다.2E and 2F, the polysilicon film 26 for the upper electrode is deposited on the oxide film 25 and then patterned to form the polysilicon film 22a and the oxynitride film 23b for the lower electrode. ), A capacitor formed of a nitride film 24a, an oxide film 25a, and a polysilicon film 26a for the upper electrode.

이상에서 살펴 본 바와 같이, 본 발명은 N/O 커패시터의 형성시 하부전극용 폴리실로콘막의 형성 후 폴리실로콘막의 표면에 자연산화막의 생성을 억제하기 위하여 세정공정을 실시하지 않음으로써 Tox값을 낮출 수 있다.As described above, the present invention does not perform the cleaning process to suppress the formation of the natural oxide film on the surface of the polysilicon film after the formation of the polysilicon film for the lower electrode when the N / O capacitor is formed Tox value Can be lowered.

또한, 본 발명은 하부전극용 폴리실리콘막의 표면을 NH3에 플라즈마 처리하여 질화막을 형성시키고, 이어서 NH3개스와 O2개스에 플라즈마 처리하여 1차로 진행한 질화막을 산 질화막화 시켜 하부전극용 폴리실리콘막을 개질시키므로써, N/O 커패시터의 전기적 특성을 개선할 수 있다.In addition, in the present invention, the surface of the polysilicon film for the lower electrode is plasma-treated with NH 3 to form a nitride film, and then, the plasma is treated with NH 3 gas and O 2 gas to oxynitride the nitride film which has been advanced first, and the poly for the lower electrode By modifying the silicon film, it is possible to improve the electrical characteristics of the N / O capacitor.

전술한 바와 같은 본 발명은 MPS(Metal stable PolySilicon)가 형성된 평판 및 실린더구조에 적용할 수 있다.As described above, the present invention can be applied to a plate and a cylinder structure in which metal stable polysilicon (MPS) is formed.

Claims (8)

트랜지스터가 형성된 반도체기판 위에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate on which the transistor is formed; 상기 층간절연막 위에 하부전극용의 폴리실리콘막을 형성하는 단계;Forming a polysilicon film for a lower electrode on the interlayer insulating film; 상기 하부전극용의 폴리실리콘막을 도우핑하는 단계;Doping the polysilicon film for the lower electrode; 상기 도우핑된 폴리실리콘막 위에 제1질화막을 형성하는 단계;Forming a first nitride film on the doped polysilicon film; 상기 제1질화막을 산 질화막화 시키는 단계;Oxidizing the first nitride film; 상기 산 질화막 위에 제2질화막을 형성하는 단계;Forming a second nitride film on the oxynitride film; 상기 제2질화막 위에 산화막을 형성하는 단계; 및Forming an oxide film on the second nitride film; And 상기 산화막 위에 상부전극용 폴리실리콘막을 증착한 후 패터닝하는 단계로 구성되는 반도체소자의 커패시터 제조방법.And depositing a polysilicon film for the upper electrode on the oxide film and then patterning the capacitor. 제1항에 있어서, 상기 하부전극용 폴리실리콘막을 도우핑하는 단계는 PH3플라즈마 처리를 실시하되, PH3개스의 양을 수sccm~수백sccm으로 하고, 수Watt~수백Watt의 고주파 전력(Power)을 인가하며, 압력을 0.1torr~2torr로 유지하고, 처리시간은 수초~수백초로 하는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, wherein the doping of the polysilicon film for the lower electrode is performed by performing a PH 3 plasma treatment, wherein the amount of PH 3 gas is set to several sccm to several hundred sccm, and a high frequency power of several Watts to several hundred Watts. ) Is applied, the pressure is maintained at 0.1torr ~ 2torr, and the processing time is several seconds to several hundred seconds. 제1항에 있어서, 상기 제1질화막은 NH3에 플라즈마 처리하여 형성하되, NH3개스의 양을 수sccm~수백sccm으로 하고, 수Watt~수백Watt의 고주파 전력(Power)을 인가하며, 압력을 0.1torr~2torr로 유지하고, 처리시간은 수초~수백초로 하는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, wherein said first nitride film is NH, but is formed by plasma treatment in the third, the amount of NH 3 gas to be sccm ~ several hundred sccm, and the number and applying a high-frequency power (Power) of the Watt ~ hundreds of Watt, the pressure Is maintained at 0.1torr to 2torr, and the processing time is several seconds to several hundreds of seconds. 제1항에 있어서, 상기 산 질화막은 NH3+ O2개스에 플라즈마 처리하여 형성하되, NH3개스와 O2개스의 양을 수sccm~수백sccm으로 하고, 수Watt~수백Watt의 고주파 전력을 인가하며, 압력을 0.1torr~2torr로 유지하고, 처리시간은 수초~수백초로 하는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The oxynitride film is formed by plasma treatment of NH 3 + O 2 gas, wherein the amount of NH 3 gas and O 2 gas is several sccm to several hundred sccm, and the high frequency power of several Watts to several hundred Watts is applied. And a pressure of 0.1torr to 2torr, and a processing time of several seconds to several hundreds of seconds. 제4항에 있어서, 상기 산 질화막을 형성하기 위하여 O2개스 대신에 N2O 개스를 사용하는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 4, wherein N 2 O gas is used instead of O 2 gas to form the oxynitride film. 제1항에 있어서, 상기 제2질화막은 NH3+ DCS 분위기에서 퍼니스 어닐링을 실시하여 형성되는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, wherein the second nitride film is formed by performing furnace annealing in an NH 3 + DCS atmosphere. 제1항에 있어서, 상기 산화막은 H2+ O2분위기에서 퍼니스 어닐링을 실시하여 형성되는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, wherein the oxide film is formed by furnace annealing in an H 2 + O 2 atmosphere. 제1항에 있어서, 상기 폴리실리콘막을 도우핑하는 단계, 상기 제1질화막을 형성하는 단계 그리고 상기 산 질화막을 형성하는 단계는 인-시튜로 진행하는 것을 특징으로 하는 반도체소자의 커패시터 제조방법.The method of claim 1, wherein the doping of the polysilicon layer, the forming of the first nitride layer, and the forming of the oxynitride layer are performed in-situ.
KR1020000037266A 2000-06-30 2000-06-30 Method for fabricating capacitor of semiconductor memory device KR20020002902A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000037266A KR20020002902A (en) 2000-06-30 2000-06-30 Method for fabricating capacitor of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000037266A KR20020002902A (en) 2000-06-30 2000-06-30 Method for fabricating capacitor of semiconductor memory device

Publications (1)

Publication Number Publication Date
KR20020002902A true KR20020002902A (en) 2002-01-10

Family

ID=19675500

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000037266A KR20020002902A (en) 2000-06-30 2000-06-30 Method for fabricating capacitor of semiconductor memory device

Country Status (1)

Country Link
KR (1) KR20020002902A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100479237B1 (en) * 2002-05-24 2005-03-30 주성엔지니어링(주) Method for fabricating lower electrode of capacitor used in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100479237B1 (en) * 2002-05-24 2005-03-30 주성엔지니어링(주) Method for fabricating lower electrode of capacitor used in semiconductor device

Similar Documents

Publication Publication Date Title
KR100618815B1 (en) Semiconductor device having different gate dielectric layers and method for manufacturing the same
JP3451943B2 (en) Method for forming capacitor of semiconductor device
US7361572B2 (en) STI liner modification method
US6207544B1 (en) Method of fabricating ultra thin nitride spacers and device incorporating same
KR100414948B1 (en) Method of forming a capacitor in a semiconductor device
KR20020002902A (en) Method for fabricating capacitor of semiconductor memory device
KR100400253B1 (en) Method for forming the thin film transistor of semiconductor device
KR100336574B1 (en) Method of manufacturing semiconductor device
KR20050060268A (en) Method for fabrication of transistor having sonos structure
KR20040059931A (en) Method for fabricating dual gate oxide of semiconductor device
KR100335773B1 (en) Method of manufacturing a capacitor in a semiconductor device
KR20020045266A (en) Method for forming a dielectric of capacitor
KR100237022B1 (en) Forming method of dielectric film of capacitor
KR20000039607A (en) Method for fabricating capacitor of semiconductor device
KR100311178B1 (en) A method of fabricating a capacitor
KR100511919B1 (en) Capacitor of semiconductor device and method for fabricating the same
KR100434708B1 (en) Method for forming capacitor of semiconductor device
KR100235973B1 (en) Manufacturing method of capacitor in the semiconductor device
KR100691941B1 (en) Method of manufacturing a capacitor in semiconductor device
KR20010068499A (en) Fabricating method of capacitor
KR20040037568A (en) Transistor in a semiconductor device and a method of manufacturing the same
KR100398569B1 (en) Method for manufactruing capacitor in semiconductor device
KR20050010673A (en) Semiconductor device capable of preventing degradation due to hard mask on gate electrode and method of forming the same
KR20000042480A (en) Method for fabricating capacitor of semiconductor device
KR20020002639A (en) A method for forming a storage node of a semiconductor device

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid