KR20010059031A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20010059031A KR20010059031A KR1019990066409A KR19990066409A KR20010059031A KR 20010059031 A KR20010059031 A KR 20010059031A KR 1019990066409 A KR1019990066409 A KR 1019990066409A KR 19990066409 A KR19990066409 A KR 19990066409A KR 20010059031 A KR20010059031 A KR 20010059031A
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- metal layer
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910008807 WSiN Inorganic materials 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 239000007789 gas Substances 0.000 claims abstract description 11
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 35
- 229910052721 tungsten Inorganic materials 0.000 claims description 35
- 239000010937 tungsten Substances 0.000 claims description 35
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000006117 anti-reflective coating Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910018999 CoSi2 Inorganic materials 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- -1 nitrogen ion Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 NH3 및 N2 가스의 이온주입 공정으로 베리어(Barrier)층인 WSiN층을 형성하여 소자의 열안정성, 신뢰성 및 수율을 향상시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a WSiN layer, which is a barrier layer, is formed by ion implantation of NH 3 and N 2 gases to improve thermal stability, reliability, and yield of the device. will be.
반도체 소자의 게이트 전극은 낮은 저항의 금속물을 채택하는 것이 RC 지연시간의 감소를 위해 필수적이다.As the gate electrode of the semiconductor device, it is necessary to adopt a low resistance metal material for reducing the RC delay time.
최근의 기가(Giga)급 소자에서는 TiSi2 게이트 전극, CoSi2 게이트 전극 및 텅스텐(W) 게이트 전극 등이 사용하고 있다.In recent Giga class devices, TiSi2 gate electrodes, CoSi2 gate electrodes, tungsten (W) gate electrodes, and the like are used.
상기 고집적 소자의 텅스텐 게이트 전극은 열처리 공정에 따라 텅스텐과 그 하부층인 다결정 실리콘층과의 반응에 의한 텅스텐 실리사이드(Silicide)층이 형성된다.In the tungsten gate electrode of the highly integrated device, a tungsten silicide layer is formed by a reaction between tungsten and a polycrystalline silicon layer below the tungsten gate electrode.
상기 텅스텐 실리사이드층의 형성으로 상기 텅스텐 게이트 전극의 저항이 텅스텐층 저항 보다 증가하는 현상이 발생한다.The formation of the tungsten silicide layer causes the resistance of the tungsten gate electrode to increase than that of the tungsten layer.
그 결과 열처리 공정에 따라 상기 텅스텐층과 다결정 실리콘층과의 반응을 방지하기 위해 상기 텅스텐층과 다결정 실리콘층 사이에 베리어층을 형성하고 있다.As a result, a barrier layer is formed between the tungsten layer and the polycrystalline silicon layer in order to prevent the reaction between the tungsten layer and the polycrystalline silicon layer according to the heat treatment process.
종래 기술에 따른 반도체 소자 중 텅스텐 게이트 전극의 제조 방법은 도 1a에서와 같이, 반도체 기판(31)상에 열 산화 공정으로 게이트 산화막(32)을 성장시킨 후, 상기 게이트 산화막(32)상에 비정질 실리콘층(33), WNX막(11) 및 텅스텐층(34)을 형성한다.In the method of manufacturing a tungsten gate electrode of the semiconductor device according to the related art, after the gate oxide film 32 is grown on the semiconductor substrate 31 by a thermal oxidation process, as shown in FIG. 1A, an amorphous phase is formed on the gate oxide film 32. The silicon layer 33, the WNX film 11, and the tungsten layer 34 are formed.
도 1b에서와 같이, 상기 텅스텐층(34)상에 하드 마스크(Hard Mask)층(35), 에이알시(Anti Reflective Coating:ARC)층(36) 및 감광막을 순차적으로 형성한 후, 상기 감광막을 게이트 전극 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.As shown in FIG. 1B, a hard mask layer 35, an Anti Reflective Coating (ARC) layer 36, and a photoresist layer are sequentially formed on the tungsten layer 34, and then the photoresist layer is formed. Is selectively exposed and developed so as to remain only at the site where the gate electrode is to be formed.
그리고, 상기 선택적으로 노광 및 현상된 감광막을 마스크로 상기 ARC층(36), 하드 마스크층(35), 텅스텐층(34), WNX막(11) 및 비정질 실리콘층(33)을 선택적으로 식각하여 게이트 전극을 형성한 후, 상기 감광막을 제거한다.The ARC layer 36, the hard mask layer 35, the tungsten layer 34, the WNX layer 11, and the amorphous silicon layer 33 are selectively etched using the selectively exposed and developed photoresist layer as a mask. After the gate electrode is formed, the photosensitive film is removed.
그러나 종래의 반도체 소자의 제조 방법은 비정질 실리콘층과 베리어(Barrier)층인 WNX막 그리고 텅스텐(W)층의 적층 구조의 게이트 전극을 형성하기 때문에 WNX막과 텅스텐층에 의해 게이트 산화막에 스트레스(Stress)가 가해지므로 게이트 산화막의 특성이 저하된다는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device, since a gate electrode having a stacked structure of an amorphous silicon layer, a barrier layer, a WNX film, and a tungsten (W) layer is formed, a stress is applied to the gate oxide film by the WNX film and the tungsten layer. There is a problem that the characteristics of the gate oxide film are deteriorated because is added.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 비정질 실리콘층과 텅스텐층 사이에 NH3 및 N2 가스의 이온주입 공정을 사용하여 베리어층인 WSiN층을 형성하므로 게이트 산화막의 특성 저하를 방지하는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and the semiconductor device prevents the gate oxide film from deteriorating because the WSiN layer, which is a barrier layer, is formed between the amorphous silicon layer and the tungsten layer by using an ion implantation process of NH 3 and N 2 gases. Its purpose is to provide a process for the preparation.
도 1a와 도 1b는 종래 기술에 따른 반도체 소자 중 텅스텐 게이트 전극의 제조 방법을 나타낸 공정 단면도1A and 1B are cross-sectional views illustrating a method of manufacturing a tungsten gate electrode in a semiconductor device according to the related art.
도 2a 내지 도 2d는 본 발명의 실시 예에 따른 반도체 소자 중 텅스텐 게이트 전극의 제조 방법을 나타낸 공정 단면도2A to 2D are cross-sectional views illustrating a method of manufacturing a tungsten gate electrode in a semiconductor device according to an embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
31: 반도체 기판 32: 게이트 산화막31 semiconductor substrate 32 gate oxide film
33: 비정질 실리콘층 34: 텅스텐층33: amorphous silicon layer 34: tungsten layer
35: 하드 마스크층 36: ARC층35: hard mask layer 36: ARC layer
37: WSiN층37: WSiN layer
본 발명의 반도체 소자의 제조 방법은 기판상에 게이트 절연막, 도전층 및 금속층을 형성하는 단계, 상기 도전층과 금속층 사이에 질소(N) 성분이 피크가 되도록 전면에 NH3 및 N2 가스를 이온주입하는 단계, 상기 금속층상에 하드 마스크층을 형성하는 단계, 상기 하드 마스크층, 금속층 및 도전층을 선택적으로 식각하여 게이트 전극을 형성하는 단계 및 전면을 열치리 하여 상기 도전층과 금속층 사이에 주입된 질소(N) 성분에 의해 실리사이드층 형성 방지층인 베리어층을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the method of manufacturing a semiconductor device of the present invention, forming a gate insulating film, a conductive layer, and a metal layer on a substrate, and ion-implanting NH3 and N2 gas on the entire surface such that a nitrogen (N) component becomes a peak between the conductive layer and the metal layer. Forming a hard mask layer on the metal layer, selectively etching the hard mask layer, the metal layer, and the conductive layer to form a gate electrode and treating the entire surface with nitrogen injected between the conductive layer and the metal layer It characterized by comprising the step of forming a barrier layer which is a silicide layer formation prevention layer by the (N) component.
상기와 같은 본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.
도 2a 내지 도 2d는 본 발명의 실시 예에 따른 반도체 소자 중 텅스텐 게이트 전극의 제조 방법을 나타낸 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a tungsten gate electrode in a semiconductor device according to an embodiment of the present invention.
본 발명의 실시 예에 따른 반도체 소자 중 텅스텐 게이트 전극의 제조 방법은 도 2a에서와 같이, 반도체 기판(31)상에 열 산화 공정으로 게이트 산화막(32)을 성장시킨 후, 상기 게이트 산화막(32)상에 비정질 실리콘층(33)과 텅스텐층(34)을 형성한다.In the method of manufacturing a tungsten gate electrode of the semiconductor device according to the embodiment of the present invention, as shown in FIG. 2A, after the gate oxide layer 32 is grown on the semiconductor substrate 31 by a thermal oxidation process, the gate oxide layer 32 is formed. An amorphous silicon layer 33 and a tungsten layer 34 are formed on it.
여기서, 상기 텅스텐층(34)을 아르곤(Ar) 스퍼터링(Sputtering) 공정에 의해 형성한다.Here, the tungsten layer 34 is formed by an argon (Ar) sputtering process.
도 2b에서와 같이, 상기 비정질 실리콘층(33)과 텅스텐층(34) 사이에 질소(N) 성분이 피크(Peak)가 되도록 농도 및 에너지를 조절한 후 NH3 및 N2 가스를 전면에 이온주입한다.As shown in FIG. 2B, after the concentration and energy are adjusted between the amorphous silicon layer 33 and the tungsten layer 34 so that the nitrogen (N) component becomes a peak, ion implantation of NH 3 and N 2 gases is performed on the entire surface. .
도 2c에서와 같이, 상기 텅스텐층(34)상에 하드 마스크층(35), ARC층(36) 및 감광막을 순차적으로 형성한 후, 상기 감광막을 게이트 전극 형성될 부위에만 남도록 선택적으로 노광 및 현상한다.As shown in FIG. 2C, after the hard mask layer 35, the ARC layer 36, and the photoresist layer are sequentially formed on the tungsten layer 34, the photoresist layer is selectively exposed and developed so that the photoresist layer remains only at the portion where the gate electrode is to be formed. do.
그리고, 상기 선택적으로 노광 및 현상된 감광막을 마스크로 상기 ARC층(36), 하드 마스크층(35), 텅스텐층(34) 및 비정질 실리콘층(33)을 선택적으로 식각하여 게이트 전극을 형성한 후, 상기 감광막을 제거한다.The ARC layer 36, the hard mask layer 35, the tungsten layer 34, and the amorphous silicon layer 33 are selectively etched using the selectively exposed and developed photoresist as a mask to form a gate electrode. Remove the photosensitive film.
도 2d에서와 같이, 상기 게이트 전극이 형성된 전면에 열처리 공정을 하여 상기 비정질 실리콘층(33)과 텅스텐층(34) 사이에 주입된 질소 이온 그리고 텅스텐과 실리콘을 반응시켜 상기 비정질 실리콘층(33)과 텅스텐층(34) 사이에 베리어층인 WSiN층(37)을 형성한다.As shown in FIG. 2D, a heat treatment process is performed on the entire surface where the gate electrode is formed to react nitrogen ion implanted between the amorphous silicon layer 33 and the tungsten layer 34, and tungsten and silicon to react with the amorphous silicon layer 33. And a WSiN layer 37 as a barrier layer is formed between the tungsten layer 34 and the tungsten layer 34.
여기서, 상기 WSiN층(37)은 상기 비정질 실리콘층(33)과 텅스텐층(34)의 반응으로 인한 텅스텐 실리사이드층의 형성을 방지하는 역할을 한다.Here, the WSiN layer 37 serves to prevent the formation of a tungsten silicide layer due to the reaction between the amorphous silicon layer 33 and the tungsten layer 34.
본 발명의 반도체 소자의 제조 방법은 NH3 및 N2 가스의 이온주입 공정을 사용하여 비정질 실리콘층과 텅스텐층 사이에 베리어층인 WSiN층을 형성하므로, 상기 WSiN층에 의해 텅스텐 실리사이드층의 형성을 방지하여 게이트 전극의 저항을 감소시키고 또한 상기 WSiN층의 형성 공정시 사용한 NH3 및 N2 가스의 이온주입 공정에 의해 상기 텅스텐층이 비정질화되어 균일한 게이트 식각 프로파일(Profile)을 갖으며 NH3 및 N2 가스의 이온주입 공정에 의해 WSiN층을 형성하므로 게이트 산화막에 가해지는 스트레스를 완화시켜 소자의 열안정성, 신뢰성 및 수율을 향상시키는 효과가 있다.In the method of manufacturing a semiconductor device of the present invention, a WSiN layer, which is a barrier layer, is formed between an amorphous silicon layer and a tungsten layer by using an ion implantation process of NH 3 and N 2 gases, thereby preventing formation of a tungsten silicide layer by the WSiN layer. The tungsten layer is amorphous by reducing the resistance of the gate electrode and ion implantation of NH3 and N2 gas used in the WSiN layer formation process, and thus has a uniform gate etch profile and ion of NH3 and N2 gas. Since the WSiN layer is formed by the implantation process, the stress applied to the gate oxide film is alleviated, thereby improving the thermal stability, reliability, and yield of the device.
Claims (5)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100443243B1 (en) * | 2001-12-29 | 2004-08-04 | 주식회사 하이닉스반도체 | Method for forming a metal interconnection line |
| WO2014158448A1 (en) * | 2013-03-14 | 2014-10-02 | Applied Materials, Inc. | Enhancing uv compatibility of low k barrier film |
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1999
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100443243B1 (en) * | 2001-12-29 | 2004-08-04 | 주식회사 하이닉스반도체 | Method for forming a metal interconnection line |
| WO2014158448A1 (en) * | 2013-03-14 | 2014-10-02 | Applied Materials, Inc. | Enhancing uv compatibility of low k barrier film |
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