KR20010020984A - 반도체장치 및 반도체장치의 제조방법 - Google Patents
반도체장치 및 반도체장치의 제조방법 Download PDFInfo
- Publication number
- KR20010020984A KR20010020984A KR1020000032414A KR20000032414A KR20010020984A KR 20010020984 A KR20010020984 A KR 20010020984A KR 1020000032414 A KR1020000032414 A KR 1020000032414A KR 20000032414 A KR20000032414 A KR 20000032414A KR 20010020984 A KR20010020984 A KR 20010020984A
- Authority
- KR
- South Korea
- Prior art keywords
- memory cell
- gate
- peripheral circuit
- circuit portion
- cell portion
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 49
- 238000000034 method Methods 0.000 title claims description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 230000015654 memory Effects 0.000 claims abstract description 72
- 230000002093 peripheral effect Effects 0.000 claims abstract description 57
- 125000006850 spacer group Chemical group 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 6
- 230000009977 dual effect Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 69
- 239000010410 layer Substances 0.000 description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000005684 electric field Effects 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
Claims (8)
- 동일 반도체 기판상에 형성된 메모리 셀부와 주변 회로부에 각각 복수의 트랜지스터를 갖고 있는 반도체장치의 제조방법에 있어서,(a) 주변 회로부에 트랜지스터의 게이트를 형성하는 단계;(b) 게이트 측벽에 제1 사이드월 스페이서를 형성하는 단계;(c) 메모리 셀부에 트랜지스터의 게이트를 형성하는 단계;(d) 주변 회로부 및 메모리 셀부에 게이트측벽에 제2 사이드월 스페이서를 형성하는 것에 의해 주변 회로부의 트랜지스터에는 이중 사이드월 스페이서를, 메모리 셀부의 트랜지스터에는 단일 사이드월 스페이서를 각각 형성하는 단계; 및(e) 주변 회로부 및 메모리 셀부에 소스/드레인 영역을 형성함으로써 복수의 트랜지스터를 형성하는 단계;를 포함하는 반도체장치의 제조방법.
- 제1항에 있어서, 상기 제2 사이드월 스페이서를 실리콘 질화막으로 형성하는 방법.
- 제2항에 있어서, 상기 제2 사이드월 스페이서를 500 내지 1000 Å 폭으로 형성하는 방법.
- 제1항에 있어서, 단계(a) 전에 플로팅 게이트용 재료막 및 절연막을 순차적으로 형성하고 또 단계(c)에서 메모리 셀부에 트랜지스터의 게이트를 플래쉬 메모리 셀 구조로 형성하는 방법.
- 제1항에 있어서, 상기 제1 사이드월 스페이서를 실리콘 산화막, 실리콘 질화막 또는 이들의 적층으로 형성하는 방법.
- 제5항에 있어서, 상기 제1 사이드월 스페이서를 1000 내지 1500Å 폭으로 형성하는 방법.
- 동일 반도체 기판상의 메모리 셀부와 주변 회로부에 각각 복수의 트랜지스터를 포함하고, 상기 메모리 셀부의 트랜지스터의 게이트는 실리콘 질화막으로된 제1 사이드월 스페이서를 갖고 있고, 상기 주변 회로부의 트랜지스터의 게이트는 외측에 실리콘 질화막으로된 제1 사이드월 스페이서가 형성된 이중 사이드월 스페이서를 갖고 있는 것을 특징으로 하는 반도체장치.
- 제7항에 있어서, 상기 메모리 셀부와 주변 회로부가 LDD, DDD, 비대칭 LDD 또는 DDD 구조의 소스/드레인 영역을 갖는 것을 특징으로 하는 반도체장치.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11-219969 | 1999-08-03 | ||
JP21996999A JP3516616B2 (ja) | 1999-08-03 | 1999-08-03 | 半導体装置の製造方法及び半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010020984A true KR20010020984A (ko) | 2001-03-15 |
KR100402703B1 KR100402703B1 (ko) | 2003-10-22 |
Family
ID=16743875
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2000-0032414A KR100402703B1 (ko) | 1999-08-03 | 2000-06-13 | 반도체장치 및 반도체장치의 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6380584B1 (ko) |
JP (1) | JP3516616B2 (ko) |
KR (1) | KR100402703B1 (ko) |
TW (1) | TW456028B (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100766233B1 (ko) * | 2006-05-15 | 2007-10-10 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자 및 그의 제조 방법 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7012008B1 (en) * | 2000-03-17 | 2006-03-14 | Advanced Micro Devices, Inc. | Dual spacer process for non-volatile memory devices |
JP2002050767A (ja) * | 2000-08-04 | 2002-02-15 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US20020123180A1 (en) * | 2001-03-01 | 2002-09-05 | Peter Rabkin | Transistor and memory cell with ultra-short gate feature and method of fabricating the same |
US6472271B1 (en) * | 2001-05-24 | 2002-10-29 | Macronix International Co., Ltd. | Planarization method of memory unit of flash memory |
TW538507B (en) * | 2002-04-26 | 2003-06-21 | Macronix Int Co Ltd | Structure of a mask ROM device |
US6770932B2 (en) * | 2002-07-10 | 2004-08-03 | Kabushiki Kaisha Toshiba | Semiconductor memory device having a memory region and a peripheral region, and a manufacturing method thereof |
KR100509828B1 (ko) * | 2002-09-19 | 2005-08-24 | 동부아남반도체 주식회사 | 스플리트형 플래시 메모리 셀의 게이트 전극 및 그 제조방법 |
EP1816675A1 (en) * | 2006-02-03 | 2007-08-08 | STMicroelectronics S.r.l. | Manufacturing process of spacers for high-voltage transistors in an EEPROM device |
KR100816755B1 (ko) * | 2006-10-19 | 2008-03-25 | 삼성전자주식회사 | 플래시 메모리 장치 및 그 제조방법 |
JP6518485B2 (ja) | 2015-03-30 | 2019-05-22 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5208472A (en) * | 1988-05-13 | 1993-05-04 | Industrial Technology Research Institute | Double spacer salicide MOS device and method |
JPH01292863A (ja) | 1988-05-20 | 1989-11-27 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH05102428A (ja) * | 1991-10-07 | 1993-04-23 | Sony Corp | 半導体メモリ装置及びその製造方法 |
WO1994014198A1 (en) * | 1992-12-11 | 1994-06-23 | Intel Corporation | A mos transistor having a composite gate electrode and method of fabrication |
JP3238556B2 (ja) * | 1993-12-06 | 2001-12-17 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JPH098307A (ja) * | 1995-06-26 | 1997-01-10 | Matsushita Electron Corp | 半導体装置 |
KR100214519B1 (ko) * | 1996-11-14 | 1999-08-02 | 구본준 | 반도체소자 제조방법 |
-
1999
- 1999-08-03 JP JP21996999A patent/JP3516616B2/ja not_active Expired - Fee Related
-
2000
- 2000-06-05 US US09/587,187 patent/US6380584B1/en not_active Expired - Lifetime
- 2000-06-08 TW TW089111142A patent/TW456028B/zh not_active IP Right Cessation
- 2000-06-13 KR KR10-2000-0032414A patent/KR100402703B1/ko active IP Right Grant
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100766233B1 (ko) * | 2006-05-15 | 2007-10-10 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자 및 그의 제조 방법 |
US7573089B2 (en) | 2006-05-15 | 2009-08-11 | Hynix Semiconductor Inc. | Non-volatile memory device |
US7851311B2 (en) | 2006-05-15 | 2010-12-14 | Hynix Semiconductor Inc. | Method of manufacturing non-volatile memory device |
Also Published As
Publication number | Publication date |
---|---|
KR100402703B1 (ko) | 2003-10-22 |
TW456028B (en) | 2001-09-21 |
JP3516616B2 (ja) | 2004-04-05 |
JP2001044393A (ja) | 2001-02-16 |
US6380584B1 (en) | 2002-04-30 |
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