KR20010003424A - Method of forming a metal line in a semiconductor device - Google Patents
Method of forming a metal line in a semiconductor device Download PDFInfo
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- KR20010003424A KR20010003424A KR1019990023717A KR19990023717A KR20010003424A KR 20010003424 A KR20010003424 A KR 20010003424A KR 1019990023717 A KR1019990023717 A KR 1019990023717A KR 19990023717 A KR19990023717 A KR 19990023717A KR 20010003424 A KR20010003424 A KR 20010003424A
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- semiconductor device
- metal wiring
- metal compound
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- metal
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000002184 metal Substances 0.000 title claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 150000002736 metal compounds Chemical class 0.000 claims abstract description 25
- 239000011248 coating agent Substances 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims abstract description 11
- 239000003960 organic solvent Substances 0.000 claims abstract description 5
- 238000011065 in-situ storage Methods 0.000 claims description 5
- 238000011066 ex-situ storage Methods 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 230000008021 deposition Effects 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 150000002739 metals Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 13
- 235000012431 wafers Nutrition 0.000 description 13
- 238000000151 deposition Methods 0.000 description 10
- 239000010936 titanium Substances 0.000 description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 239000000376 reactant Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 235000019441 ethanol Nutrition 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000007086 side reaction Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 특히 유기물 금속 화합물을 이용하여 빠르고 간단한 방법으로 티타늄 배선을 형성할 수 있는 반도체 소자의 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device capable of forming a titanium wiring by a quick and simple method using an organic metal compound.
반도체 소자에서 금속배선은 소자의 동작을 위한 신호의 공급원으로 작용한다. 이러한 금속배선을 형성하기 위한 공정으로 여러가지 방법이 이용되고 있으며, 대표적으로 PVD, CVD 등의 방식이 사용되고 있다. PVD 방식에서는 스퍼터 방식을 가장 많이 사용하고 있으며, CVD 방식에서는 PECVD, MOCVD 등의 방법을 사용하고 있다. 그러나 이러한 방법들은 증착 반응기를 만들고 반응 및 증착 조건을 형성하는데 많은 비용이 들게 된다.In semiconductor devices, metallization serves as a source of signal for the operation of the device. Various methods are used as a process for forming such a metal wiring, and typically, methods such as PVD and CVD are used. In the PVD method, the sputter method is most used, and in the CVD method, methods such as PECVD and MOCVD are used. However, these methods are expensive to build deposition reactors and to form reaction and deposition conditions.
기존의 공정 중에서 스퍼터 방식은 콘택 홀의 크기가 작아질수록 그 매립에 한계를 갖고 있으며, 증착하게 되는 웨이퍼 레벨에서의 균일도를 얻는 것이 매우 어렵다. 특히, 반도체 소자가 고집적화에 됨에 따라 웨이퍼 크기가 계속 증가하고 있는 추세이며, 이와 같은 큰 크기를 갖는 웨이퍼의 균일성을 제어하는 것이 어려운 문제가 있다. 또한, 증착 장비의 구성을 위해서는 고진공을 필요로 하는 등 많은 비용을 필요로 하게 된다.In the conventional process, the sputtering method has a limitation in filling the smaller contact hole, and it is very difficult to obtain uniformity at the wafer level to be deposited. In particular, as semiconductor devices become more integrated, wafer sizes continue to increase, and it is difficult to control uniformity of wafers having such a large size. In addition, the configuration of the deposition equipment requires a high cost, such as requiring a high vacuum.
반면, CVD 방식에 의해 금속 배선을 증착하는 경우에는 콘택의 미세화에 따른 문제를 쉽게 해결할 수 있으며, 많은 부분에서 실용적으로 사용하고 있다. 그러나 CVD 방식에 의한 금속배선 증착은 화학반응에 의해 이루어지기 때문에 필요없는 부반응물이 형성되어 이 부반응물이 금속배선 내에 존재함에 따라 배선의 저항값이 다르게 나타날 수 있고, 챔버의 구성에 대미지(damage)를 형성할 수 있으며, 이 부반응물이 챔버 내에서 반응을 일으켜 증착 챔버 외벽에 증착되는 현상이 나타나 매 주기 세정해야 하는 등의 문제점이 있다. 또한, CVD에 의한 금속배선 증착은 접착층에 따라 증착할 수 있는 배선이 한계가 있으며, 공정 단계가 증가하는 단점이 있다. 또한,On the other hand, in the case of depositing a metal wiring by the CVD method, the problem caused by the miniaturization of the contact can be easily solved, and it is practically used in many parts. However, since the deposition of metal wires by the CVD method is performed by chemical reaction, unnecessary side reactants are formed, and the resistance values of the wires may appear differently as the side reactants exist in the metal wires, and damage to the configuration of the chamber may occur. ), And the sub-reactant reacts in the chamber, causing deposition on the outer wall of the deposition chamber, which causes cleaning every cycle. In addition, the metal wiring deposition by CVD has a limitation that the wiring that can be deposited according to the adhesive layer is limited, the process step is increased. Also,
이와 같이, 종래의 금속배선 증착 공정 시에는 그 챔버 구성이 매우 복잡하고, 증착 조건이 매우 다양하여 완전한 공정을 만들기 어려우며, 실제 금속 증착 공정에서 균일도가 저하되는 문제점이 있다.As described above, in the conventional metallization deposition process, the chamber configuration is very complicated, the deposition conditions are very diverse, and it is difficult to make a complete process, and there is a problem in that uniformity is lowered in the actual metal deposition process.
따라서, 본 발명은 웨이퍼를 회전시키면서 유기물 금속 화합물을 코팅하고 이를 큐링하여 티타늄 배선을 형성하므로써 비용을 증가시키지 않고 간단한 공정으로 미세 콘택의 매립 특성을 향상시킬 수 있는 반도체 소자의 금속배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a method for forming a metal wiring of a semiconductor device that can improve the buried characteristics of the fine contact in a simple process without increasing the cost by coating the organic metal compound and curing the titanium while forming a titanium wiring while rotating the wafer. Its purpose is to.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속배선 형성 방법은 절연막이 형성된 웨이퍼를 회전시키면서 상기 절연막 상에 유기물 금속 화합물을 코팅하는 단계; 상기 유기물 금속 화합물이 코팅된 웨이퍼를 큐링하여 상기 유기물 금속 화합물의 유기 용매를 제거하고, 이로 인하여 순수한 금속만으로 이루어진 금속배선층이 형성되는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method comprising: coating an organic metal compound on the insulating film while rotating the wafer on which the insulating film is formed; Curing the wafer coated with the organic metal compound to remove the organic solvent of the organic metal compound, thereby forming a metal wiring layer consisting of pure metal only.
도 1a 내지 1c는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.1A to 1C are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 절연막11 semiconductor substrate 12 insulating film
13A : 유기물 금속 화합물층 13 : 금속배선층13A: organic metal compound layer 13: metal wiring layer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1a 내지 1c는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1C are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.
도 1a에 도시된 바와 같이, 하부구조가 형성된 반도체 기판(11) 상에 절연막(12)을 형성한다. 이후 웨이퍼 즉, 반도체 기판(11)이 급속한 속도로 회전하는 상태에서, 절연막(12) 상에 유기물 금속 화합물(organo metallic compound)층(13A)을 코팅한다. 여기에서, 웨이퍼의 회전 속도는 500 내지 10000RPM으로 하고, 유기물 금속 화합물층(13)으로는 액상 형태의 (C2H5O)4Ti 화합물층이 이용된다. 유기물 금속 화합물층(13A)은 웨이퍼가 회전하는 상태에서 코팅되기 때문에 웨이퍼 전면에 걸쳐 균일하게 코팅될 수 있다.As shown in FIG. 1A, an insulating film 12 is formed on a semiconductor substrate 11 on which a lower structure is formed. Subsequently, in a state in which the wafer, that is, the semiconductor substrate 11 is rotated at a rapid speed, the organic metal compound layer 13A is coated on the insulating film 12. Here, the rotational speed of the wafer is 500 to 10000 RPM, and the (C 2 H 5 O) 4 Ti compound layer in liquid form is used as the organic metal compound layer 13. Since the organic metal compound layer 13A is coated while the wafer is rotating, the organic metal compound layer 13A may be uniformly coated over the entire surface of the wafer.
도 1b는 상대적으로 낮은 온도에서 큐링 공정 또는 베이킹 공정을 실시하여 유기물 금속 화합물층(13A)에서 유기용매를 제거시키는 과정을 나타내는 소자의 단면도이다. 본 발명의 큐링 공정은 100 내지 1000℃의 온도조건 및 수소 분위기 하에서 이루어지며 주로 RTP 방법을 이용한다. 큐링 공정시 RTP 방법을 이용할 경우 열처리 온도는 450 내지 700℃로 한다. 이때 유기물 금속 화합물층(13A)과 수소와의 반응은 다음의 [화학식 1]과 같다.FIG. 1B is a cross-sectional view of a device illustrating a process of removing an organic solvent from the organic metal compound layer 13A by performing a curing process or a baking process at a relatively low temperature. Curing process of the present invention is carried out under a temperature condition and hydrogen atmosphere of 100 to 1000 ℃ and mainly uses the RTP method. When the RTP method is used in the curing process, the heat treatment temperature is 450 to 700 ° C. At this time, the reaction between the organic metal compound layer 13A and hydrogen is shown in the following [Formula 1].
유기물 금속 화합물층(13A)의 코팅 및 큐링은 인-시투 또는 익스-시투 방법으로 진행할 수 있으며, 인-시투로 진행할 경우에는 코팅 후 큐링 시간을 더욱 단축시킬 수 있어 스루우풋(throughput)을 향상시킬 수 있고, 익스-시투로 진행할 경우에는 반응물로부터 웨이퍼 및 반응기를 보호할 수 있다.Coating and curing of the organic metal compound layer 13A may be performed in-situ or ex-situ, and in-situ may further shorten the curing time after coating, thereby improving throughput. And proceeding with ex-situ can protect the wafer and reactor from the reactants.
도 1c는 (C2H5O)4Ti와 수소의 반응으로 유기물 금속 화합물층(13A)으로부터 유기용매인 4C2H5OH가 제거되고, 티타늄만으로된 순수한 금속배선층(13)이 형성된 상태를 나타내는 소자의 단면도이다. 이러한 반응의 부반응물로 나타나는 에틸 알콜은 휘발성이기 때문에 용이하게 제거할 수 있다.FIG. 1C illustrates a state in which the organic solvent 4C 2 H 5 OH is removed from the organic metal compound layer 13A by the reaction of (C 2 H 5 O) 4 Ti and hydrogen, and a pure metal wiring layer 13 made of titanium is formed. A cross-sectional view of the device. Ethyl alcohol, which appears as a side reaction of this reaction, is volatile and can be easily removed.
상술한 바와 같이 본 발명은 웨이퍼를 회전시키면서 유기물 금속 화합물을 코팅하고 이를 큐링하여 티타늄 배선을 형성하므로써 균일한 증착 특성을 갖는 금속배선을 형성할 수 있다. 본 발명에서는 코팅과 큐링을 분리하여 진행하기 때문에 챔버의 오염으로 인한 세정문제를 해결할 수 있으며, 반응에 의해 나타나는 부반응물 역시 전혀 위해가 없는 에틸알콜이기 때문에 부반응물에 대한 반응기 체계에 아무런 문제가 없다. 또한, 본 발명은 대기압 상태에서 금속배선 증착 공정을 진행할 수 있어 고진공을 요하는 챔버가 필요하지 않고, 코팅과 큐링을 진행하는데 인-시투, 익스-시투의 방법을 모두 사용할 수 있으므로 장비의 구성이 매우 다양한 특성을 얻을 수 있으며, 인-시투로 진행하는 경우에는 코팅 후 큐링하는 시간을 최대한 단축시킬 수 있다. 그리고 티타늄을 사용하는 메탈 게이트에서는 평탄화 측면에서 더욱 유리하며, 유기물 금속 화합물이 미세한 콘택에 액상 형태로 코팅되기 때문에 콘택 매립 특성을 향상시킬 수 있다.As described above, the present invention may form a metal wiring having uniform deposition characteristics by coating an organic metal compound and rotating the wafer while forming a titanium wiring by rotating the wafer. In the present invention, since the coating and the curing proceed separately, the cleaning problem due to the contamination of the chamber can be solved, and the reaction system does not have any problem in the reactor system for the side reaction because the reaction product is also ethyl alcohol without any harm. . In addition, the present invention can proceed the metallization deposition process at atmospheric pressure, does not require a chamber requiring a high vacuum, and can be used both in-situ, ex-situ to proceed with coating and curing, so the configuration of equipment A wide variety of properties can be obtained, and when in-situ can minimize the time to cure after coating as much as possible. In addition, the metal gate using titanium is more advantageous in terms of planarization, and since the organic metal compound is coated in a liquid form in a liquid form, it is possible to improve contact filling properties.
Claims (7)
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| KR10-1999-0023717A KR100368304B1 (en) | 1999-06-23 | 1999-06-23 | Method of forming a metal line in a semiconductor device |
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| KR20030002625A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | a method for manufacturing of semiconductor device |
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|---|---|---|---|---|
| JPS6414938A (en) * | 1987-07-08 | 1989-01-19 | Nec Corp | Forming method of multilayered interconnection |
| JPH0555132A (en) * | 1991-08-28 | 1993-03-05 | Hitachi Ltd | Formation of wiring member |
| KR0148327B1 (en) * | 1995-04-18 | 1998-12-01 | 김주용 | Formation method of metal wiring in semiconductor device |
-
1999
- 1999-06-23 KR KR10-1999-0023717A patent/KR100368304B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030002625A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | a method for manufacturing of semiconductor device |
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| Publication number | Publication date |
|---|---|
| KR100368304B1 (en) | 2003-01-24 |
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