KR100341849B1 - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR100341849B1 KR100341849B1 KR1019990048752A KR19990048752A KR100341849B1 KR 100341849 B1 KR100341849 B1 KR 100341849B1 KR 1019990048752 A KR1019990048752 A KR 1019990048752A KR 19990048752 A KR19990048752 A KR 19990048752A KR 100341849 B1 KR100341849 B1 KR 100341849B1
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- copper
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- plasma processing
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 45
- 239000002184 metal Substances 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000010949 copper Substances 0.000 claims abstract description 56
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 51
- 229910052802 copper Inorganic materials 0.000 claims abstract description 51
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 238000009832 plasma treatment Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 55
- 238000005229 chemical vapour deposition Methods 0.000 claims description 26
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 20
- 239000007789 gas Substances 0.000 claims description 19
- 239000001257 hydrogen Substances 0.000 claims description 17
- 229910052739 hydrogen Inorganic materials 0.000 claims description 17
- 239000010409 thin film Substances 0.000 claims description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 12
- 238000003672 processing method Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 11
- 229910052786 argon Inorganic materials 0.000 claims description 10
- 238000005240 physical vapour deposition Methods 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 8
- 239000010408 film Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- 150000002431 hydrogen Chemical class 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 229910052734 helium Inorganic materials 0.000 claims description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000012691 Cu precursor Substances 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 239000012159 carrier gas Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 239000002243 precursor Substances 0.000 claims description 2
- 239000007921 spray Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000006200 vaporizer Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims 1
- 238000007740 vapor deposition Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
Abstract
본 발명은 금속 배선 재료로 구리를 사용하는 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 물리기상증착(PVD)법이나 전기도금(Electroplating)법으로 매립하기 어려운 초 미세 배선 구조에 구리를 화학기상증착(CVD)법으로 매립할 때, 구리의 접착(adhesion) 특성을 향상시키기 위하여, 초 미세 다마신 패턴에 배리어 금속층(barrier metal layer)을 형성한 후, 배리어 금속층에 존재하는 미세 산화물(oxide), 질화물(nitride) 등과 같은 계면 불순물(interfacial impurity)을 리모트 플라즈마 및/또는 챔버 플라즈마 처리하여 제거하는 금속 배선 형성 방법에 관하여 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices using copper as a metal wiring material. In order to improve the adhesion characteristics of copper when buried by the (CVD) method, after forming a barrier metal layer on the ultra fine damascene pattern, fine oxides present in the barrier metal layer, A method for forming metal wirings in which interfacial impurity such as nitride and the like is removed by remote plasma and / or chamber plasma treatment is described.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 화학기상증착(CVD)법에 의한 구리의 접착(adhesion) 특성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices capable of improving the adhesion characteristics of copper by chemical vapor deposition (CVD).
일반적으로, 반도체 소자에서 금속 배선을 형성함에 있어서, 구리 박막은 알루미늄 박막에 비해 녹는점이 높아 전기적 이동(electro-migration; EM)에 대한 저항이 커서 반도체 소자의 신뢰성을 향상시키고, 비저항 약 1.7μΩcm정도로 낮아 신호전달 속도를 증가시킬 수 있다. 따라서 구리 박막의 형성 기술은 고속 소자 및 고집적 소자에서 필요한 기술이다.In general, in forming a metal wiring in a semiconductor device, a copper thin film has a higher melting point than an aluminum thin film, and thus has a high resistance to electro-migration (EM), thereby improving reliability of the semiconductor device and having a specific resistance of about 1.7 μmcm. Low to increase the signaling rate. Therefore, the technology of forming a copper thin film is a necessary technology for high speed devices and high integration devices.
차세대 반도체 소자의 급격한 고성능화 추세로 인하여 콘택 크기의 감소와 급격한 단차(aspect ratio)의 증가로 인하여 우수한 단차 피복성(Step coverage) 및 우수한 콘택 매립이 요구된다. 현재의 추세는 타이타늄(Ti) 박막 증착 후 알루미늄(A1) 박막을 물리기상증착(PVD)법 및 화학기상증착(CVD)법이 사용되는 방법과, 구리의 확산 방지막으로 물리기상증착법으로 증착된 Ta, TaN을 이용한 전기도금법으로 구리(Cu)를 증착하는 방법이 적용되고 있는 추세이다. 그러나, 전자의 경우는 알루미늄 박막이 구리 박막보다 저항이 높아서 차세대 고성능 반도체 소자의 적용에는 문제점을 가지고 있으며, 후자의 경우 콘택 크기의 급격한 감소 및 단차의 증가는 전기도금법을 이용한 구리 증착이 한계에 부딪치는 문제점이 있으며, 따라서 알루미늄 배선 및 전기 도금을 이용한 구리 배선의 적용은 차세대 반도체 소자에 많은 문제점을 가지고 있다.Due to the rapid performance trend of next-generation semiconductor devices, excellent step coverage and excellent contact filling are required due to a decrease in contact size and a sudden increase in aspect ratio. Current trends include physical vapor deposition (PVD) and chemical vapor deposition (CVD) of aluminum (A1) thin films after deposition of titanium (Ti) thin films, and Ta deposited by physical vapor deposition as a copper diffusion barrier. , A method of depositing copper (Cu) by an electroplating method using TaN is being applied. However, in the former case, the aluminum thin film has higher resistance than the copper thin film, and thus there is a problem in the application of the next-generation high-performance semiconductor device. There is a problem, and therefore, the application of copper wiring using aluminum wiring and electroplating has many problems in next-generation semiconductor devices.
또한, 초 미세 배선 구조에 화학기상증착법으로 구리를 매립할 경우 현재까지 가장 큰 문제점으로 지적되고 있는 것은 화학기상증착법에 의한 박막의 접착(adhesion) 문제이다. 접착이 매우 취약할 경우에는 후속 공정에 상당한 문제점을 야기시켜 구리 금속 배선의 불량을 초래하게 된다. 따라서, 화학기상증착법으로 형성된 구리 박막이 반도체 소자에 적용되기 위해서는 접착 문제가 개선되어야 한다. 통상적으로 구리층을 형성하기 전에 Ta, TaN, TiN과 같은 물질을 사용하여 배리어 메탈층(barrier metal layer)을 형성하고 있는데, 이때 역시 접착이 큰 문제로 지적되고 있다.In addition, when the copper is buried in the ultra fine wiring structure by the chemical vapor deposition method, the biggest problem so far is pointed out the problem of adhesion of the thin film by the chemical vapor deposition method. If the adhesion is very weak, it will cause significant problems in subsequent processes, resulting in poor copper metal wiring. Therefore, in order for the copper thin film formed by chemical vapor deposition to be applied to a semiconductor device, the adhesion problem should be improved. Typically, before forming the copper layer, a barrier metal layer is formed using a material such as Ta, TaN, TiN, and at this time, the adhesion is also pointed out as a big problem.
구리층의 접착 문제를 개선하기 위하여 여러 가지 방법이 시도되고 있는데, 다음의 방법들이 주로 시도되고 있다. 첫째, 화학기상증착법으로 구리층을 형성한 후에 300 내지 400℃ 정도에서 열처리하는 방법인데, 이 방법은 계면 불순물(interfacial impurity)을 감소시키는 효과는 있으나, 생산성( throughput)이 문제가 되며, 또한 저유전율 유전체(low k dielectrics)를 사용할 경우에 인터그레이션(integration) 문제를 야기하기 때문에 적적한 해결책(optimal solution)이 아니다. 둘째, 화학기상증착법으로 구리층을 증착하기 전에 첨가제를 첨가하는 방법이나, 전구체(precursor)를 새롭게 개발하는 방법이 있는데, 이 방법들은 뚜렷한 개선책이 되지 못하고 있다. 최근에는 화학기상증착법으로 구리층을 증착하기 전에 물리기상증착법으로 구리 시드층을 먼저 형성한 다음 화학기상증착법으로 구리층을 형성하는 방법이 하나의 개선책으로 제시되고 있다.Various methods have been tried to improve the adhesion problem of the copper layer, and the following methods have been mainly attempted. First, after the copper layer is formed by chemical vapor deposition, the heat treatment is performed at about 300 to 400 ° C. This method has the effect of reducing interfacial impurity, but the productivity is a problem. The use of low k dielectrics is not an optimal solution because it causes integration problems. Second, there is a method of adding an additive before depositing a copper layer by chemical vapor deposition, or a method of newly developing a precursor, which is not a clear improvement. Recently, a method of forming a copper seed layer by physical vapor deposition and then forming a copper layer by chemical vapor deposition has been proposed as an improvement before depositing a copper layer by chemical vapor deposition.
따라서, 본 발명은 화학기상증착법만으로 구리층을 형성하되, 구리의 접착 특성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of forming a copper layer using only chemical vapor deposition, and improving the adhesion characteristics of copper.
이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 하지층이 형성된 기판 상에 층간 절연막을 형성하는 단계; 상기 층간 절연막에 다마신 패턴을 형성한 후, 클리닝 공정을 실시하는 단계; 상기 다마신 패턴을 포함한 상기 층간 절연막 표면을 따라 배리어 금속층을 형성하는 단계; 상기 배리어 금속층의 표면에 생성된 계면 불순물층을 제거하기 위하여 플라즈마 처리하는 단계; 화학기상증착법으로 상기 다마신 패턴을 구리로 매립시켜 구리층을 형성하는 단계; 및 상기 구리층을 수소환원 열처리한 후에 화학적 기계적 연마 처리하여 구리 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.Method for forming a metal wiring of the semiconductor device according to the present invention for achieving this object comprises the steps of forming an interlayer insulating film on a substrate on which the base layer is formed; Forming a damascene pattern on the interlayer insulating film, and then performing a cleaning process; Forming a barrier metal layer along a surface of the interlayer insulating film including the damascene pattern; Plasma treatment to remove the interfacial impurity layer formed on the surface of the barrier metal layer; Filling the damascene pattern with copper by chemical vapor deposition to form a copper layer; And chemically polishing the copper layer after the hydrogen reduction heat treatment to form a copper metal wire.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 기판 12: 하지층11: substrate 12: base layer
13: 층간 절연막 14: 다마신 패턴13: interlayer insulating film 14: damascene pattern
15: 배리어 금속층 16: 계면 불순물층15: barrier metal layer 16: interface impurity layer
17: 구리층 170: 구리 금속 배선17: copper layer 170: copper metal wiring
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of devices for describing a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11) 상에 하지층(12)을 형성한다. 하지층(12)을 포함한 전체 구조상에 층간 절연막(13)을 형성한 후, 다마신 식각(damascene etch) 공정으로 비아 콘택홀 및 트렌치로 이루어진 다마신 패턴(14)을 형성한다. 클리닝(cleaning) 공정을 실시한 후, 다마신 패턴(14)을 포함한 층간 절연막(13) 표면을 따라 배리어 금속층(16)을 형성한다. 배리어 금속층(16)의 표면에는 공정 및 외부 요인에 의해 산화물(oxide), 질화물(nitride) 등과 같은 불순물로 된 계면 불순물층(16)이 생성된다.Referring to FIG. 1A, an underlayer 12 is formed on a substrate 11 on which various elements for forming a semiconductor device are formed. After the interlayer insulating layer 13 is formed on the entire structure including the base layer 12, a damascene pattern 14 including a via contact hole and a trench is formed by a damascene etch process. After the cleaning process, the barrier metal layer 16 is formed along the surface of the interlayer insulating film 13 including the damascene pattern 14. On the surface of the barrier metal layer 16, an interface impurity layer 16 made of impurities such as oxide, nitride, etc. is formed by a process and external factors.
상기에서, 하지층(12)은 폴리실리콘 구조, 폴리사이드 구조, W, A1, Cu,등과 같은 금속 구조로 된 전도성 패턴이다. 층간 절연막(13)은 낮은 유전 상수를 갖는 유전체물질을 이용하여 형성된다. 다마신 패턴(14)을 형성한 후에 실시하는 클리닝 공정은 하지층(12)이 W, A1등의 금속일 경우에는 고주파 플라즈마(RF Plasma)를 이용하며, 하지층(12)이 Cu일 경우에는 반응성 클리닝(reactive cleaning) 방법을 적용한다. 배리어 금속층(15)은 이온화(ionized) PVD, CVD, MOCVD TiN 박막이나, 이온화(ionized) PVD Ta, TaN, CVD Ta, TaN, WN 박막중 어느 하나로 형성한다. 계면 불순물층(16)은 화학기상증착법으로 구리층을 증착할 때, 구리층의 접착 특성을 저하시키는 것으로 알려져 있다.In the above, the base layer 12 is a conductive pattern of a metal structure such as polysilicon structure, polyside structure, W, A1, Cu, and the like. The interlayer insulating film 13 is formed using a dielectric material having a low dielectric constant. After the damascene pattern 14 is formed, the cleaning process is performed using RF plasma when the base layer 12 is made of metal such as W or A1, and when the base layer 12 is Cu. Reactive cleaning method is applied. The barrier metal layer 15 is formed of any one of ionized PVD, CVD, and MOCVD TiN thin films, or ionized PVD Ta, TaN, CVD Ta, TaN, and WN thin films. The interfacial impurity layer 16 is known to reduce the adhesive properties of the copper layer when the copper layer is deposited by chemical vapor deposition.
도 1b를 참조하면, 후에 실시될 화학기상증착법에 의한 구리층 형성시에 구리층의 접착 특성을 개선하기 위하여, 계면 불순물층(16)을 플라즈마 처리 방법으로 제거한다.Referring to FIG. 1B, in order to improve adhesion characteristics of the copper layer at the time of forming the copper layer by chemical vapor deposition, which will be performed later, the interface impurity layer 16 is removed by a plasma treatment method.
상기에서 플라즈마 처리 방법은 리모트 플라즈마(Remote Plasma) 처리 방법, 챔버 플라즈마(Chamber Plasma) 처리 방법, 리모트 플라즈마 처리와 챔버 플라즈마 처리를 병행하는 방법중 어느 하나를 적용하는데, 그 조건은 다음과 같다.The plasma processing method may be any one of a remote plasma processing method, a chamber plasma processing method, a method of performing a remote plasma processing and a chamber plasma processing in parallel, and the conditions are as follows.
첫째, 리모트 플라즈마 처리 방법은 리모트 플라즈마의 전력(power)을 50 내지 700W의 범위로 하고, 사용 가스를 수소(H2), 질소(N2), 아르곤(Ar), 헬륨(He) 중 적어도 어느 하나를 사용하되, 그 유량을 50 내지 500 sccm으로 유지하며, 웨이퍼온도를 150 내지 350℃로 유지하고, 웨이퍼와 샤워 헤드의 간격을 20 내지 50mm로 하며, 챔버 압력을 0.3 내지 2 Torr로 하여 10초-10분 동안 처리 한다.First, in the remote plasma processing method, the power of the remote plasma is in the range of 50 to 700 W, and the gas used is at least one of hydrogen (H 2 ), nitrogen (N 2 ), argon (Ar), and helium (He). Using one, the flow rate is maintained at 50 to 500 sccm, the wafer temperature is maintained at 150 to 350 ℃, the distance between the wafer and the shower head is 20 to 50mm, the chamber pressure is 0.3 to 2 Torr 10 Handle for 10-10 minutes.
사용 가스로 혼합 가스를 사용할 경우 아르곤 5 내지 95% 및 수소 5 내지 95%로 하여 이용하여 스퍼터링(sputtering)하는 방법을 포함한다.In the case of using the mixed gas as the working gas, a method of sputtering by using 5 to 95% of argon and 5 to 95% of hydrogen is included.
한편, 리모트 플라즈마 처리 방법은 단일 스텝 및 다단계 스텝의 이용이 가능한데, 단일 스텝을 이용하는 경우는 사용 가스로 단일 가스 및 혼합 가스의 사용이 가능하며, 다단계 스텝을 이용하는 경우는 먼저 아르곤 단일 가스를 이용하거나 혼합 가스를 이용하여 처리한 후, 수소 가스를 이용하여 최종 처리를 하는 주기를 1 내지 10회 반복하는 과정을 포함한다.In the remote plasma processing method, a single step and a multi-step step may be used. When using a single step, a single gas and a mixed gas may be used as the used gas, and when using a multi-step step, a single argon single gas may be used. After the treatment using the mixed gas, a cycle of performing the final treatment using hydrogen gas is repeated 1 to 10 times.
둘째, 챔버 플라즈마 처리 방법은 챔버 플라즈마 전력을 50 내지 700W의 범위로 하고, 사용 가스를 수소(H2), 질소(N2), 아르곤(Ar), 헬륨(He) 중 적어도 어느 하나를 사용하되, 그 유량을 50 내지 500 sccm으로 유지하며, 웨이퍼 온도를 150 내지 350℃로 유지하고, 웨이퍼와 샤워 헤드의 간격을 20 내지 50mm로 하며, 챔버 압력을 0.3 내지 2 Torr로 하여 10초-10분 동안 처리 한다.Second, the chamber plasma treatment method is a chamber plasma power in the range of 50 to 700W, using at least one of hydrogen (H 2 ), nitrogen (N 2 ), argon (Ar), helium (He). The flow rate is maintained at 50 to 500 sccm, the wafer temperature is maintained at 150 to 350 ° C., the gap between the wafer and the shower head is 20 to 50 mm, and the chamber pressure is 0.3 to 2 Torr for 10 seconds to 10 minutes. Should be handled during.
사용 가스로 혼합 가스를 사용할 경우 아르곤 5 내지 95% 및 수소 5 내지 95%로 하여 이용하여 스퍼터링(sputtering)하는 방법을 포함한다.In the case of using the mixed gas as the working gas, a method of sputtering by using 5 to 95% of argon and 5 to 95% of hydrogen is included.
셋째, 챔버 플라즈마 처리 및 리모트 플라즈마 처리를 병행하는 방법은 먼저 챔버 플라즈마 처리를 한 후에 리모트 플라즈마 처리를 시행하는데, 단일 스텝 및 다단계 스텝의 이용이 가능하다. 이때, 챔버 플라즈마 처리 및 리모트 플라즈마 처리 각각의 조건은 전술한 각 플라즈마 처리 조건과 같다.Third, the chamber plasma process and the remote plasma process are performed in parallel, and the chamber plasma process is performed first, and then the remote plasma process is performed. A single step and a multi-step step can be used. At this time, the conditions of the chamber plasma processing and the remote plasma processing are the same as the above-mentioned respective plasma processing conditions.
도 1c를 참조하면, 플라즈마 처리하여 계면 불순물층(16)을 제거한 후, 화학기상증착법으로 다마신 패턴(14)을 구리로 매립시켜 구리층(17)을 형성한다.Referring to FIG. 1C, after the plasma impurity layer 16 is removed, the damascene pattern 14 is embedded with copper to form a copper layer 17 by chemical vapor deposition.
상기에서, 구리 매립은 (hfac)CuVTMOS계열, (hfac)CuTMVS계열, (hfac)CuDMB계열과 같은 hfac를 이용한 모든 종류의 구리 전구체를 이용하여 DLI(Direct Liquid Injection), CEM, 오리피스(Orifice)와 스프레이(Spray) 방식의 모든 기화기(vaporizer)에 적용이 가능하며, 이를 이용한 금속 유기 화학기상증착(MOCVD)법으로 구리 증착을 한다.In the above, the copper buried using all kinds of copper precursors using hfac, such as (hfac) CuVTMOS series, (hfac) CuTMVS series, (hfac) CuDMB series, DLI (Direct Liquid Injection), CEM, Orifice (Orifice) and It is applicable to all vaporizers of the spray method, and copper deposition is performed by metal organic chemical vapor deposition (MOCVD) method using the same.
금속 유기 화학기상증착법에 의한 증착 조건은 구리 전구체를 0.1 내지 5.0 sccm의 유량비로 유지하고, 캐리어 가스를 수소(H2), 아르곤(Ar), 헬륨(He) 중 적어도 어느 하나를 사용하되, 그 유량을 100 내지 700 sccm으로 유지하며, 반응챔버의 온도를 기화기의 온도와 같게 유지하며, 샤워 헤드의 온도가 일정하게 유지 되도록 하고, 증착 온도를 150 내지 300℃로 유지하며, 서셉터 플레이트(susceptor)와 샤워 헤드의 간격을 20 내지 50mm로 하며, 챔버 압력을 0.5 내지 5 Torr로한다.The deposition conditions by the metal organic chemical vapor deposition method is to maintain the copper precursor at a flow rate of 0.1 to 5.0 sccm, using a carrier gas of at least one of hydrogen (H 2 ), argon (Ar), helium (He), Maintaining a flow rate of 100 to 700 sccm, keeping the temperature of the reaction chamber equal to the temperature of the vaporizer, keeping the temperature of the shower head constant, maintaining the deposition temperature at 150 to 300 ° C, and susceptor plates ) And the shower head is 20 to 50 mm, and the chamber pressure is 0.5 to 5 Torr.
도 1d를 참조하면, 구리층(17)을 수소환원 열처리한 후에 화학적 기계적 연마(CMP) 처리 및 후 세정(post-cleaning)을 실시하여 다마신 패턴(14) 내에 구리 금속 배선(170)을 형성한다.Referring to FIG. 1D, after the hydrogen reduction heat treatment of the copper layer 17, chemical mechanical polishing (CMP) and post-cleaning are performed to form the copper metal wiring 170 in the damascene pattern 14. do.
상기에서, 수소환원 열처리는 수소 환원분위기에서 상온 내지 450℃의 온도에서 1분 내지 3시간 열처리를 하여 구리층(17)의 그레인 조직(grain morphology)을 바꾸는 과정인데, 이때의 수소 환원분위기는 수소(H2) 만을 사용하거나, H2+Ar(0-95%), H2+N2(0-95%)등과 같은 수소 혼합기체를 사용한다.In the above, the hydrogen reduction heat treatment is a process of changing the grain morphology of the copper layer 17 by performing a heat treatment for 1 minute to 3 hours at a temperature of from room temperature to 450 ° C. in a hydrogen reduction atmosphere. Use only (H 2 ) or a hydrogen mixed gas such as H 2 + Ar (0-95%), H 2 + N 2 (0-95%).
상기한 본 발명의 실시예는 물리기상증착법이나 전기도금(Electroplating)법으로 매립하기 어려운 초 미세 배선 구조에 구리를 화학기상증착(CVD)법으로 매립할 때, 단일 화학기상증착 챔버(CVD chamber)에서 구리층의 접착 특성을 개선하기 위하여, 리모트 플라즈마 장치를 이용하여 화학기상증착법으로 구리층을 증착하기 전에 배리어 금속층의 표면에 계면 불순물층을 제거하는 플라즈마 처리하는 것이다. 플라즈마 처리는 리모트 플라즈마 및/또는 챔버 플라즈마 처리 방법을 적용한다.The embodiment of the present invention described above is a single chemical vapor deposition chamber (CVD chamber) when copper is buried in a very fine wiring structure that is difficult to be buried by physical vapor deposition or electroplating. In order to improve the adhesion characteristics of the copper layer, the plasma treatment is performed to remove the interfacial impurity layer on the surface of the barrier metal layer before depositing the copper layer by chemical vapor deposition using a remote plasma apparatus. Plasma processing applies a remote plasma and / or chamber plasma processing method.
상술한 바와 같이, 본 발명은 물리기상증착법이나 전기도금법으로 매립하기 어려운 초 미세 배선 구조에 구리를 화학기상증착법으로 매립할 때 발생되는 구리층의 접착 특성 문제를 개선시키므로, 기존의 물리기상증착법으로 구리 시드층(seed layer) 형성 공정을 생략할 수 있고, 화학기상증착법으로만 구리 금속 배선을 형성가능하게 하여 공정을 용이하게 할 수 있다.As described above, the present invention improves the problem of adhesion characteristics of the copper layer generated when the copper is buried in the chemical vapor deposition method in the ultra fine wiring structure that is difficult to be embedded by the physical vapor deposition method or the electroplating method. The copper seed layer forming process can be omitted, and the copper metal wiring can be formed only by chemical vapor deposition to facilitate the process.
Claims (14)
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| KR1019990048752A KR100341849B1 (en) | 1999-11-05 | 1999-11-05 | Method of forming a metal wiring in a semiconductor device |
| TW89123263A TW486746B (en) | 1999-11-05 | 2000-11-04 | Method of forming a metal wiring in a semiconductor device |
| JP2000337605A JP2001144094A (en) | 1999-11-05 | 2000-11-06 | Method of forming metal interconnection for semiconductor device |
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| US9051641B2 (en) | 2001-07-25 | 2015-06-09 | Applied Materials, Inc. | Cobalt deposition on barrier surfaces |
| KR20030051014A (en) * | 2001-12-20 | 2003-06-25 | 동부전자 주식회사 | Method of manufacturing via contact in semiconductor device |
| KR100445551B1 (en) * | 2001-12-21 | 2004-08-25 | 동부전자 주식회사 | Method of remove a residual metal-oxidation product of a semiconductor device fabrication process |
| KR100723253B1 (en) * | 2005-12-29 | 2007-05-29 | 동부일렉트로닉스 주식회사 | Fabricating method of metal line in semiconductor device |
| KR20080113518A (en) | 2007-06-25 | 2008-12-31 | 주식회사 동부하이텍 | Method of manufacturing semiconductor device |
| KR101225642B1 (en) | 2007-11-15 | 2013-01-24 | 삼성전자주식회사 | Method for formation of contact plug of semiconductor device using Ｈ2 remote plasma treatment |
| US8227344B2 (en) * | 2010-02-26 | 2012-07-24 | Tokyo Electron Limited | Hybrid in-situ dry cleaning of oxidized surface layers |
| KR101366367B1 (en) * | 2013-01-25 | 2014-02-24 | 박종익 | Method for forming copper layer of power semiconductor module |
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