KR19990051220A - Method for forming metal wiring of semiconductor device with plug metal film - Google Patents

Method for forming metal wiring of semiconductor device with plug metal film Download PDF

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KR19990051220A
KR19990051220A KR1019970070501A KR19970070501A KR19990051220A KR 19990051220 A KR19990051220 A KR 19990051220A KR 1019970070501 A KR1019970070501 A KR 1019970070501A KR 19970070501 A KR19970070501 A KR 19970070501A KR 19990051220 A KR19990051220 A KR 19990051220A
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film
metal
forming
metal film
plug
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KR1019970070501A
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KR100257481B1 (en
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박상훈
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김영환
현대전자산업 주식회사
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    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
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    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
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Abstract

본 발명은 텅스텐 플러그를 구비하는 반도체 소자의 금속 배선에 있어서, 금속 배선과 텅스텐 플러그간에 오정렬이 발생되더라도, 접촉 저항이 증대되지 않는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법에 관한 것이다. 본 발명은, 도전 영역을 구비한 반도체 기판을 제공한다. 반도체 기판 상부에 평탄화된 산화막을 형성하고, 도전 영역이 노출되도록 산화막을 소정 부분 식각하여, 콘택홀을 형성한다. 이어서, 콘택홀내부에 플러그 금속막을 형성하는 단계와, 상기 플러그 금속막 상부 및 산화막 상부에 금속막을 증착하고, 금속막 상부에 금속 배선 형성용 마스크를 형성한다. 그리고나서, 마스크를 이용하여, 금속막을 소정 두께만큼 남도록 식각한다음, 금속막 상부에 절연막을 증착한다. 그후, 절연막을 금속막 표면이 노출되도록 비등방성 식각하여, 일부 식각되어진 금속막의 측부에 스페이서를 형성하고, 스페이서를 마스크로 하여, 노출된 금속막을 식각한다. 이때, 마스크를 형성하는 단계시 오정렬이 발생될 수 있으며, 상기 절연막의 두께는 오정렬이 발생된 거리보다 두껍게 형성하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device having a plug metal film in which the contact resistance does not increase even when misalignment occurs between the metal wiring and the tungsten plug in the metal wiring of the semiconductor device having the tungsten plug. The present invention provides a semiconductor substrate having a conductive region. A planarized oxide film is formed over the semiconductor substrate, and the oxide film is partially etched to expose the conductive region, thereby forming contact holes. Subsequently, a plug metal film is formed in the contact hole, a metal film is deposited on the plug metal film and the oxide film, and a metal wiring forming mask is formed on the metal film. Then, using a mask, the metal film is etched to remain by a predetermined thickness, and then an insulating film is deposited on the metal film. Thereafter, the insulating film is anisotropically etched to expose the surface of the metal film, a spacer is formed on the side of the partially etched metal film, and the exposed metal film is etched using the spacer as a mask. In this case, misalignment may occur during the forming of the mask, and the thickness of the insulating layer may be thicker than a distance at which the misalignment occurs.

Description

플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법Metal wiring formation method of semiconductor element provided with plug metal film

본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 보다 구체적으로는, 텅스텐 플러그를 구비하는 반도체 소자의 금속 배선에 있어서, 금속 배선과 텅스텐 플러그간에 오정렬이 발생되더라도, 접촉 저항이 증대되지 않는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device. More specifically, in a metal wiring of a semiconductor device having a tungsten plug, a plug in which contact resistance does not increase even when misalignment occurs between the metal wiring and the tungsten plug. A metal wiring formation method of a semiconductor element provided with a metal film.

최근, 반도체 장치가 고집적화됨에 따라, 배선 설계가 자유롭고, 배선 저항 및 전류 용량등의 설정을 여유있게 할 수 있는 다층 금속 배선 제조 기술에 대한 연구가 활발하게 진행되고 있다. 그러나, 이러한 다층 금속 배선은, R(저항)·C(캐패시턴스) 신호 전달 시간 지연과 동력 배선의 I(전류)·R(저항) 강하등의 문제로 인하여 단위칩에서 배선 능력이 한계에 다다르게 되고, 또한, 알루미늄 박막의 층덮힘 특성에 의하여 비아 콘택 부위에 상대적으로 얇아진 알루미늄 배선은 보다 쉽게 전자 이동(electromigration)을 발생시키고 있다.In recent years, as semiconductor devices have been highly integrated, research on multilayer metal wiring manufacturing techniques that can freely design wiring and allow setting of wiring resistance and current capacity, etc., has been actively conducted. However, due to problems such as delay of R (resistance) and C (capacitance) signal transmission time and I (current) and R (resistance) drop of power wiring, such a multilayer metal wiring reaches the limit of wiring capability in the unit chip. In addition, the aluminum wiring, which is relatively thinned in the via contact region due to the layer covering characteristic of the aluminum thin film, more easily generates electromigration.

이러한 전자 이동에 대하여 보다 상세히 설명하자면, 알루미늄 배선에 전계가 인가되면, 많은 수의 전자로 구성된 전류가 발생되고, 이로 인하여 전자가 전계 백터의 반대 방향으로 움직이는데, 이를 통상적으로 전자 바람(electron wind)라 한다. 또한, 알루미늄 원자가 여기된 상태에서의 전자는 활성화된 알루미늄 원자와 충돌하고, 일부 전자의 모멘텀(momentum)이 알루미늄에 전달되어, 전자 바람의 방향으로 알루미늄 원자가 이동함으로써, 결국에는 알루미늄 배선내에 전자 이동이 발생된다.To describe in more detail the electron movement, when an electric field is applied to the aluminum wiring, a current consisting of a large number of electrons are generated, which causes the electrons to move in the opposite direction of the electric field vector, which is typically an electron wind. It is called. In addition, electrons in the state where the aluminum atoms are excited collide with the activated aluminum atoms, and momentum of some electrons is transferred to the aluminum, and the aluminum atoms move in the direction of the electron wind, resulting in electron movement in the aluminum wiring. Is generated.

일반적으로, 알루미늄 배선의 전자 이동에 따른 불량은 오픈(open) 또는 쇼트(short)의 형태로 발생되고, 이러한 불량은 알루미늄 배선의 단면적으로부터 충분한 수의 알루미늄 원자가 국부적으로 부족하게 될 때 발생되며, 이로 인하여 전기적 불연속이 형성된다. 이런 형태의 결함은 전자 바람의 힘(force)이 없이도 일어나게 되고, 알루미늄 배선은 기계적인 스트레스를 받게된다. 또 다른 형태로는, 하나 혹은 그 이상의 지역으로부터 부족하게 되는 알루미늄 원자가 축적되어, 휘스커(whisker), 돌기(extrusion), 힐록(hillock)등이 국부적으로 형성되어 쇼트가 발생된다. 이는 알루미늄 배선의 압축되거나, 플럭스 다이버전스(flux divergence)의 사이트(site)에 있을 때, 알루미늄 원자가 축적됨으로써, 힐록이 발생된다. 즉, 알루미늄 배선이 압축 스트레스하에 있을때에, 휘스커 또는 익스트르션과 같은 현상이 발생된다. 또한, 플럭스 다이버젼스의 사이트에 설정되었다면, 동공이 성장하기 위하여 연속적인 베컨시(vacancy) 플럭스 다이버젼스가 필요하게 된다. 제한된 단면적을 갖는 알루미늄 배선의 경우에 있어서, 동공 성장은 국부적인 막의 온도를 증가시켜, 동공 성장을 가속시키는 전류 밀집(current crowding) 현상을 일으키게 된다.In general, a failure due to electron movement of the aluminum wiring occurs in the form of an open or a short, and this failure occurs when a sufficient number of aluminum atoms are locally insufficient from the cross-sectional area of the aluminum wiring. Due to this electrical discontinuity is formed. This type of defect occurs without the force of an electronic wind, and aluminum wiring is subject to mechanical stress. In another form, aluminum atoms, which are lacking from one or more regions, accumulate, and whiskers, protrusions, hillocks, and the like are locally formed to cause shorts. This is due to the accumulation of aluminum atoms when the aluminum wiring is compressed or at the site of flux divergence, resulting in hillock. That is, when the aluminum wiring is under compressive stress, a phenomenon such as whiskers or extrusion occurs. Also, if set at the site of flux divergence, a continuous vacancy flux divergence is required for the pupil to grow. In the case of aluminum interconnects with a limited cross-sectional area, pupil growth increases the local film temperature, causing current crowding that accelerates pupil growth.

따라서, 비아, 콘택 홀의 크기가 0.5㎛ 이하로 축소되는 다층 금속 배선의 구조에서, 특히 에스펙트비가 1.8 이상인 경우에는, 금속 배선간의 수직 연결용 비아 콘택 기술로, 알루미늄 스퍼터링 방법이 부적절하다.Therefore, in the structure of the multi-layer metal wiring in which the size of the via and the contact hole is reduced to 0.5 µm or less, especially when the aspect ratio is 1.8 or more, the aluminum sputtering method is inappropriate as a via contact technology for vertical connection between the metal wirings.

이러한 알루미늄이 가지고 있는 문제점을 해소하기 위하여, 종래에는 콘택홀 내부에 전자 이동 현상이 비교적 적으면서, 콘택홀 매립 특성이 우수한 텅스텐을 매립하는 플러그 기술이 제안되었다.In order to solve the problem that aluminum has, conventionally, a plug technology for embedding tungsten with excellent contact hole filling characteristics while relatively less electron transfer phenomenon has been proposed.

이 기술은, 도 1에 도시된 바와 같이, 도전 영역(2)을 구비한 반도체 기판(1) 상부에 평탄화 산화막(3)을 소정 두께로 증착한다. 이어서, 도전 영역(2)의 소정 부분이 노출되도록, 예를들어, 2개의 콘택홀을 형성한다. 그후, 콘택홀의 내벽부에는 전자 이동 또는 스트레스가 소자내로 인가되는 것을 감소하도록, Ti/TiN막과 같은 장벽 금속막(4)을 피복한다. 콘택홀내에, 화학 기상 증착 방식에 의하여, 텅스텐 플러그(5)를 형성한다. 이때, 텅스텐 금속은 매립 특성이 우수하여, 콘택홀내에 용이하게 매립되어, 결과물 표면은 평탄하여 진다. 그리고나서, 텅스텐 플러그(5) 및 산화막(3) 상부에 금속 배선용 금속막을 증착하고, 소정 부분 패터닝하여, 금속 배선막(6)을 형성한다.In this technique, as shown in FIG. 1, the planarization oxide film 3 is deposited to a predetermined thickness on the semiconductor substrate 1 provided with the conductive region 2. Next, for example, two contact holes are formed so that a predetermined portion of the conductive region 2 is exposed. The inner wall portion of the contact hole is then covered with a barrier metal film 4, such as a Ti / TiN film, to reduce the application of electron transfer or stress into the device. In the contact hole, a tungsten plug 5 is formed by chemical vapor deposition. At this time, the tungsten metal is excellent in the embedding characteristics, it is easily embedded in the contact hole, the resulting surface becomes flat. Then, a metal film for metal wiring is deposited on the tungsten plug 5 and the oxide film 3, and predetermined patterning is performed to form the metal wiring film 6.

그러나, 상기와 같은 텅스텐 플러그를 포함하는 금속 배선 형성 방법은 다음과 같은 문제점을 갖는다.However, the metal wiring forming method including the tungsten plug as described above has the following problems.

즉, 상기 텅스텐 플러그과 접촉되도록 금속 배선을 형성하는 공정은 일반적으로 포토리소그라피 공정에 의하여 마스크를 형성한 후, 이 마스크의 형태로 금속 배선을 식각하여, 금속 배선을 형성한다. 그러나, 상기의 포토리소그라피 공정시, 노광 장비의 불안정에 의하여 도 1에 도시된 바와 같이, 마스크가 약간 오정렬이 발생될 수 있다. 이로 인하여, 텅스텐 플러그와 금속 배선간의 접촉하는 면적이 변화되어, 접촉 저항이 증가된다.That is, in the process of forming the metal wiring to contact the tungsten plug, a mask is generally formed by a photolithography process, and then the metal wiring is etched in the form of the mask to form the metal wiring. However, in the above photolithography process, the mask may be slightly misaligned as shown in FIG. 1 due to instability of the exposure equipment. As a result, the contact area between the tungsten plug and the metal wiring is changed, and the contact resistance is increased.

따라서, 본 발명은, 포토리소그라피 공정이 약간의 오정렬이 발생되더라도, 접촉 저항을 증가시키지 않는 플러그 금속막을 포함하는 반도체 소자의 금속 배선 형성방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device including a plug metal film which does not increase the contact resistance even if some misalignment occurs in the photolithography process.

도 1은 종래의 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법을 설명하기 위한 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view for explaining a metal wiring formation method of a semiconductor device having a conventional plug metal film.

도 2a 내지 도 2e는 본 발명에 따른 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법을 설명하기 위한 각 제조 공정별 단면도.2A to 2E are cross-sectional views of respective manufacturing processes for explaining a method for forming metal wirings of a semiconductor device having a plug metal film according to the present invention.

(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

11 : 반도체 기판 12 : 도전 영역11 semiconductor substrate 12 conductive region

13 : 산화막 14 : 장벽 금속막13 oxide film 14 barrier metal film

15 : 텅스텐 플러그 16 : 접촉 금속막15 tungsten plug 16 contact metal film

17 : 알루미늄 합금막 18 : 난반사 방지막17: aluminum alloy film 18: diffuse reflection prevention film

19 : 마스크 패턴 20 : 스페이서용 절연막19 mask pattern 20 insulating film for spacer

21 : 스페이서21: spacer

상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 일 실시예에 따르면, 도전 영역을 구비한 반도체 기판을 제공하는 단계와, 상기 반도체 기판 상부에 평탄화된 산화막을 형성하는 단계와, 상기 도전 영역이 노출되도록 상기 산화막을 소정 부분 식각하여, 콘택홀을 형성하는 단계와, 상기 콘택홀내부에 플러그 금속막을 형성하는 단계와, 상기 플러그 금속막 상부 및 산화막 상부에 금속막을 증착하는 단계와, 상기 금속막 상부에 금속 배선 형성용 마스크를 형성하는 단계와, 상기 마스크를 이용하여, 금속막을 소정 두께만큼 남도록 식각하는 단계와, 상기 금속막 상부에 절연막을 증착하는 단계와, 상기 절연막을 금속막 표면이 노출되도록 비등방성 식각하여, 일부 식각되어진 금속막의 측부에 스페이서를 형성하는 단계와, 상기 스페이서를 마스크로 하여, 노출된 금속막을 식각하는 단계를 포함하며, 상기 마스크를 형성하는 단계시 오정렬이 발생될 수 있으며, 상기 절연막의 두께는 오정렬이 발생된 거리보다 두껍게 형성하는 것을 특징으로 한다.In order to achieve the above object of the present invention, according to an embodiment of the present invention, providing a semiconductor substrate having a conductive region, forming a planarized oxide film on the semiconductor substrate, and the conductive region Etching a portion of the oxide film so that the oxide film is exposed, forming a contact hole, forming a plug metal film in the contact hole, depositing a metal film on the plug metal film and on the oxide film, and Forming a mask for forming a metal wiring on the film, etching the metal film to a predetermined thickness using the mask, depositing an insulating film on the metal film, and depositing the insulating film on the metal film surface. Anisotropically etching to expose the spacers to form spacers on the sides of the partially etched metal film, and masking the spacers As by comprising the step of etching the exposed metal film, can be a misalignment when forming the mask occurs, the thickness of the insulating film is characterized in that it is formed to be thicker than the misalignment occurs distance.

본 발명에 의하면, 금속 배선 형성시, 알루미늄 합금막을 전체 두께의 소정 두께만을 식각한다음, 식각이 이루어진 부분에 오정렬을 수용할 수 있을만큼의 폭을 갖는 스페이서를 형성한다음, 이를 마스크로 이용하여 금속 배선을 패터닝한다. 이에 따라, 금속 배선 형성용 마스크가 오정렬이 발생되더라도, 스페이서에 의하여 오정렬이 발생된 부분을 충분히 수용하여, 금속 배선과 텅스텐 플러그 접촉되는 면적은 변화되지 않는다. 그러므로, 금속 배선의 접촉 저항이 감소된다. 따라서, 금속 배선 신뢰성이 개선된다.According to the present invention, when forming a metal wiring, the aluminum alloy film is etched only a predetermined thickness of the entire thickness, and then a spacer having a width wide enough to accommodate misalignment is formed in the etched portion, and then used as a mask. Pattern the metal wires. Accordingly, even if the misalignment occurs in the mask for forming the metal wiring, the area where the misalignment is caused by the spacer is sufficiently accommodated, and the area where the tungsten plug contacts the metal wiring is not changed. Therefore, the contact resistance of the metal wiring is reduced. Therefore, the metal wiring reliability is improved.

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도면 도 2a 내지 도 2e는 본 발명에 따른 플러그 금속막을 포함하는 반도체 소자의 금속 배선 형성방법을 설명하기 위한 각 제조 공정별 단면도이다.2A through 2E are cross-sectional views of respective manufacturing processes for explaining a method of forming metal wirings of a semiconductor device including a plug metal film according to the present invention.

먼저, 도전 영역(12)을 포함하는 반도체 기판(11)이 준비된다. 여기서, 도전 영역(12)은 접합 영역, 게이트 전극, 제 1 금속 배선등이 될 수 있으며, 본 실시예는 도전 영역(12)을 접합 영역으로 예를들어 설명한다. 반도체 기판(11) 상부에 층간 절연용 산화막(13)을 형성한다. 이때, 층간 절연용 산화막(13)은 저압 기상(LPCVD)-TEOS막, BPSG막, 오존-BPSG막, 오존-TEOS막, PE-TEOS막, PSG막, SOG막. 과잉 실리콘(silicon rich)산화막, 질산화막 중 하나 또는 이들중 두 개 이상의 박막이 조합된 막이 이용된다. 아울러, 이들막은 평탄화를 도모하기 위하여, 실리카 슬러리를 사용한 화학 기계적 연마법, 또는 CF4/CHF3가스의 화학 반응에 의하여 에치백된다. 그후, 도전 영역이 노출되도록, 산화막(13)을 소정 부분 식각하여, 예를들어, 2개의 콘택홀을 형성한다. 콘택홀 내벽에 250 내지 350Å 두께의 Ti막과, 650 내지 750Å 두께의 TiN막으로 된 장벽 금속막(14)을 피복한다. 그후, 400 내지 450℃의 온도에서 WF6가스와 SiH4가스로서, 전면성 텅스텐 금속막을 4000 내지 6000Å 두께로 화학 기상 증착법에 의하여 형성한다. 이어서, 이 전면성 텅스텐막을 SF6/Ar 가스에 의하여 비등방성 식각하여, 플러그 금속막 즉, 텅스텐 플러그(15)를 형성한다.First, the semiconductor substrate 11 including the conductive region 12 is prepared. Here, the conductive region 12 may be a junction region, a gate electrode, a first metal wiring, or the like. In this embodiment, the conductive region 12 will be described as an example of a junction region. An interlayer insulating oxide film 13 is formed over the semiconductor substrate 11. At this time, the interlayer insulating oxide film 13 is a low pressure gas phase (LPCVD) -TEOS film, a BPSG film, an ozone-BPSG film, an ozone-TEOS film, a PE-TEOS film, a PSG film, and an SOG film. One of an excess silicon rich oxide film, a nitride oxide film, or a combination of two or more thin films thereof is used. In addition, these films are etched back by chemical mechanical polishing using a silica slurry or chemical reaction of CF 4 / CHF 3 gas to planarize. Thereafter, the oxide film 13 is partially etched so that the conductive region is exposed, for example, two contact holes are formed. A barrier metal film 14 made of a Ti film 250 to 350 mm thick and a TiN film 650 to 750 mm thick is coated on the inner wall of the contact hole. Thereafter, a full-tungsten metal film is formed by chemical vapor deposition to a thickness of 4000 to 6000 kPa as WF 6 gas and SiH 4 gas at a temperature of 400 to 450 占 폚. Subsequently, the full surface tungsten film is anisotropically etched with SF 6 / Ar gas to form a plug metal film, that is, a tungsten plug 15.

그리고나서, 도 2b에 도시된 바와 같이, 텅스텐 플러그(15) 및 산화막(13) 상부에는 이후 형성될 알루미늄막과 텅스텐 플러그(15)간의 접착 특성을 강화하기 위하여, 300 내지 1000Å 두께의 Ti과 같은 접촉 금속막(16)을 증착한다. 그후, 그 상부에 인 시튜(in-situ) 방식에 의하여 5000 내지 8000Å두께의 알루미늄 합금막(17)을 형성한다. 이 알루미늄 합금막(17)으로는, Al-0.5%Cu막, Al-1%Si-0.5%Cu막, Al-1%Si막중 하나가 이용된다. 그후, 알루미늄 합금막(17) 상부에 알루미늄의 난반사를 방지하기 위하여, 질산화막과 같은 난반사 방지막(18)을 알루미늄 합금막 두께의 10 내지 20% 정도 예를들어, 500 내지 1600Å 정도로 증착한다. 그리고나서, 난반사 방지막(18) 상부에 금속 배선용 마스크 패턴(19)을 공지의 포토리소그라피 공정에 의하여 형성한다. 이때, 마스크 패턴(19)은 종래와 같이 노광 장비의 불안정으로 인하여 다소 오정렬이 발생될 수 있다. 여기서, 미설명 부호 d는 마스크 패턴이 오정렬이 발생되는 거리이다. 즉, 상기 마스크 패턴은 콘택홀을 포함할 수 있도록 형성되어야 하나, 포토리소그라피 공정시 약간의 오정렬로 일측으로 치우치게 형성될 수 있다. 이 마스크 패턴(19)을 이용하여, 노출된 난반사 방지막(18)과 알루미늄 합금막(17)을 BCl3, Cl2가스에 의하여 패터닝한다. 이때, 노출된 난반사 방지막(18)은 모두 식각되고, 알루미늄 합금막(17)은, 전체 알루미늄 합금막(17)의 두께의 2분의 1 내지는 4분의 3만큼 식각되도록 한다. 또한, 상기 난반사 방지막(18)을 500 내지 1600Å 정도로 비교적 두껍게 형성하는 것은 다음과 같다. 즉, 1988년, wolf등에 의하여 IEEE/IRPS에 발표된 "Reliability prediction of MOS device: Exiperiments and model for charge build up and annealing" 논문에 기재된 바와 같이, 금속 배선을 식각하기 위한 플라즈마 전하 인가시, 플라즈마 전하는 금속 배선을 통하여 축적되어, 게이트 산화막내에 전하(trap charge)가 포획되고, 이 포획 전하가 게이트 산화막의 파괴 전압을 떨어뜨려, 반도체 소자의 특성 및 신뢰성을 악화시키는 안테나 현상을 방지하기 위함이다. 또한, 이후에 형성되어질 금속 배선의 측벽에 산화막 스페이서의 형성시 알루미늄 합금막에 가해지는 플라즈마 손상을 방지하기 위함이다.Then, as shown in Fig. 2b, on the top of the tungsten plug 15 and the oxide film 13, in order to enhance the adhesive properties between the aluminum film and the tungsten plug 15 to be formed later, such as Ti of 300 to 1000 300 thickness The contact metal film 16 is deposited. Thereafter, an aluminum alloy film 17 having a thickness of 5000 to 8000 kPa is formed on the top thereof by an in-situ method. As the aluminum alloy film 17, one of an Al-0.5% Cu film, an Al-1% Si-0.5% Cu film, and an Al-1% Si film is used. Thereafter, in order to prevent diffuse reflection of aluminum on the aluminum alloy film 17, a diffuse reflection prevention film 18 such as a nitrification film is deposited by about 10 to 20% of the thickness of the aluminum alloy film, for example, about 500 to 1600 kPa. Then, the mask pattern 19 for metal wiring is formed on the diffuse reflection prevention film 18 by a well-known photolithography process. At this time, the mask pattern 19 may be somewhat misaligned due to instability of the exposure equipment as in the prior art. Here, reference numeral d denotes a distance at which the mask pattern is misaligned. That is, the mask pattern should be formed to include contact holes, but may be formed to be biased to one side with a slight misalignment during the photolithography process. Using this mask pattern 19, the exposed antireflection film 18 and the aluminum alloy film 17 are patterned by BCl 3 and Cl 2 gas. At this time, all the exposed antireflection films 18 are etched, and the aluminum alloy film 17 is etched by 1/2 to 3/4 of the thickness of the entire aluminum alloy film 17. In addition, it is as follows that the diffuse reflection prevention film 18 is formed relatively thick about 500-1600 Å. In other words, as described in the article "Reliability prediction of MOS device: Exiperiments and model for charge build up and annealing" published in IEEE / IRPS in 1988 by wolf et al. This is to prevent the antenna phenomenon that accumulates through the metal wirings, trap charges are trapped in the gate oxide film, and this trap charge lowers the breakdown voltage of the gate oxide film, thereby deteriorating the characteristics and reliability of the semiconductor element. In addition, this is to prevent plasma damage to the aluminum alloy film when the oxide spacer is formed on the sidewall of the metal wiring to be formed later.

그 다음으로, 도 2c에서와 같이, 감광막 패턴(19)을 공지의 방법으로 제거하고, 스페이서용 절연막(20) 예를들어, PE-TEOS 산화막 또는 과잉 실리콘 산화막을 소정 두께, 바람직하게는, 오정렬이 발생된 거리 d보다 약 300 내지 500Å 정도 더 두껍게 형성된다.Next, as shown in Fig. 2C, the photosensitive film pattern 19 is removed by a known method, and the insulating film for spacers 20, for example, a PE-TEOS oxide film or an excess silicon oxide film is a predetermined thickness, preferably misalignment. It is formed about 300 to 500 mm thicker than this generated distance d.

그후, 난반사 방지막(18)을 식각 정지층으로 하여, 상기 난반사 방지막(18)이 노출되도록 상기 스페이서용 절연막(20)을 CF4또는 C2F6가스를 이용하여 비등방성 전면 식각한다. 이에 따라, 소정 부분 패터닝이 된 난반사 방지막(18) 및 알루미늄 합금막(17)의 측벽에 도 2d에 도시된 바와 같이, 스페이서(21)가 형성된다.Thereafter, using the antireflection film 18 as an etch stop layer, the spacer insulating film 20 is anisotropically etched using CF 4 or C 2 F 6 gas so as to expose the diffuse reflection film 18. As a result, spacers 21 are formed on the sidewalls of the diffuse reflection prevention film 18 and the aluminum alloy film 17 that have been subjected to the predetermined partial patterning.

그리고나서, 도 2e에 도시된 바와 같이, 스페이서(21)을 마스크로 하여, 노출된 알루미늄 합금막(17)을 패터닝하여, 금속 배선을 형성한다.Then, as shown in FIG. 2E, the exposed aluminum alloy film 17 is patterned using the spacer 21 as a mask to form a metal wiring.

이와같은 본 발명은, 스페이서(21)의 폭이 오정렬이 발생된 거리 보다 더 넓은 폭을 가짐으로써, 본 발명에 따른 금속 배선은 상기 금속 배선용 마스크(19)의 폭보다는 더 넓은 폭을 갖게 된다. 따라서, 오정렬이 발생되더라도, 금속 배선이 오정렬을 수용할 수 있을 만큼의 폭을 지니므로, 금속 배선과 텅스텐 플러그(15)가 접촉되는 면적은 변하지 않게 된다.In the present invention, the width of the spacer 21 is wider than the distance at which misalignment occurs, so that the metal wiring according to the present invention has a width wider than that of the mask 19 for metal wiring. Therefore, even if misalignment occurs, since the metal wiring has a width enough to accommodate the misalignment, the area where the metal wiring and the tungsten plug 15 come into contact does not change.

이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 금속 배선 형성시, 알루미늄 합금막을 전체 두께의 소정 두께만을 식각한다음, 식각이 이루어진 부분에 오정렬을 수용할 수 있을만큼의 폭을 갖는 스페이서를 형성한다음, 이를 마스크로 이용하여 금속 배선을 패터닝한다. 이에 따라, 금속 배선 형성용 마스크가 오정렬이 발생되더라도, 스페이서에 의하여 오정렬이 발생된 부분을 충분히 수용하여, 금속 배선과 텅스텐 플러그 접촉되는 면적은 변화되지 않는다. 그러므로, 금속 배선의 접촉 저항이 감소된다. 따라서, 금속 배선 신뢰성이 개선된다.As described in detail above, according to the present invention, when forming a metal wiring, the aluminum alloy film is etched only a predetermined thickness of the entire thickness, and then a spacer having a width wide enough to accommodate misalignment in the etched portion is formed. Then, the metal wiring is patterned using this as a mask. Accordingly, even if the misalignment occurs in the mask for forming the metal wiring, the area where the misalignment is caused by the spacer is sufficiently accommodated, and the area where the tungsten plug contacts the metal wiring is not changed. Therefore, the contact resistance of the metal wiring is reduced. Therefore, the metal wiring reliability is improved.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (14)

도전 영역을 구비한 반도체 기판을 제공하는 단계;Providing a semiconductor substrate having a conductive region; 상기 반도체 기판 상부에 평탄화된 산화막을 형성하는 단계;Forming a planarized oxide film on the semiconductor substrate; 상기 도전 영역의 소정 부분이 노출되도록 상기 산화막을 식각하여, 콘택홀을 형성하는 단계;Etching the oxide layer to expose a predetermined portion of the conductive region to form a contact hole; 상기 콘택홀내부에 플러그 금속막을 형성하는 단계;Forming a plug metal layer in the contact hole; 상기 플러그 금속막 상부 및 산화막 상부에 금속막을 증착하는 단계;Depositing a metal film on the plug metal film and on the oxide film; 상기 금속막 상부에 금속 배선 형성용 마스크를 형성하는 단계;Forming a metal wiring forming mask on the metal layer; 상기 마스크를 이용하여, 금속막을 소정 두께만큼 남도록 식각하는 단계;Etching the metal film to a predetermined thickness by using the mask; 상기 금속막 상부에 절연막을 증착하는 단계;Depositing an insulating film on the metal film; 상기 절연막을 금속막 표면이 노출되도록 비등방성 식각하여, 일부 식각되어진 금속막의 측부에 스페이서를 형성하는 단계; 및Anisotropically etching the insulating film to expose the surface of the metal film, thereby forming a spacer on a side of the partially etched metal film; And 상기 스페이서를 마스크로 하여, 노출된 금속막을 식각하는 단계를 포함하며, 상기 마스크를 형성하는 단계시 오정렬이 발생될 수 있으며, 상기 절연막의 두께는 오정렬이 발생된 거리보다 두껍게 형성하는 것을 특징으로 하는 플러그 금속막을 구비하는 반도체 소자의 금속 배선 형성방법.Etching the exposed metal film using the spacer as a mask, and misalignment may occur during the forming of the mask, wherein the thickness of the insulating layer is formed to be thicker than a distance at which misalignment occurs. A metal wiring forming method of a semiconductor device having a plug metal film. 제 1 항에 있어서, 상기 평탄화된 산화막을 형성하는 단계는, 저압 기상(LPCVD)-TEOS막, BPSG막, 오존-BPSG막, 오존-TEOS막, PE-TEOS막, PSG막, SOG막. 과잉 실리콘(silicon rich)산화막, 질산화막 중 하나 또는 이들중 두 개 이상의 박막이 조합된 막을 증착하는 단계; 상기 선택되는 막을 화학 기계적 연마 또는 에치백하는 평탄화 단계를 포함하는 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.The method of claim 1, wherein the forming of the planarized oxide film comprises: a low pressure gas phase (LPCVD) -TEOS film, a BPSG film, an ozone-BPSG film, an ozone-TEOS film, a PE-TEOS film, a PSG film, and an SOG film. Depositing a film of one or more of a silicon rich oxide film, a nitride oxide film or a combination of two or more thin films thereof; And planarizing the chemically mechanically polished or etched back film of the selected film. 제 1 항에 있어서, 상기 콘택홀을 형성하는 단계와, 상기 플러그 금속막을 형성하는 단계사이에, 상기 콘택홀 내벽에 장벽 금속막을 더 형성하는 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.The metal line of claim 1, wherein a barrier metal film is further formed on an inner wall of the contact hole between the forming of the contact hole and the forming of the plug metal film. Formation method. 제 3 항에 있어서, 상기 장벽 금속막은 Ti막과 TiN 금속막인 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.4. The method for forming a metal wiring of a semiconductor device with a plug metal film according to claim 3, wherein said barrier metal film is a Ti film and a TiN metal film. 제 1 항에 있어서, 상기 플러그 금속막을 형성하는 단계는, 텅스텐 금속막을 상기 콘택홀이 충분이 메꾸어 질정도로 증착하는 단계; 상기 텅스텐 금속막을 상기 산화막이 노출되도록 비등방성 식각하는 단계를 포함하는 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.The method of claim 1, wherein the forming of the plug metal film comprises: depositing a tungsten metal film to the extent that the contact hole is sufficiently filled; And anisotropically etching the tungsten metal film to expose the oxide film. 제 5 항에 있어서, 상기 텅스텐 금속막은, 400 내지 450℃의 온도에서, WF6가스와 SiH4가스에 의하여, 전면성 텅스텐 금속막을 화학 기상 증착법에 의하여, 4000 내지 6000Å 두께로 형성하는 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.6. The tungsten metal film according to claim 5, wherein the tungsten metal film is formed to a thickness of 4000 to 6000 kW by a chemical vapor deposition method by WF 6 gas and SiH 4 gas at a temperature of 400 to 450 占 폚. A metal wiring forming method of a semiconductor device having a plug metal film. 제 1 항에 있어서, 상기 금속막을 증착하는 단계는, 상기 플러그 금속막 및 산화막 상부에 접촉 금속막을 증착하는 단계; 상기 접촉 금속막 상부에 알루미늄 합금막을 증착하는 단계; 상기 알루미늄 합금막 상부에 난반사 방지막을 형성하는 단계를 포함하는 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.The method of claim 1, wherein the depositing of the metal layer comprises: depositing a contact metal layer on the plug metal layer and the oxide layer; Depositing an aluminum alloy film on the contact metal film; Forming a diffuse reflection prevention film on the aluminum alloy film; and forming a metal wire of a semiconductor device having a plug metal film. 제 7 항에 있어서, 상기 접촉 금속막은 Ti 금속막인 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.8. The method for forming a metal wiring of a semiconductor device with a plug metal film according to claim 7, wherein said contact metal film is a Ti metal film. 제 7 항에 있어서, 상기 알루미늄 합금막은 Al-0.5%Cu, Al-1%Si-0.5%Cu, Al-1%Si중 하나의 막인 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.8. The metal wire formation of a semiconductor device with a plug metal film according to claim 7, wherein the aluminum alloy film is one of Al-0.5% Cu, Al-1% Si-0.5% Cu and Al-1% Si. Way. 제 7 항에 있어서, 상기 난반사 방지막은 질산화막인 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.8. The method for forming a metal wiring of a semiconductor device with a plug metal film according to claim 7, wherein the diffuse reflection prevention film is a nitrate film. 제 10 항에 있어서, 상기 난반사 방지막은, 상기 알루미늄 합금막 두께의 10 내지 20% 정도의 두께로 증착되는 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.The method of claim 10, wherein the diffuse reflection prevention film is deposited to a thickness of about 10 to 20% of the thickness of the aluminum alloy film. 제 7 항에 있어서, 상기 마스크 패턴을 이용하여, 상기 금속막을 패터닝하는 단계는, 상기 노출된 난반사 방지막은 모두 제거하고, 상기 알루미늄 합금막은 그 두께의 2분의 1 내지는 4분의 3만큼의 두께를 식각하는 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.The method of claim 7, wherein the patterning of the metal layer using the mask pattern comprises removing all of the exposed anti-reflective coating, and the aluminum alloy layer having a thickness of one half to three quarters of the thickness. The metal wiring forming method of the semiconductor device provided with the plug metal film characterized by etching. 제 7 항에 있어서, 상기 스페이서를 형성하는 단계에서, 상기 절연막은 상기 금속막의 난반사 방지막이 노출되도록 비등방성 식각하는 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.8. The method of claim 7, wherein in the forming of the spacer, the insulating layer is anisotropically etched to expose the diffuse reflection prevention layer of the metal layer. 9. 제 1 항에 있어서, 상기 절연막은 오정렬의 발생된 거리 보다 약 300 내지 500Å 정도 더 두껍게 증착하는 것을 특징으로 하는 플러그 금속막을 구비한 반도체 소자의 금속 배선 형성방법.2. The method of claim 1, wherein the insulating film is deposited about 300 to 500 Å thicker than the generated distance of misalignment.
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Publication number Priority date Publication date Assignee Title
KR100382730B1 (en) * 2000-12-14 2003-05-09 삼성전자주식회사 Metal contact structure in semiconductor device and forming method thereof
KR100441252B1 (en) * 2002-06-26 2004-07-21 삼성전자주식회사 Semiconductor interconnection structure and a method of forming the same
KR100935188B1 (en) * 2002-11-11 2010-01-06 매그나칩 반도체 유한회사 Method for manufacturing metal line in semiconductor device

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KR100772272B1 (en) 2005-12-27 2007-11-01 동부일렉트로닉스 주식회사 Method for manufacturing mosfet on semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100382730B1 (en) * 2000-12-14 2003-05-09 삼성전자주식회사 Metal contact structure in semiconductor device and forming method thereof
KR100441252B1 (en) * 2002-06-26 2004-07-21 삼성전자주식회사 Semiconductor interconnection structure and a method of forming the same
KR100935188B1 (en) * 2002-11-11 2010-01-06 매그나칩 반도체 유한회사 Method for manufacturing metal line in semiconductor device

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