KR19980060869A - Transistor Formation Method of Semiconductor Device - Google Patents
Transistor Formation Method of Semiconductor Device Download PDFInfo
- Publication number
- KR19980060869A KR19980060869A KR1019960080236A KR19960080236A KR19980060869A KR 19980060869 A KR19980060869 A KR 19980060869A KR 1019960080236 A KR1019960080236 A KR 1019960080236A KR 19960080236 A KR19960080236 A KR 19960080236A KR 19980060869 A KR19980060869 A KR 19980060869A
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- Prior art keywords
- semiconductor device
- forming
- thin film
- transistor
- film
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 230000015572 biosynthetic process Effects 0.000 title description 7
- 239000010408 film Substances 0.000 claims abstract description 31
- 239000010409 thin film Substances 0.000 claims abstract description 21
- 229910019001 CoSi Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 150000001875 compounds Chemical class 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229910015900 BF3 Inorganic materials 0.000 claims abstract description 4
- 229910052785 arsenic Inorganic materials 0.000 claims abstract description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims abstract description 4
- -1 boron fluoride ions Chemical class 0.000 claims abstract description 3
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 238000000313 electron-beam-induced deposition Methods 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 7
- 229910008484 TiSi Inorganic materials 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000003870 refractory metal Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910005329 FeSi 2 Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910017082 Fe-Si Inorganic materials 0.000 description 1
- 229910017133 Fe—Si Inorganic materials 0.000 description 1
- 229910004339 Ti-Si Inorganic materials 0.000 description 1
- 229910010978 Ti—Si Inorganic materials 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
Abstract
본 발명은 반도체 소자의 트랜지스터 형성방법에 관한 것으로, 반도체 기판에 소자 분리막, 게이트 산화막, 게이트, 절연막 스페이서를 형성하고 비소 또는 불화붕소 이온을 이온주입하여 n+ 또는 p+ 타입의 소오스/드레인을 형성하고 상기 구조의 전 표면에 Fe 박막을 증착한 다음, 상기 Fe 박막 상부에 연속적으로 Co 박막을 증착하고 상기 반도체 기판을 열처리하여 CoSi2막을 형성한 다음, 상기 열처리공정중 절연막 스페이서와 소자분리막 상부에 형성된 Fe-O-N의 화합물을 선택적으로 식각하여 불순물 접합영역과 게이트 표면에 균일하게 얇은 두께의 실리사이드를 형성함으로써 소자의 특성 및 신뢰성을 향상시키고 공정을 단순화시켜 반도체 소자의 수율 및 생산성을 향상시키며 그에 따른 반도체 소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device, comprising forming a device isolation film, a gate oxide film, a gate, an insulating film spacer on a semiconductor substrate, and implanting arsenic or boron fluoride ions to form an n + or p + type source / drain. After depositing a thin Fe film on the entire surface of the structure, and subsequently depositing a Co thin film on top of the Fe thin film and heat-treating the semiconductor substrate to form a CoSi 2 film, Fe formed on the insulating film spacer and the device isolation film during the heat treatment process By selectively etching the compound of -ON to form a uniformly thin silicide in the impurity junction region and the gate surface, improve the characteristics and reliability of the device, simplify the process to improve the yield and productivity of the semiconductor device, accordingly It is a technology that enables high integration.
Description
본 발명은 반도체 소자의 트랜지스터 형성방법에 관한 것으로, 특히 모스전계 효과 트랜지스터(MOSFET)를 제조하는데 있어서, 소오스/드레인 접합과 게이트 저항 값을 감소시켜 얕은 깊이의 접합을 형성할 수 있는 MOSFET 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor in a semiconductor device, and more particularly, to a MOSFET manufacturing method capable of forming a shallow depth junction by reducing a source / drain junction and a gate resistance value in manufacturing a MOSFET. It is about.
반도체 소자의 집적도 증가에 따른 얕은 깊이의 소오스/드레인 접합을 낮은 면저항을 갖도록 하는 것이 중요해지고 있다. 따라서 게이트와 소오스/드레인을 동시에 실리사이드(silicide)화하여 저 저항화하는 기술이 필수적이다.As the integration of semiconductor devices increases, it is important to make shallow source / drain junctions have low sheet resistance. Therefore, a technique for reducing resistance by silicideing the gate and the source / drain simultaneously is essential.
지금까지는 여러 금속 실리사이드 중에서 가장 비저항이 낮은 TiSi2가 주로 연구, 사용되어져 왔으나 앞으로 소자의 고밀도화가 더욱 진행되면 C49상에서 저저항의 안정한 C54상으로 상전이가 어려워지는 점, 게이트와 소오스/드레인(S/D) 간의 스페이서 산화막 위에서 TiSi2가 브릿지(bridge) 되어 전극들이 쉽게 단락되는 점, AS, B 등의 도펀트(dopant)와 화합물 형성으로 인한 접촉저항의 상승, 선폭이 좁아질 때 고온에서 쉽게 응집이 발생하는 점 등과 같은 문제가 발생한다.Until now, TiSi 2 , which has the lowest resistivity among various metal silicides, has been mainly studied and used, but as the device becomes more densified, it becomes difficult to transition from C 49 to low resistance, stable C 54 , gate and source / drain ( TiSi 2 is bridged on the spacer oxide film between S / D), and the electrodes are easily shorted, and the contact resistance is increased due to the formation of dopants and compounds such as A S and B, and the line width is narrowed at high temperature. Problems such as aggregation easily occur.
그러나, TiSi2보다 상대적으로 많은 장점을 가진 CoSi2공정도 단일층으로 형성시킬 경우 Si의 소모가 너무 크고, 실리사이드 공정 중에 침투하는 산소나 Si 표면에 남아있는 산소에 의해 막질이 급격히 저하되는 점, 자연산화막을 환원시킬 수 없기 때문에 계면에서의 불균일한 반응으로 인하여 실리사이드/Si계면이 매우 거칠어져 접촉저항이 상승하는 점 등으로 양산 공정에의 적용에 걸림돌이 되고 있다. 이러한 Co 단일막에 의한 문제를 극복하기 위해서 여러가지로 모색되고 있는 해결책 중에서 Co/Ti의 이중층구조를 통한 CoSi2형성이 제안된 바 있다. 여기서 Ti는 Co의 확산을 제어하고 표면의 자연산화막을 제거하는 역할을 하는 장점이 있는 반면, Ti이 Co 내에 고용되어 Co-Ti-Si의 삼성분계 화합물을 만들거나, 공정조건에 매우 민감하여 공정이 어렵다는 문제가 있다.However, the CoSi 2 process, which has more advantages than TiSi 2, is also consumed when Si is formed in a single layer, and the film quality is rapidly degraded by oxygen penetrating during the silicide process or oxygen remaining on the Si surface. Since the natural oxide film cannot be reduced, the silicide / Si interface becomes very rough due to the heterogeneous reaction at the interface, which increases the contact resistance, which is an obstacle to the application to the mass production process. In order to overcome the problems caused by the Co monolayer, CoSi 2 formation through a double layer structure of Co / Ti has been proposed. Here, Ti has the advantage of controlling the diffusion of Co and removing the natural oxide film on the surface, whereas Ti is dissolved in Co to form a tertiary compound of Co-Ti-Si or is very sensitive to process conditions. There is a problem that this is difficult.
상기한 바와 같이 종래 기술에 따른 반도체 소자의 트랜지스터 형성방법은, 많은 단점을 갖는 현상으로 인하여 소자의 특성 및 신뢰성을 저하시키고 반도체 소자의 수율 및 생산성을 저하시키며 그에 따른 반도체 소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, the method of forming a transistor of a semiconductor device according to the prior art has a problem that the characteristics and reliability of the device are deteriorated, the yield and productivity of the semiconductor device are deteriorated due to a phenomenon having many disadvantages, and thus, the integration of the semiconductor device is difficult. There is this.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위하여, 소오스/드레인 접합과 게이트 저항 값을 감소시켜 얕은 깊이의 접합을 형성할 수 있도록 하되, 한번의 열처리공정만을 이용하여 실시함으로써 공정을 단순화시켜 반도체 소자의 수율 및 생산성을 향상시키고 반도체 소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체 소자의 고집적화를 가능하게 하는 반도체 소자의 트랜지스터 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the source / drain junction and the gate resistance value can be reduced to form a shallow depth junction, but the process is simplified using only one heat treatment process to simplify the semiconductor process. It is an object of the present invention to provide a method for forming a transistor of a semiconductor device that improves the yield and productivity of the device, improves the characteristics and reliability of the semiconductor device, and thereby enables high integration of the semiconductor device.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 트랜지스터 형성방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a transistor forming method of a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1 : 반도체 기판2 : 소자분리막1: semiconductor substrate 2: device isolation film
3 : 게이트산화막4 : 게이트3: gate oxide film 4: gate
5 : 스페이서 산화막6 : 소오스/드레인5: spacer oxide film 6: source / drain
7 : Fe 박막8 : Co 박막7: Fe thin film 8: Co thin film
9 : CoSi2막10 : Fe-O-N의 화합물9: CoSi 2 film 10: compound of Fe-ON
이상의 목적을 달성하기 위해 본 발명에 따른 반도체 소자의 트랜지스터 형성방법은, 반도체 기판에 소자분리막, 게이트산화막, 게이트, 절연막 스페이서를 형성하고 비소 또는 불화붕소 이온을 이온주입하여 n+ 또는 p+ 타입의 소오스/드레인을 형성하는 단계와, 상기 구조의 전 표면에 Fe 박막을 증착하는 단계와, 상기 Fe 박막 상부에 연속적으로 Co 박막을 증착하는 단계와, 상기 반도체 기판을 열처리하여 CoSi2막을 형성하는 단계와, 상기 열처리공정중 절연막 스페이서와 소자분리막 상부에 형성된 Fe-O-N의 화합물을 선택적으로 식각하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention includes forming a device isolation film, a gate oxide film, a gate, an insulating film spacer on a semiconductor substrate, and implanting arsenic or boron fluoride ions to ion / n + or p + type source / Forming a drain, depositing a thin Fe film on the entire surface of the structure, depositing a Co thin film continuously on the Fe thin film, heat treating the semiconductor substrate to form a CoSi 2 film; And selectively etching the compound of Fe—ON formed on the insulating layer spacer and the device isolation layer during the heat treatment process.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, Co 단일막에 의한 CoSi2형성에서 발생할 수 있는 문제를 극복하기 위해서, Co/내화물금속의 이중층 구조에서 내화물 금속으로 Ti이 아닌 Fe를 사용하는 것으로, Co/Fe의 이중층에서 실리사이드 공정중 Fe는 Si 표면의 자연산화막을 환원시켜 제거함으로써 전 계면에 걸쳐 균일한 CoSi2반응이 일어나 매끈하고 평탄한 계면을 만들어 주며 중간에서 실리사이드 반응을 제어하여 Si의 지나친 소모를 방지하는 역할을 한다. 특히, Fe는 여러 내화물 금속 중에서도 산화 성향이 매우 커서 Si 표면의 자연산화막 제거 능력이 우수하고, Co 내부에 함유된 Fe의 고용도(solid solubility)도 매우 낮아 Co-Fe-Si의 삼성분계 화합물을 형성하지 않을 뿐 아니라, FeSi2의 형성 온도는 CoSi2의 형성온도보다 높은 편이므로, Co/Fe의 층역전을 통한 균일하고 얇은 CoSi2층 형성할 수 있다.On the other hand, the principle of the present invention for achieving the above object, in order to overcome the problems that can occur in the formation of CoSi 2 by Co single layer, in the bi-layer structure of Co / refractory metal using Fe rather than Ti as the refractory metal In the double layer of Co / Fe, Fe in the silicide process reduces and removes the natural oxide film on the surface of Si, resulting in a uniform CoSi 2 reaction over the entire interface to create a smooth and flat interface and control the silicide reaction in the middle. It prevents excessive consumption. Particularly, Fe has a high oxidation tendency among various refractory metals, so it has excellent ability to remove the natural oxide film on the surface of Si, and has a low solid solubility of Fe contained in Co. As well as not forming, since the formation temperature of FeSi 2 is higher than that of CoSi 2 , a uniform and thin CoSi 2 layer can be formed through layer reversal of Co / Fe.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 트랜지스터 형성방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체 기판(1)의 소자 분리 영역에 소자 분리막(2)을 형성하고, 반도체 기판의 액티브(active) 영역에 게이트산화막(3) 형성하고, 폴리 실리콘을 증착한 후 게이트 마스크(도시안됨)를 이용한 식각공정으로 식각하여 게이트(4)를 형성한다.First, the device isolation film 2 is formed in the device isolation region of the semiconductor substrate 1, the gate oxide film 3 is formed in the active region of the semiconductor substrate, and polysilicon is deposited, followed by a gate mask (not shown). The gate 4 is formed by etching by using an etching process.
그 다음, 상기 게이트(4)의 측벽에 산화막 스페이서(5)를 형성하고, 비소(AS) 또는 불화붕소(BF2) 이온을 3E15/㎤ 이상의 농도로 주입하여 n+또는 p-타입의 소오스/드레인(6)을 형성한다. (도 1a)Next, an oxide spacer 5 is formed on the sidewall of the gate 4, and arsenic (A S ) or boron fluoride (BF 2 ) ions are implanted at a concentration of 3E15 / cm 3 or more to provide an n + or p − type source. / Drain 6 is formed. (FIG. 1A)
그리고, 상기 구조의 전 표면에 Fe 박막(7)을 스퍼터링법이나 전자빔증착법을 이용하여 20~300Å 정도의 두께로 증착한다. 이때, 상기 스퍼터링법은 타겟을 고순도의 Fe 물질로 하되, N2(+Ar) 플라즈마 상태에서 증착 압력은 1 mTorr~10 Torr 정도로 하고, 기판 온도는 상온 ~500℃가 되도록 하여 실시한다.Then, the Fe thin film 7 is deposited on the entire surface of the structure to a thickness of about 20 to 300 mW using the sputtering method or the electron beam deposition method. At this time, the sputtering method is carried out by using a target of high purity Fe material, the deposition pressure in the N 2 (+ Ar) plasma state to about 1 mTorr ~ 10 Torr, the substrate temperature to room temperature ~ 500 ℃.
그 다음에, 상기 Fe 박막(7) 증착 후에 공기중에 노출하지 않고 연속적으로 Co 박막(8)을 80~500Å 정도의 두께 증착하되, 스퍼터링방법으로 증착하며 그 조건은, 타겟을 고순도의 Co로 하되, N2(+Ar) 플라즈마 상태에서 증착 압력은 1 mTorr~10 Torr 정도로 하며 기판 온도는 상온 ~500℃ 정도로 되도록 한다.Subsequently, after depositing the Fe thin film 7, the Co thin film 8 is continuously deposited to a thickness of about 80 to 500 mV without being exposed to air, but is deposited by a sputtering method. In the N 2 (+ Ar) plasma state, the deposition pressure is about 1 mTorr ~ 10 Torr and the substrate temperature is about room temperature ~ 500 ℃.
한편, 상기 Fe 박막(7)이나 Co 박막(8)을 전자빔 증착법을 이용하여 실시하는 경우는 기저진공을 1×10-5Torr 이하로 유지하면서 Fe와 Co 이중막을 연속적으로 형성한다. (도 1b)On the other hand, in the case where the Fe thin film 7 or the Co thin film 8 is carried out by the electron beam evaporation method, the Fe and Co double films are continuously formed while maintaining the base vacuum at 1 × 10 −5 Torr or less. (FIG. 1B)
그 다음에, 상기의 Co 박막(8)을 500~800℃ 정도의 온도에서 0~60초 정도의 시간동안 RTA(Rapid Thermal Annal)를 0.1 Torr 이하의 압력, 질소 분위기에서 열처리하거나, 퍼니스(Furnace)를 사용하여 400~700℃ 정도의 온도에서 0~30분 정도의 시간동안 질소분위기에서 열처리함으로써 소오스/드레인(6)과 게이트(4) 전극 위에만 선택적으로 CoSi2(9)를 형성한다.Then, the Co thin film 8 is heat-treated in a nitrogen atmosphere at a pressure of 0.1 Torr or less for RTA (Rapid Thermal Annal) at a temperature of about 500 to 800 ° C. for 0 to 60 seconds. CoSi 2 (9) is selectively formed only on the source / drain (6) and gate (4) electrodes by heat treatment in a nitrogen atmosphere at a temperature of about 400 to 700 ° C. for about 0 to 30 minutes.
이때, 상기 스페이서 산화막(5)이나 소자 분리막(2)은 표면에 Fe-O-N(10)의 화합물이 존재하게 된다. (도 1c)At this time, the spacer oxide film 5 or the device isolation film 2 is a compound of Fe-O-N (10) is present on the surface. (FIG. 1C)
그 다음에, 상기 Fe-O-N(10)의 화합물은 NH4OH : H2O : H2O = 1 : 1 : 5의 구성비를 갖는 SC-1이나 HCl과 H2O2의 혼합용액으로 20~60분 정도의 시간동안 선택적으로 식각하여 상기 소오스/드레인(6)과 게이트(5) 위에만 CoSi2(9)가 형성되도록 한다. (도 1d)Next, the compound of Fe-ON (10) is a mixture of SC-1 or HCl and H 2 O 2 having a composition ratio of NH 4 OH: H 2 O: H 2 O = 1: 1: 5 20 Selectively etching for a time of about 60 minutes so that CoSi 2 (9) is formed only on the source / drain (6) and the gate (5). (FIG. 1D)
이 후에 층간 절연막을 증착하여 평탄화시키고 콘택을 오픈한 후에 금속으로 콘택을 메꾸는 등의 기존의 반도체 공정 그대로 후속 공정을 진행한다.Thereafter, the interlayer insulating film is deposited to be planarized, the contact is opened, and then the contact is filled with metal, and the subsequent process is performed as it is.
이상에서 설명한 바와 같이 본 발명에 따른 반도체 소자의 트랜지스터 형성방법은, 여러 내화물 금속 중에서도 산화 성향이 매우 큰 Fe금속을 사용하여 Si 표면의 자연산화막을 환원시켜 제거함으로써 전 계면에 걸쳐 균일한 CoSi2반응이 일어나 매끈하고 평탄한 계면을 만들어 주며, Co 내의 고용도도 매우 낮아 Co-Fe-Si의 삼성분계 화합물을 형성하지 않는 Fe를 사용하여 CoSi2의 두께를 균일하게 형성할 수 있도록 하고, CoSi2의 형성온도보다 높은 FeSi2의 형성을 추구하여 형성공정시 Si의 소모량이 감소시킨다. 그리고, TiSi2형성공정시 사용되는 다단계의 열처리공정을 한단계의 열처리공정으로 감소하여 공정을 단순화시킨다. 상기와 같은 현상들로 인하여 본 발명은 반도체 소자의 수율 및 생산성을 향상시키고 반도체 소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체 소자의 고집적화를 가능하게 하는 효과가 있다.As described above, in the method of forming a transistor of a semiconductor device according to the present invention, the CoSi 2 reaction is uniform over the entire interface by reducing and removing the natural oxide film on the surface of Si using Fe metal having a very high oxidation tendency among various refractory metals. gives the up and create a smooth, flat surface, and is also employed in the Co also uses Fe does not form a ternary compound of a very low Co-Fe-Si, and to uniformly form the thickness of the CoSi 2, the CoSi 2 The consumption of Si in the forming process is reduced by pursuing the formation of FeSi 2 higher than the forming temperature. In addition, the multi-stage heat treatment process used in the TiSi 2 formation process is reduced to a single heat treatment process to simplify the process. Due to the phenomena as described above, the present invention has the effect of improving the yield and productivity of the semiconductor device, improving the characteristics and reliability of the semiconductor device, and thereby enabling high integration of the semiconductor device.
Claims (12)
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| KR1019960080236A KR100224785B1 (en) | 1996-12-31 | 1996-12-31 | Method of manufacturing transistor of semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100395776B1 (en) * | 2001-06-28 | 2003-08-21 | 동부전자 주식회사 | Method for manufacturing a silicide layer of semiconductor device |
| KR20040001455A (en) * | 2002-06-28 | 2004-01-07 | 주식회사 하이닉스반도체 | Method for forming mask pattern of semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100395776B1 (en) * | 2001-06-28 | 2003-08-21 | 동부전자 주식회사 | Method for manufacturing a silicide layer of semiconductor device |
| KR20040001455A (en) * | 2002-06-28 | 2004-01-07 | 주식회사 하이닉스반도체 | Method for forming mask pattern of semiconductor device |
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