KR19980030876U - Ceramic chip capacitors - Google Patents
Ceramic chip capacitors Download PDFInfo
- Publication number
- KR19980030876U KR19980030876U KR2019960044022U KR19960044022U KR19980030876U KR 19980030876 U KR19980030876 U KR 19980030876U KR 2019960044022 U KR2019960044022 U KR 2019960044022U KR 19960044022 U KR19960044022 U KR 19960044022U KR 19980030876 U KR19980030876 U KR 19980030876U
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- South Korea
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- ceramic
- covers
- chip capacitor
- external electrodes
- external
- Prior art date
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- 239000000919 ceramic Substances 0.000 title claims abstract description 61
- 239000003990 capacitor Substances 0.000 title claims abstract description 22
- 238000004049 embossing Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
본 고안은 제 1, 2 세라믹 커버 사이에 복수개의 내부 전극과 세라믹 유전체가 교대로 적층 형성되고, 상기 제 1, 2 세라믹 커버의 양단부에 외부 전극이 각각 형성된 세라믹 칩 커패시터에 있어서, 상기 제 1, 2 세라믹 커버 중 상기 외부 전극과의 접촉면에 물결무늬의 요철이 전체적으로 형성된 세라믹 칩 커패시터에 관한 것으로서, 제 1, 2 세라믹 커버에 형성된 물결무늬의 요철 위에 외부 전극이 형성되기 때문에 제 1, 2 세라믹 커버와 외부 전극의 접촉 면적이 넓어져서 상호 접착력이 강해짐으로써 외부 전극의 박리가 방지되고, 상기 요철로 인해 외부 전극 사이의 거리가 증가됨으로써 표면 누설 전류의 발생이 억제되는 효과가 있다.The present invention provides a ceramic chip capacitor in which a plurality of internal electrodes and a ceramic dielectric are alternately stacked between first and second ceramic covers, and external electrodes are formed at both ends of the first and second ceramic covers, respectively. The present invention relates to a ceramic chip capacitor in which wavy irregularities are formed on the contact surface with the external electrodes among the two ceramic covers, and the first and second ceramic covers are formed because the external electrodes are formed on the wavy irregularities formed in the first and second ceramic covers. The contact area between the external electrode and the external electrode becomes wider, and the mutual adhesive force is increased, thereby preventing peeling of the external electrode, and the distance between the external electrodes increases due to the unevenness, thereby suppressing the occurrence of surface leakage current.
Description
본 고안은 세라믹 칩 커패시터에 관한 것으로서, 특히 제 1, 2 세라믹 커버의 양면 중 외부 전극과의 접촉면에 물결무늬의 요철이 전체적으로 형성된 세라믹 칩 커패시터에 관한 것이다.The present invention relates to a ceramic chip capacitor, and more particularly, to a ceramic chip capacitor in which wavy irregularities are formed on a contact surface with an external electrode among both surfaces of the first and second ceramic covers.
종래 기술에 의한 세라믹 칩 커패시터는 도 1 및 도 2에 도시된 바와 같이 표면이 매끈한 제 1, 2 세라믹 커버(51a, 51b) 사이에 복수개의 내부 전극(52)과 세라믹 유전체(53)가 교대로 적층 형성되고, 그 양단부에 외부 전극(54a, 54b)이 각각 형성되어 있다.In the ceramic chip capacitor according to the related art, as illustrated in FIGS. 1 and 2, a plurality of internal electrodes 52 and ceramic dielectrics 53 are alternately disposed between the first and second smooth ceramic covers 51a and 51b. Laminated | stacked and the external electrode 54a, 54b is formed in the both ends, respectively.
상기에서 복수개의 내부 전극(52)은 도 3에 도시된 바와 같이 각 세라믹 유전체(53) 위에 T 자형으로 형성되고, T 자의 머리부분(52a)이 번갈아 도면상 좌측 및 우측 방향으로 향하도록 형성된다.As shown in FIG. 3, the plurality of internal electrodes 52 are formed in a T shape on each ceramic dielectric 53, and the heads 52a of the T shapes are alternately directed in the left and right directions in the drawing. .
또한, 상기 외부 전극(54a, 54b)은 제 1, 2 세라믹 커버(51a, 51b)의 양단부에 연질 상태로 끼워진 다음 800℃ 정도의 온도에서 소성되어 형성된다.In addition, the external electrodes 54a and 54b are formed in a soft state at both ends of the first and second ceramic covers 51a and 51b and then fired at a temperature of about 800 ° C.
그러나, 종래 기술에 의한 세라믹 칩 커패시터는 외부 전극의 소성시 온도 변화가 발생하거나, 내부 전극 또는 세라믹 유전체와 분위기가 맞지 않으면 제 1, 2 세라믹 커버와 외부 전극의 접착력이 약화되어 외부 전극이 제 1, 2 세라믹 커버로부터 분리되는 외부 전극의 박리 현상이 발생하는 문제점이 있었다.However, in the ceramic chip capacitor according to the related art, when the temperature change occurs during firing of the external electrode, or when the atmosphere does not match with the internal electrode or the ceramic dielectric, the adhesion between the first and second ceramic covers and the external electrode is weakened, and thus the external electrode is the first electrode. , 2 has a problem in that the peeling phenomenon of the external electrode separated from the ceramic cover occurs.
또한, 최근 들어 세라믹 칩 커패시터가 점점 소형화되어 감에 따라 제 1, 2 세라믹 커버 양단부에 형성되는 외부 전극 사이의 거리도 점점 짧아져서 외부 전극 사이에 미소한 표면 누설 전류가 흐르는 문제점이 있었다.In addition, in recent years, as the ceramic chip capacitors have been miniaturized, the distance between the external electrodes formed at both ends of the first and second ceramic covers is also shortened, so that a small surface leakage current flows between the external electrodes.
본 고안은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 제 1, 2 세라믹 커버의 양면 중 외부 전극과의 접촉면에 물결무늬의 요철을 전체적으로 형성하여 상기 제 1, 2 세라믹 커버와 외부 전극의 접촉 면적을 넓힘과 동시에 외부 전극 사이의 거리를 증가시킴으로써 외부 전극의 박리가 방지되고, 표면 누설 전류의 발생이 억제되는 세라믹 칩 커패시터를 제공함에 그 목적이 있다.The present invention has been made in order to solve the above problems, the contact between the first and second ceramic cover and the external electrode by forming a wavy irregularities on the contact surface of the first and second ceramic cover with the external electrode as a whole. It is an object of the present invention to provide a ceramic chip capacitor in which the peeling of the external electrode is prevented and the occurrence of surface leakage current is suppressed by increasing the area and increasing the distance between the external electrodes.
도 1은 종래 기술에 의한 세라믹 칩 커패시터의 사시도,1 is a perspective view of a ceramic chip capacitor according to the prior art,
도 2는 종래 기술에 의한 세라믹 칩 커패시터의 측단면도,2 is a side cross-sectional view of a ceramic chip capacitor according to the prior art;
도 3은 종래 기술에 의한 세라믹 칩 커패시터의 분해 사시도,3 is an exploded perspective view of a ceramic chip capacitor according to the prior art;
도 4는 본 고안의 일 실시예에 의한 세라믹 칩 커패시터의 사시도,4 is a perspective view of a ceramic chip capacitor according to an embodiment of the present invention;
도 5는 본 고안의 일 실시예에 의한 세라믹 칩 커패시터의 측단면도,5 is a side cross-sectional view of a ceramic chip capacitor according to an embodiment of the present invention;
도 6은 본 고안의 제 1, 2 세라믹 커버가 엠보싱(embossing) 가공되는 것을 나타내는 도면.FIG. 6 shows that the first and second ceramic covers of the present invention are embossed. FIG.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1a, 1b: 제 1, 2 세라믹 커버 2: 내부 전극1a, 1b: first and second ceramic covers 2: internal electrodes
3: 세라믹 유전체 4a, 4b: 외부 전극3: ceramic dielectric 4a, 4b: external electrode
상기와 같은 목적을 달성하기 위하여 본 고안에 의한 세라믹 칩 커패시터는 제 1, 2 세라믹 커버 사이에 복수개의 내부 전극과 세라믹 유전체가 교대로 적층 형성되고, 상기 제 1, 2 세라믹 커버의 양단부에 외부 전극이 각각 형성된 세라믹 칩 커패시터에 있어서, 상기 제 1, 2 세라믹 커버의 양면 중 상기 외부 전극과의 접촉면에 물결무늬의 요철이 전체적으로 형성된 것을 특징으로 한다.In order to achieve the above object, in the ceramic chip capacitor according to the present invention, a plurality of internal electrodes and a ceramic dielectric are alternately formed between first and second ceramic covers, and external electrodes are formed at both ends of the first and second ceramic covers. In each of the formed ceramic chip capacitors, wave-shaped irregularities are formed on the contact surfaces of the first and second ceramic covers with the external electrodes as a whole.
또한, 본 고안의 실시예에 의하면 상기 물결무늬의 요철은 엠보싱(embossing) 가공되어 형성되는 것이 바람직하다.In addition, according to an embodiment of the present invention, the irregularities of the wave pattern is preferably formed by embossing (embossing) process.
이하, 본 고안에 의한 세라믹 칩 커패시터의 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings an embodiment of a ceramic chip capacitor according to the present invention will be described in detail.
본 고안의 일 실시예에 의한 세라믹 칩 커패시터는 도 4 및 도 5에 도시된 바와 같이 제 1, 2 세라믹 커버(1a, 1b) 사이에 복수개의 내부 전극(2)과 세라믹 유전체(3)가 교대로 적층 형성되고, 그 양단부에 외부 전극(4a, 4b)이 각각 형성되어 있으며, 상기 제 1, 2 세라믹 커버(1a, 1b)의 양면 중 상기 외부 전극(4a, 4b)과의 접촉면에 물결무늬의 요철이 전체적으로 형성되어 있다.In the ceramic chip capacitor according to the exemplary embodiment of the present invention, as illustrated in FIGS. 4 and 5, the plurality of internal electrodes 2 and the ceramic dielectric 3 are alternated between the first and second ceramic covers 1a and 1b. The external electrodes 4a and 4b are formed at both ends thereof, respectively, and wavy patterns are formed on contact surfaces with the external electrodes 4a and 4b of both surfaces of the first and second ceramic covers 1a and 1b. Unevenness is formed as a whole.
상기에서 복수개의 내부 전극(2)은 종래 기술과 마찬가지로 각 세라믹 유전체(3) 위에 T 자형으로 형성되고, T 자의 머리부분이 번갈아 도면상 좌측 및 우측 방향으로 향하도록 형성된다.As described above, the plurality of internal electrodes 2 are formed in a T-shape on each ceramic dielectric 3 as in the prior art, and the heads of the T-shaped are alternately formed in the left and right directions in the drawing.
또한, 상기 외부 전극(4a, 4b) 역시 제 1, 2 세라믹 커버(1a, 1b)의 양단부에 연질 상태로 끼워진 다음 800℃ 정도의 온도에서 소성되어 형성된다.In addition, the external electrodes 4a and 4b are also formed in the soft state at both ends of the first and second ceramic covers 1a and 1b and then fired at a temperature of about 800 ° C.
한편, 상기 제 1, 2 세라믹 커버(1a, 1b)의 외부면에 각각 형성되는 물결무늬의 요철은 도 6에 도시된 바와 같이 압착 전사를 위한 물결무늬의 요철(10a, 11a)이 형성되어 있는 플레이트(10, 11)를 이용한 엠보싱 가공에 의해 형성된다. 그 후, 상기 제 1, 2 세라믹 커버(1a, 1b)의 양단부에 외부 전극(4a, 4b)이 형성된다.Meanwhile, as shown in FIG. 6, the wavy irregularities formed on the outer surfaces of the first and second ceramic covers 1a and 1b are provided with wavy irregularities 10a and 11a for compression transfer. It is formed by the embossing process using the plates 10 and 11. Thereafter, external electrodes 4a and 4b are formed at both ends of the first and second ceramic covers 1a and 1b.
상기와 같이 제 1, 2 세라믹 커버(1a, 1b)에 형성된 물결무늬의 요철 위에 외부 전극(4a, 4b)이 형성되면 상기 제 1, 2 세라믹 커버(1a, 1b)와 외부 전극(4a, 4b)의 접촉 면적이 넓어져서 상호 접착력이 강해짐으로써 외부 전극(4a, 4b)의 박리가 방지되고, 아울러 요철에 의해 외부 전극(4a, 4b)의 박리가 방지된다.As described above, when the external electrodes 4a and 4b are formed on the wavy irregularities formed on the first and second ceramic covers 1a and 1b, the first and second ceramic covers 1a and 1b and the external electrodes 4a and 4b are formed. ), The contact area of the electrode becomes wider, and the mutual adhesive force becomes stronger, thereby preventing peeling of the external electrodes 4a and 4b, and preventing peeling of the external electrodes 4a and 4b by unevenness.
아울러, 제 1, 2 세라믹 커버(1a, 1b)의 외부면에 형성된 다수의 요철로 인해 외부 전극(4a, 4b) 사이의 거리가 증가됨으로써 표면 누설 전류의 발생이 억제된다.In addition, the distance between the external electrodes 4a and 4b is increased due to a plurality of irregularities formed on the outer surfaces of the first and second ceramic covers 1a and 1b, thereby suppressing the occurrence of surface leakage current.
이와 같이 본 고안에 의한 세라믹 칩 커패시터는 제 1, 2 세라믹 커버에 형성된 물결무늬의 요철 위에 외부 전극이 형성되기 때문에 제 1, 2 세라믹 커버와 외부 전극의 접촉 면적이 넓어져서 상호 접착력이 강해짐으로써 외부 전극의 박리가 방지되고, 상기 요철로 인해 외부 전극 사이의 거리가 증가됨으로써 표면 누설 전류의 발생이 억제되는 효과가 있다.As described above, in the ceramic chip capacitor according to the present invention, since the external electrode is formed on the wavy irregularities formed on the first and second ceramic covers, the contact area between the first and second ceramic covers and the external electrodes is widened, thereby increasing the mutual adhesive strength. The peeling of the electrode is prevented, and the distance between the external electrodes is increased due to the unevenness, thereby suppressing the occurrence of surface leakage current.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960044022U KR19980030876U (en) | 1996-11-29 | 1996-11-29 | Ceramic chip capacitors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960044022U KR19980030876U (en) | 1996-11-29 | 1996-11-29 | Ceramic chip capacitors |
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| Publication Number | Publication Date |
|---|---|
| KR19980030876U true KR19980030876U (en) | 1998-08-17 |
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|---|---|---|---|
| KR2019960044022U KR19980030876U (en) | 1996-11-29 | 1996-11-29 | Ceramic chip capacitors |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101384035B1 (en) * | 1999-09-02 | 2014-04-09 | 이비덴 가부시키가이샤 | Printed circuit board and method of manufacturing printed circuit board |
| KR101422938B1 (en) * | 2012-12-04 | 2014-07-23 | 삼성전기주식회사 | Embedded multilayer capacitor and method of manufacturing thereof, print circuit board having embedded multilayer capacitor |
| CN115083774A (en) * | 2021-03-16 | 2022-09-20 | 株式会社村田制作所 | Multilayer ceramic capacitor |
-
1996
- 1996-11-29 KR KR2019960044022U patent/KR19980030876U/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101384035B1 (en) * | 1999-09-02 | 2014-04-09 | 이비덴 가부시키가이샤 | Printed circuit board and method of manufacturing printed circuit board |
| KR101422938B1 (en) * | 2012-12-04 | 2014-07-23 | 삼성전기주식회사 | Embedded multilayer capacitor and method of manufacturing thereof, print circuit board having embedded multilayer capacitor |
| CN115083774A (en) * | 2021-03-16 | 2022-09-20 | 株式会社村田制作所 | Multilayer ceramic capacitor |
| CN115083774B (en) * | 2021-03-16 | 2023-10-20 | 株式会社村田制作所 | Laminated ceramic capacitor |
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