JP2784863B2 - Multilayer capacitors - Google Patents
Multilayer capacitorsInfo
- Publication number
- JP2784863B2 JP2784863B2 JP4257374A JP25737492A JP2784863B2 JP 2784863 B2 JP2784863 B2 JP 2784863B2 JP 4257374 A JP4257374 A JP 4257374A JP 25737492 A JP25737492 A JP 25737492A JP 2784863 B2 JP2784863 B2 JP 2784863B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- internal
- electrodes
- wide
- narrow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Description
【０００１】[0001]
【産業上の利用分野】本発明は奇数個の内部電極を有す
る積層コンデンサに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor having an odd number of internal electrodes.
【０００２】[0002]
【従来の技術】積層コンデンサにおいて内部電極のパタ
ーンずれに基づく容量変化を防ぐために対向する対の内
部電極の内の一方を幅狭に形成することがある。図１２
及び図１３はこの種の積層コンデンサを示す。図１２及
び図１３において磁器誘電体１の中に設けられた第１の
内部電極２は第２の内部電極３よりも幅広に形成されて
いる。この例では幅広の第１の内部電極２が２枚設けら
れ、誘電体１の第１の側面４の第１の外部電極５にそれ
ぞれ接続されている。幅狭の第２の内部電極３は第２の
側面６の第２の外部電極７に接続されている。積層コン
デンサをこの様に構成すると、積層時において第１の内
部電極２と第２の内部電極３との間に多少のパターンず
れが生じても第１の内部電極２と第２の内部電極３との
対向面積を一定に維持することができ、容量変化が生じ
ない。2. Description of the Related Art In a multilayer capacitor, one of a pair of opposing internal electrodes may be formed to be narrow in order to prevent a capacitance change due to a pattern shift of the internal electrodes. FIG.
FIG. 13 shows such a multilayer capacitor. In FIGS. 12 and 13, the first internal electrode 2 provided in the ceramic dielectric 1 is formed wider than the second internal electrode 3. In this example, two wide first internal electrodes 2 are provided and connected to the first external electrodes 5 on the first side surface 4 of the dielectric 1, respectively. The narrow second internal electrode 3 is connected to the second external electrode 7 on the second side surface 6. When the multilayer capacitor is configured in this manner, the first internal electrode 2 and the second internal electrode 3 are connected even if a slight pattern shift occurs between the first internal electrode 2 and the second internal electrode 3 during lamination. Can be maintained constant, and no change in capacitance occurs.
【０００３】[0003]
【発明が解決しようとする課題】ところで、図１２に示
すような積層コンデンサを材料の節約を図るように量産
すると、図１３と図１４とに示す２種類の構成の積層コ
ンデンサが生じる。図１４の積層コンデンサは１枚の幅
広の内部電極２と２枚の幅狭の内部電極３とから成るの
で、電極間の等電位分布曲線が図１３と異なる。この結
果、図１３と図１４の２種類の積層コンデンサの容量値
に相違が生じる。なお、内部電極の積層数が偶数の場合
には上述のような問題が生じないが、要求される容量及
び寸法等の関係で積層数を奇数にすることが必要にな
る。When a multilayer capacitor as shown in FIG. 12 is mass-produced so as to save material, two types of multilayer capacitors as shown in FIGS. 13 and 14 are produced. Since the multilayer capacitor of FIG. 14 includes one wide internal electrode 2 and two narrow internal electrodes 3, the equipotential distribution curve between the electrodes differs from that of FIG. As a result, the capacitance values of the two types of multilayer capacitors shown in FIGS. 13 and 14 differ. Note that the above-mentioned problem does not occur when the number of stacked internal electrodes is even, but the number of stacked electrodes needs to be odd due to the required capacity and dimensions.
【０００４】図１３と図１４の２種類の積層コンデンサ
が生じる理由を次に説明する。積層コンデンサを製造す
る場合には、同一のグリーンシートの上に第１の内部電
極２のための導電層パターンと第２の内部電極３のため
の導電層パターンとを同一のスクリーンを使用して同時
に印刷するのが一般的である。この様に印刷すれば、第
１及び第２の内部電極２、３の厚み等を同一にすること
ができ、容量のバラツキを抑制することができる。第１
及び第２の内部電極２、３を同時に印刷する方法におい
て、図１３の構造のみの積層コンデンサを作製すれば、
第２の内部電極３を有するグリーンシートが１枚余り、
不経済になる。また、図１４の構造のみの積層コンデン
サを作製すれば、第１の内部電極２のグリーンシートの
みが１枚余り、不経済になる。そこで、すべてのグリー
ンシートを使用すれば、必然的に図１３及び図１４の２
種類の積層コンデンサが生じる。The reason why the two types of multilayer capacitors shown in FIGS. 13 and 14 occur will be described below. When manufacturing a multilayer capacitor, a conductive layer pattern for the first internal electrode 2 and a conductive layer pattern for the second internal electrode 3 are formed on the same green sheet using the same screen. It is common to print at the same time. By printing in this manner, the thickness and the like of the first and second internal electrodes 2 and 3 can be made equal, and variation in capacitance can be suppressed. First
In the method of printing the second internal electrodes 2 and 3 simultaneously, if a multilayer capacitor having only the structure of FIG. 13 is manufactured,
More than one green sheet having the second internal electrode 3,
It becomes uneconomical. In addition, if a multilayer capacitor having only the structure of FIG. 14 is manufactured, only one green sheet of the first internal electrode 2 is left, which is uneconomical. Therefore, if all the green sheets are used, it is inevitable that the green sheet shown in FIG. 13 and FIG.
There are different types of multilayer capacitors.
【０００５】本発明の目的は、図１３及び図１４の２種
類の積層コンデンサの容量のバラツキを抑制することが
できる積層コンデンサを提供することにある。An object of the present invention is to provide a multilayer capacitor capable of suppressing variations in capacitance between the two types of multilayer capacitors shown in FIGS.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
の本発明は、互いに対向する第１及び第２の側面を有す
る誘電体と、前記誘電体の内部の互いに平行な３以上の
奇数個の仮想平面にそれぞれ設けられた奇数個の内部電
極と、前記第１の側面に形成され且つ前記奇数個の内部
電極の内の奇数番目の第１の内部電極に接続された第１
の外部電極と、前記第２の側面に形成され且つ前記奇数
個の内部電極の内の偶数番目の第２の内部電極に接続さ
れた第２の外部電極とを備えた積層コンデンサにおい
て、前記第１及び第２の内部電極が幅広電極と幅狭電極
とからそれぞれなり、前記第１の内部電極の幅広電極が
前記第２の内部電極の幅狭電極に対向し、前記第１の内
部電極の幅狭電極が前記第２の内部電極の幅広電極に対
向していることを特徴とする積層コンデンサに係わるも
のである。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a dielectric having first and second side surfaces facing each other, and an odd number of three or more parallel dielectrics inside the dielectric. An odd number of internal electrodes respectively provided on the virtual plane, and a first internal electrode formed on the first side face and connected to an odd-numbered first internal electrode of the odd number of internal electrodes.
And a second external electrode formed on the second side surface and connected to an even-numbered second internal electrode of the odd number of internal electrodes. The first and second internal electrodes each include a wide electrode and a narrow electrode, and the wide electrode of the first internal electrode faces the narrow electrode of the second internal electrode, and The present invention relates to a multilayer capacitor, wherein a narrow electrode faces a wide electrode of the second internal electrode.
【０００７】[0007]
【作用及び効果】本発明に従う積層コンデンサは、幅広
電極、幅狭電極、幅広電極の順に積層された第１の部分
と、幅狭電極、幅広電極、幅狭電極の順に積層された第
２の部分とを含む。この第１及び第２の部分は、第１及
び第２の内部電極の積層順番を変えても生じる。従っ
て、奇数個の内部電極を有する積層コンデンサを経済的
に量産する時に生じる内部電極の積層順番の異なる２種
類の積層コンデンサにおける容量のバラツキを少なくす
ることができる。The multilayer capacitor according to the present invention has a first portion laminated in the order of a wide electrode, a narrow electrode and a wide electrode, and a second portion laminated in the order of a narrow electrode, a wide electrode and a narrow electrode. And parts. The first and second portions are generated even when the stacking order of the first and second internal electrodes is changed. Accordingly, it is possible to reduce variations in capacitance between two types of multilayer capacitors having different internal electrode stacking orders, which are caused when economically mass-producing a multilayer capacitor having an odd number of internal electrodes.
【０００８】[0008]
【実施例】次に、図１〜図９を参照して本発明の実施例
に係わる積層コンデンサ及びこの製造方法を説明する。
図１〜図６に示す積層コンデンサは、図１２の従来の積
層コンデンサと同様に、磁器誘電体１と、幅広の２枚の
第１の内部電極２と、幅狭の１枚の第２の内部電極３
と、対向する第１及び第２の側面４、６に設けられた第
１及び第２の外部電極５、７とから成る。Next, a multilayer capacitor according to an embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS.
The multilayer capacitor shown in FIGS. 1 to 6 has a ceramic dielectric 1, two wide first internal electrodes 2, and a narrow one second electrode, like the conventional multilayer capacitor of FIG. Internal electrode 3
And first and second external electrodes 5 and 7 provided on the first and second side surfaces 4 and 6 facing each other.
【０００９】３個（奇数個）の内部電極２、３は図２の
Ａ−Ａ線における第１の仮想平面と、Ｂ−Ｂ線の第２の
仮想平面と、Ｃ−Ｃ線の第３の仮想平面とにそれぞれ配
置されている。第１、第２、第３の仮想平面は互いに平
行であり、且つ直方体の誘電体１の両主面に対しても平
行である。図３、図４及び図５は第１、第２及び第３の
仮想平面における内部電極２、３のパターンを示す。The three (odd-numbered) internal electrodes 2 and 3 correspond to a first virtual plane of the line AA in FIG. 2, a second virtual plane of the line BB, and a third virtual plane of the line CC. And a virtual plane. The first, second, and third virtual planes are parallel to each other, and are also parallel to both main surfaces of the rectangular parallelepiped dielectric 1. FIGS. 3, 4 and 5 show patterns of the internal electrodes 2 and 3 in the first, second and third virtual planes.
【００１０】図２のＡ−Ａ線の第１の仮想平面には図３
に示すように第１の内部電極２として幅Ｗ1 の幅広電極
２１とＷ1 よりも狭い幅Ｗ2 の幅狭電極２２とが設けら
れている。図２のＢ−Ｂ線の第２の仮想平面には図４に
示すように第２の内部電極３として幅Ｗ1 の幅広電極３
１と幅Ｗ2 の幅狭電極３２とが設けられている。図２の
Ｃ−Ｃ線の第３の仮想平面には図５に示すように第１の
内部電極２として幅Ｗ1 の幅広電極２１と幅Ｗ2 の幅狭
電極２２が設けられている。図３及び図５の第１の内部
電極２の幅広電極２１及び幅狭電極２２は第１の外部電
極５にそれぞれ接続されている。図４の第２の内部電極
３の幅広電極３１及び幅狭電極３２は第２の外部電極７
にそれぞれ接続されている。図３から明らかなように、
第１の内部電極２の幅広電極２１が第２の内部電極３の
幅狭電極３２に対向し、第１の内部電極２の幅狭電極２
２が第２の内部電極３の幅広電極３２に対向している。
仮想平面に対して垂直な方向から見た時に幅広電極２
１、３１の中に幅狭電極２２、３２の両側縁が含まれる
ように配置されているので、第１及び第２の内部電極
２、３の幅方向のずれが生じても対向面積の変化が発生
せず、容量の変化が生じない。FIG. 3 shows a first imaginary plane taken along line AA in FIG.
As shown in FIG. 1, a wide electrode 21 having a width W1 and a narrow electrode 22 having a width W2 smaller than W1 are provided as the first internal electrodes 2. As shown in FIG. 4, a wide electrode 3 having a width W1 is formed on a second imaginary plane of the line BB in FIG.
1 and a narrow electrode 32 having a width W2. As shown in FIG. 5, a wide electrode 21 having a width W1 and a narrow electrode 22 having a width W2 are provided as the first internal electrodes 2 on a third imaginary plane of the line CC in FIG. The wide electrode 21 and the narrow electrode 22 of the first internal electrode 2 in FIGS. 3 and 5 are connected to the first external electrode 5 respectively. The wide electrode 31 and the narrow electrode 32 of the second internal electrode 3 of FIG.
Connected to each other. As is clear from FIG.
The wide electrode 21 of the first internal electrode 2 faces the narrow electrode 32 of the second internal electrode 3 and the narrow electrode 2 of the first internal electrode 2
2 faces the wide electrode 32 of the second internal electrode 3.
Wide electrode 2 when viewed from the direction perpendicular to the virtual plane
Since the first and second internal electrodes 2 and 3 are arranged so as to include both side edges of the narrow electrodes 22 and 32 in the first and second electrodes 31, the facing area changes even if the first and second internal electrodes 2 and 3 are shifted in the width direction. Does not occur and the capacitance does not change.
【００１１】内部電極の積層数を奇数個にすると、図１
３及び図１４に対応して図６及び図７の２種類の積層コ
ンデンサが得られる。しかし、図６の左半分と図７の右
半分とは幅広電極、幅狭電極、幅広電極から成る同一構
成であり、図６の右半分と図７の左半分とは幅狭電極、
幅広電極、幅狭電極から成る同一構成である。従って、
図６及び図７の積層コンデンサは実質的に同一構成であ
り、理想的には容量値が同一になる。このため、奇数個
の内部電極の積層順番の相違による容量のバラツキが発
生しない。When the number of laminated internal electrodes is odd, FIG.
6 and 7 corresponding to FIGS. 3 and 14 are obtained. However, the left half of FIG. 6 and the right half of FIG. 7 have the same configuration including a wide electrode, a narrow electrode, and a wide electrode, and the right half of FIG. 6 and the left half of FIG.
It has the same configuration consisting of a wide electrode and a narrow electrode. Therefore,
6 and 7 have substantially the same configuration, and ideally have the same capacitance value. Therefore, there is no variation in capacitance due to the difference in the stacking order of the odd number of internal electrodes.
【００１２】図８及び図９は図１〜図６のコンデンサの
製造方法の１例を原理的に示す。磁器材料と有機バイン
ダとから成るスラリを作り、このスラリからドクターブ
レード法等で長手のグリーンシート（未焼成磁器シー
ト）１０を作り、このグリーンシート１０の上にスクリ
ーンを使用して導電性ペーストを塗布することによって
第１及び第２の内部電極２、３に対応する導電層２ａ、
３ａを形成する。図８のＰ1 からＰ3 までの区間の導電
性ペーストの印刷は１枚のスクリーンを使用して同時に
行う。これにより、導電層２ａ、３ａを均一に形成する
ことができる。この印刷が終了したら同一のスクリーン
を使用してＰ3 より後の領域にＰ1 〜Ｐ3と同一パター
ンの導電層２ａ、３ａを繰返して形成する。印刷が終了
したら、Ｐ1 、Ｐ2 、Ｐ3 でグリーンシート１０を切断
する。これにより、第１の内部電極用導電層２ａを有す
る第１のグリーンシート１１と、第２の内部電極用導電
層３ａを有する第２のグリーンシートとが複数枚得られ
る。FIGS. 8 and 9 show in principle one example of a method of manufacturing the capacitor shown in FIGS. A slurry composed of a porcelain material and an organic binder is prepared, and a long green sheet (unfired porcelain sheet) 10 is formed from the slurry by a doctor blade method or the like. The conductive layers 2a corresponding to the first and second internal electrodes 2 and 3 by applying
3a is formed. Printing of the conductive paste in the section from P1 to P3 in FIG. 8 is performed simultaneously using one screen. Thereby, the conductive layers 2a and 3a can be formed uniformly. When this printing is completed, conductive layers 2a and 3a having the same pattern as P1 to P3 are repeatedly formed in the area after P3 using the same screen. When printing is completed, the green sheet 10 is cut at P1, P2, and P3. Thus, a plurality of first green sheets 11 having the first internal electrode conductive layer 2a and a plurality of second green sheets having the second internal electrode conductive layer 3a are obtained.
【００１３】次に、図９に示すように、第１及び第２の
グリーンシート１１、１２を積層すると共にカバー用グ
リーンシート１３を積層し、これを圧着し、破線で示す
位置を切断して成形体（生チップ）を得、これを焼成
し、最後に外部電極５、７を形成する。図９のように積
層すれば図６の構造の積層コンデンサが得られる。図９
では第１のグリーンシート１１が２枚であるのに対し、
第２のグリーンシート１２は１枚である。図８では第１
及び第２のグリーンシート１１、１２を同時に形成して
いるので、第２のグリーンシート１２が１枚余ることに
なる。この第２のグリーンシート１２の余りを防ぐため
に、図７の積層構造のコンデンサも作る。Next, as shown in FIG. 9, the first and second green sheets 11 and 12 are laminated and the cover green sheet 13 is laminated. A molded body (raw chip) is obtained and fired, and finally the external electrodes 5 and 7 are formed. By laminating as shown in FIG. 9, a multilayer capacitor having the structure of FIG. 6 is obtained. FIG.
Then, while the first green sheet 11 is two sheets,
The number of the second green sheets 12 is one. In FIG. 8, the first
And the second green sheets 11 and 12 are formed at the same time, so that one second green sheet 12 is left. In order to prevent the remainder of the second green sheet 12, a capacitor having a laminated structure shown in FIG. 7 is also manufactured.
【００１４】[0014]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 （１） 図１０に示すように第１及び第２の内部電極
２、３と幅広電極２１、３１と幅狭電極２２、３２とを
連結する部分２３、３３を設け、外部電極５、７に対す
る接続の信頼性を向上させることができる。 （２） 図１１に示すように、第１及び第２の電極２、
３の幅広電極２１、３１及び幅狭電極２２、３２に細条
連結部２４、２５、３４、３５をそれぞれ設けることが
できる。この場合、幅広電極２１、３１の先端２６、３
６を連結部３５、２５に交差させる。また、幅狭電極２
２、３２に連結部３５、２５と同一の突出部２７、３７
を設け、これを幅広電極２１の左端と幅広電極３１の右
端とに交差させる。これにより、図１１で左右方向に第
１及び第２の内部電極２、３がずれても対向面積及び容
量の変化が生じない。 （３） 第１及び第２の内部電極２、３を３よりも多い
奇数個積層する場合にも本発明を適用することができ
る。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) As shown in FIG. 10, portions 23 and 33 for connecting the first and second internal electrodes 2 and 3 with the wide electrodes 21 and 31 and the narrow electrodes 22 and 32 are provided. The reliability of the connection can be improved. (2) As shown in FIG. 11, the first and second electrodes 2,
The three wide electrodes 21 and 31 and the narrow electrodes 22 and 32 can be provided with the strip connecting portions 24, 25, 34 and 35, respectively. In this case, the tips 26, 3 of the wide electrodes 21, 31
6 intersects the connecting portions 35 and 25. Also, the narrow electrode 2
2, 32, the same protrusions 27, 37 as the connecting parts 35, 25
Is provided so as to intersect the left end of the wide electrode 21 and the right end of the wide electrode 31. Thus, even if the first and second internal electrodes 2 and 3 are shifted in the left-right direction in FIG. 11, the facing area and the capacitance do not change. (3) The present invention can also be applied to a case where an odd number of the first and second internal electrodes 2 and 3 that are greater than three are stacked.
【図１】実施例の積層コンデンサを示す斜視図である。FIG. 1 is a perspective view showing a multilayer capacitor according to an embodiment.
【図２】図１のコンデンサの中央縦断面図である。FIG. 2 is a central longitudinal sectional view of the capacitor of FIG. 1;
【図３】図２のＡ−Ａ線断面図である。FIG. 3 is a sectional view taken along line AA of FIG. 2;
【図４】図２のＢ−Ｂ線断面図である。FIG. 4 is a sectional view taken along line BB of FIG. 2;
【図５】図２のＣ−Ｃ線断面図である。FIG. 5 is a sectional view taken along line CC of FIG. 2;
【図６】図２のＤ−Ｄ線断面図である。FIG. 6 is a sectional view taken along line DD of FIG. 2;
【図７】図６の内部電極の積層順番を変えた場合を図６
と同様に示す断面図である。FIG. 7 shows a case where the order of lamination of the internal electrodes in FIG. 6 is changed.
It is sectional drawing shown similarly to.
【図８】図１のコンデンサを製造するための導電層のパ
ターンを有するグリーンシートを示す平面図である。FIG. 8 is a plan view showing a green sheet having a conductive layer pattern for manufacturing the capacitor of FIG. 1;
【図９】図１のコンデンサを製造するためのグリーンシ
ートの積層を示す断面図である。FIG. 9 is a cross-sectional view illustrating lamination of green sheets for manufacturing the capacitor of FIG. 1;
【図１０】変形例の内部電極のパターンを図４と同様に
示す断面図である。FIG. 10 is a cross-sectional view showing a pattern of an internal electrode according to a modified example, similarly to FIG.
【図１１】別の変形例の内部電極のパターンを図４と同
様に示す断面図である。FIG. 11 is a cross-sectional view showing a pattern of an internal electrode according to another modification, similarly to FIG.
【図１２】従来の積層コンデンサを図３と同様に示す断
面図である。FIG. 12 is a cross-sectional view showing a conventional multilayer capacitor in the same manner as FIG.
【図１３】図１２のＥ−Ｅ線に対応する部分の断面図で
ある。13 is a cross-sectional view of a portion corresponding to line EE in FIG.
【図１４】図１３の内部電極の積層順番を変えた構造を
図１３と同様に示す断面図である。14 is a cross-sectional view showing a structure in which the stacking order of the internal electrodes in FIG. 13 is changed, similarly to FIG.
２ 第１の内部電極 ３ 第２の内部電極 ２１、３１ 幅広電極 ２２、３２ 幅狭電極 2 First internal electrode 3 Second internal electrode 21, 31 Wide electrode 22, 32 Narrow electrode
Claims (1)
する誘電体と、 前記誘電体の内部の互いに平行な３以上の奇数個の仮想
平面にそれぞれ設けられた奇数個の内部電極と、 前記第１の側面に形成され且つ前記奇数個の内部電極の
内の奇数番目の第１の内部電極に接続された第１の外部
電極と、 前記第２の側面に形成され且つ前記奇数個の内部電極の
内の偶数番目の第２の内部電極に接続された第２の外部
電極とを備えた積層コンデンサにおいて、 前記第１及び第２の内部電極が幅広電極と幅狭電極とか
らそれぞれなり、 前記第１の内部電極の幅広電極が前記第２の内部電極の
幅狭電極に対向し、 前記第１の内部電極の幅狭電極が前記第２の内部電極の
幅広電極に対向していることを特徴とする積層コンデン
サ。1. A dielectric having first and second side surfaces facing each other, an odd number of internal electrodes provided on three or more odd virtual planes parallel to each other inside the dielectric, A first external electrode formed on the first side surface and connected to an odd-numbered first internal electrode of the odd number of internal electrodes; and an odd-numbered external electrode formed on the second side surface. A multilayer capacitor having a second external electrode connected to an even-numbered second internal electrode among the internal electrodes, wherein the first and second internal electrodes are each composed of a wide electrode and a narrow electrode. The wide electrode of the first internal electrode faces the narrow electrode of the second internal electrode, and the narrow electrode of the first internal electrode faces the wide electrode of the second internal electrode. A multilayer capacitor, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4257374A JP2784863B2 (en) | 1992-08-31 | 1992-08-31 | Multilayer capacitors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4257374A JP2784863B2 (en) | 1992-08-31 | 1992-08-31 | Multilayer capacitors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0684690A JPH0684690A (en) | 1994-03-25 |
| JP2784863B2 true JP2784863B2 (en) | 1998-08-06 |
Family
ID=17305506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4257374A Expired - Fee Related JP2784863B2 (en) | 1992-08-31 | 1992-08-31 | Multilayer capacitors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2784863B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4539489B2 (en) * | 2005-08-05 | 2010-09-08 | Ｔｄｋ株式会社 | Manufacturing method of multilayer capacitor |
| JP4548492B2 (en) * | 2008-02-13 | 2010-09-22 | Ｔｄｋ株式会社 | Multilayer capacitor array |
| KR101101530B1 (en) * | 2010-06-24 | 2012-01-04 | 삼성전기주식회사 | Multi layered capacitor |
| KR101388690B1 (en) * | 2012-12-20 | 2014-04-24 | 삼성전기주식회사 | Multi-layered ceramic electronic component |
| JP2018056543A (en) * | 2016-09-29 | 2018-04-05 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Multilayer capacitor and manufacturing method thereof |
-
1992
- 1992-08-31 JP JP4257374A patent/JP2784863B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0684690A (en) | 1994-03-25 |
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