KR101731497B1 - Method for texturing of semiconductor substrate, semiconductor substrate manufactured by the method and solar cell comprising the same - Google Patents
Method for texturing of semiconductor substrate, semiconductor substrate manufactured by the method and solar cell comprising the same Download PDFInfo
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- KR101731497B1 KR101731497B1 KR1020150082816A KR20150082816A KR101731497B1 KR 101731497 B1 KR101731497 B1 KR 101731497B1 KR 1020150082816 A KR1020150082816 A KR 1020150082816A KR 20150082816 A KR20150082816 A KR 20150082816A KR 101731497 B1 KR101731497 B1 KR 101731497B1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
The present invention relates to a method of texturing a semiconductor substrate comprising depositing a low melting point metal on a semiconductor substrate, dry etching the substrate on which the low melting point metal has been deposited, and removing the metal from the dry etched substrate, A semiconductor substrate manufactured according to this method and a solar cell including the semiconductor substrate are provided. According to the present invention, it is possible to provide a method of texturing a semiconductor substrate that is economical and capable of large-scale application of a full wafer scale, and the semiconductor substrate thus manufactured has excellent light absorptivity and can be applied to ultra-thin solar cells Do.
Description
The present invention relates to a method of texturing a semiconductor substrate, a semiconductor substrate manufactured by the method, and a solar cell including the same. More particularly, the present invention relates to a method of dry etching using low melting point metal nanoparticles as a mask A texturing method of a semiconductor substrate, a semiconductor substrate manufactured by the method, and a solar cell including the same.
The solar cell is a device that converts light energy into electrical energy, and has attracted much attention as an environmentally friendly future energy source. A solar cell produces electricity using the properties of a semiconductor. Specifically, the solar cell has a PN junction structure in which a P (positive) semiconductor and a N (negative) semiconductor are bonded. When solar light enters the solar cell, Holes and electrons are generated in the semiconductor due to the energy of the solar light. At this time, the holes move to the P-type semiconductor due to the electric field generated at the PN junction, and the electrons move to the N-type semiconductor And a potential is generated.
Generally, the power production performance of a solar cell is measured by photoelectric conversion efficiency in which light energy is converted into electric energy. However, a part of the sunlight incident on the solar cell is reflected at the boundary between the various layers constituting the solar cell, thereby making it impossible to contribute to the power generation of the solar cell, thereby reducing the efficiency of the solar cell. Therefore, in order to improve the efficiency of the solar cell, the reflectance of the sunlight as described above should be reduced as much as possible.
For this purpose, a texturing process is widely used in solar cells. The texturing process refers to a process of roughening the surface of a semiconductor substrate or various layers constituting a solar cell, that is, forming a pattern of irregularities or pyramid shapes on the surface of a semiconductor substrate or various layers. For example, if a pyramid-shaped pattern is formed on the surface of a semiconductor substrate, when the light reaches the first pyramid wall due to the arrival of light, part of the pyramid is absorbed and part of the light is reflected back to the pyramid wall. So that the light absorption amount is increased. Thus, the light absorption amount is increased due to the pyramidal structure, and as a result, the cell efficiency can be improved. Therefore, when the solar cell substrate is manufactured through the surface treatment method, the surface reflection of the solar cell can be reduced, the carrier collection effect can be improved, and the light confinement effect can be realized by the internal reflection of the solar cell.
For example, Patent Document 1 (Korean Patent Publication No. 0180621) uses a texture etching solution mixed at a ratio of 0.5 to 5.0% by volume of potassium hydroxide solution, 3.0 to 20.0% by volume of isopropyl alcohol and 75.0 to 96.5% by volume of deionized water Thereby texturing the silicon substrate. According to this method, a fine pyramid structure is formed on the surface of the silicon wafer, and the textured silicon surface can increase the efficiency of the solar cell by increasing the internal reflection efficiency.
However, in the case of the pyramidal structure formed by such a method, the size varies from several microns to tens of microns, resulting in a wafer loss of several tens of microns in thickness during etching, Application of ultra thin wafer solar cell is limited.
In order to solve this problem, a method of texturing a silicon wafer surface to nano or submicron size using nano-lithography is being studied.
Examples of the nanolithography process are nanoimprint (see Patent Document 2), laser interference lithography (see Non-Patent Document 1), and photolithography using extreme ultra violet (EUV) (see Patent Document 3). However, most of these processes have a problem that the process cost is high.
On the other hand, Patent Document 4 (US 2009/0236317 A1) discloses a method of synthesizing a metal into nano-sized particles through vacuum deposition and then performing a metal catalyst etching method A method of performing nano patterning is described. This method is a relatively low-cost process as compared with the above-described nanolithography processes, but uses expensive noble metal such as Au, Ag, etc., and the result of metal etching is sensitive to the etching solution environment.
A problem to be solved by the present invention is to provide a method of texturing a surface of a semiconductor substrate into a nanostructure by dry etching using low melting point metal nanoparticles as a mask.
Another object of the present invention is to provide a method of texturing a semiconductor substrate which is low in process cost and can be applied to a large area of a full wafer scale.
Another object of the present invention is to provide a semiconductor substrate which exhibits an excellent light absorptivity due to a reduced reflectance of incident light and is applicable to an ultra-thin solar cell.
Another object of the present invention is to provide a solar cell including the semiconductor substrate.
In order to solve the above problems, the present invention provides a method of manufacturing a semiconductor device, comprising: depositing a low melting point metal on a semiconductor substrate; dry etching the substrate on which the low melting point metal is deposited; and removing the metal from the dry etched substrate The present invention also provides a method of texturing a semiconductor substrate.
The present invention also provides a semiconductor substrate textured according to the above method and a solar cell comprising the same.
At this time, the semiconductor substrate may include a texture structure irregularly arranged on the surface (hereinafter referred to as a "nanostructure"), and the nanostructure preferably has a height of 100 to 1000 nm and a diameter of 100 to 1000 nm .
According to the present invention, the surface of a semiconductor substrate can be easily textured into a nanostructure by dry etching using low melting point metal nanoparticles as a mask.
Also, the texturing method according to the present invention is economical as compared with the conventional method using nanolithography, and can be applied to large-scale application of a full wafer scale.
The semiconductor substrate textured by the above method exhibits excellent light absorptivity due to low reflectance of incident light, low rate of surface area increase during texturing, high charge collection efficiency, and is particularly effective in maximizing light absorption of an ultra-thin wafer-based solar cell.
1 illustrates a texturing process of a semiconductor substrate according to an embodiment of the present invention.
2 is a SEM photograph showing the deposition thickness of tin (Sn) deposited on a silicon substrate and the heat treatment temperature.
3 is a graph showing the average diameter of tin (Sn) nanoparticles according to the thickness of tin (Sn) deposition.
4 is a graph showing the surface coverage of tin (Sn) nanoparticles according to the heat treatment temperature.
5 is a SEM photograph showing a surface structure of a textured silicon substrate according to an embodiment of the present invention.
6 is a SEM photograph showing a side structure of a silicon nano structure according to an etching time in a reactive ion etching (RIE) process.
7 is a graph showing the height of the nanostructure according to the RIE etching time.
8 is a schematic diagram showing a cross-sectional structure of a nanostructure formed on a semiconductor substrate according to the present invention.
9 is a graph showing the average reflectance according to the height of the nanostructure in a silicon wafer textured according to Example 1. FIG.
10 is a graph showing an average reflectance according to the diameter of a nanostructure in a silicon wafer textured according to Example 2. FIG.
11 is a graph showing the rate of surface area increase with annealing temperature for each of the tin (Sn) deposition thicknesses in a silicon wafer textured according to Example 2. Fig.
FIG. 12 is a schematic view showing an increased surface area as a nanostructure is formed on a textured semiconductor substrate according to an embodiment of the present invention. FIG.
A method of texturing a semiconductor substrate according to the present invention includes the steps of depositing a low melting point metal on a semiconductor substrate, dry etching the substrate on which the low melting point metal has been deposited, and removing the metal from the dry etched substrate .
The method of texturing a semiconductor substrate may further include depositing a buffer layer on the semiconductor substrate before depositing a low melting point metal on the semiconductor substrate, And a heat treatment step. In the case of the buffer layer deposition step and the heat treatment step, only one selected step may be added, or all of them may be included. For example, FIG. 1 shows a case where both the step of depositing the buffer layer and the step of heat-treating the substrate are included.
Hereinafter, a method of texturing a semiconductor substrate according to the present invention will be described in detail with reference to FIG.
(One) Buffer layer Deposition step
This step is a step of depositing a buffer layer on a semiconductor substrate.
When the buffer layer is deposited on the semiconductor substrate before the low melting point metal is deposited, the buffer layer controls the surface energy of the substrate to help control the morphology of the low melting point metal deposited on the substrate, It serves to prevent direct contact of melting point metal.
As the buffer layer, a metal oxide thin film which can be easily etched in the acid may be used. Preferably, the metal oxide thin film may include any one or two or more selected from the group consisting of SiO 2 and SiN x . This buffer layer facilitates peeling of the metal remaining on the semiconductor substrate while being easily etched in an acidic solution such as HF or the like in the "(5) metal removal step" to be described later.
The thickness of the buffer layer may vary depending on the etching selectivity of the low melting point metal and the buffer layer deposited on the semiconductor substrate and is preferably 10 nm to 500 nm. When the thickness of the buffer layer is less than 10 nm, it is insufficient to assist the low melting point metal morphology control and the removal of the low melting point metal nanoparticles. On the other hand, when the thickness of the buffer layer is more than 500 nm, the RIE process time for etching the semiconductor substrate becomes long, and etching of the metal particles serving as a mask is accompanied by difficulty in manufacturing a desired nano disk type structure Which is undesirable.
The semiconductor substrate may include any one or two or more selected from the group consisting of Si, Ge, GaAs, and InGaAs, and may preferably include Si. More preferably, the Si may be crystalline Si, and the crystalline Si may be a monocrystalline silicon, a polycrystalline silicon, or a combination thereof.
In addition, the semiconductor substrate may be a substrate subjected to a cleaning step, and the cleaning step is performed for the purpose of removing contaminants possibly adsorbed on the semiconductor substrate. In this cleaning step, a conventional cleaning method such as a spraying method of spraying the cleaning agent onto the entire surface of the semiconductor substrate from the showerhead to which the cleaning agent is supplied or a dipping method in which the semiconductor substrate is immersed in the cleaning solution for a predetermined period of time may be used. It is not. The cleaning agent may include one or more selected from the group consisting of hydrochloric acid (HCl), ammonium hydroxide (NH 4 OH), sulfuric acid (H 2 SO 4 ), and hydrogen peroxide (H 2 O 2 ).
(2) Low melting point Metal deposition step
This step is a step of depositing a low melting point metal on the semiconductor substrate.
The melting point of the low melting point metal is preferably 100 to 350 ° C. If the melting point is less than 100 ° C, it is difficult to precisely control the deposition rate during the deposition process. On the other hand, when the melting point exceeds 350 ° C, it is difficult to synthesize submicron sized nanoparticles. There may arise a problem that a high-temperature process for a long time is required.
As the low-melting point metal, it is preferable to use a metal element having low interfacial reactivity with silicon. For example, any one selected from the group consisting of Sn, In, Pb, In-Sn alloy, Sn-Pb alloy and In- Two or more can be used.
As a method of depositing the low melting point metal, a conventional vacuum deposition may be used. For example, a thermal evaporation method, an electron beam evaporation method, a sputtering method, or the like may be used. no. In the present invention, by using such a vacuum deposition method, a low-melting metal can be synthesized at a sub- micron size without a post-annealing process at a substrate temperature of room temperature.
According to the present invention, there is provided a semiconductor substrate in which nanoparticles of a low-melting-point metal deposited on a semiconductor substrate serve as a mask, and then the surface is textured into a nanostructure by etching. The size and surface coverage of such low melting point metal nanoparticles can be easily controlled by adjusting the deposition thickness of the low melting point metal and the heat treatment temperature in the "(3) heat treatment step" to be described later.
Specifically, FIG. 2 shows an SEM image according to the deposition thickness and heat treatment temperature of the low melting point metal deposited on the semiconductor substrate. At this time, silicon was used for the semiconductor substrate and tin (Sn) was used for the low melting point metal. Referring to FIG. 2, it can be seen that the cross-sectional size of island-shaped tin particles increases as the deposition thickness increases. This can be more clearly seen in FIG. 3, which shows the variation of the average diameter of tin (Sn) particles with the thickness of the tin (Sn) deposition. 3, when the tin deposition thickness is adjusted to 50 nm to 200 nm, it can be seen that the average diameter of the low melting point metal nanoparticles can be adjusted to 150 nm to 1500 nm.
Preferably, the deposition thickness of the low-melting-point metal deposited on the semiconductor substrate is 50 to 200 nm, and when the effective thickness is less than 50 nm, the average diameter of the low-melting-point metal nanoparticles synthesized on the substrate may be excessively low If it exceeds 200 nm, the average diameter of the low melting point metal nanoparticles may be excessive. If the average diameter of the low-melting-point metal nanoparticles is excessively small or excessive as described above, the diameter of the texture structure formed on the semiconductor substrate may be excessively small or excessive, and the effect of reducing the reflectance may be deteriorated. Here, the deposition thickness represents an effective thickness, and the effective thickness refers to the thickness when the deposited metal forms a continuous film on the substrate. The effective thickness is measured using a quartz crystal microbalance during vacuum deposition Value.
(3) Heat treatment step
This step is a step of heat-treating the substrate on which the low melting point metal is deposited. The heat treatment step may be introduced to control the surface coverage of the low-melting-point metal nanoparticles formed on the substrate, and may be omitted when large surface coverage is required depending on the application.
As described above, FIG. 2 shows an SEM image according to the deposition thickness of tin (Sn) deposited on a silicon substrate and the heat treatment temperature. Referring to FIG. 2, as the heat treatment temperature is lowered, Sn) particle surface courage is increased. This can be more clearly seen in FIG. 4, which shows the surface coverage change of tin (Sn) particles according to the heat treatment temperature. Specifically, FIG. 4 shows that the surface coverage can be adjusted from 30% to 90% when the heat treatment temperature is adjusted to 500 ° C. As described above, according to the present invention, the surface coverage of the low melting point metal nanoparticles can be easily controlled by adjusting the heat treatment temperature. Here, the surface coverage refers to the ratio of the surface covered with the low melting point metal nanoparticles to the entire surface of the semiconductor substrate.
At this stage, the heat treatment temperature is preferably 300 ° C. to 500 ° C. If the heat treatment temperature is lower than 300 ° C., the surface coverage of the low melting point metal nanoparticles may be excessive. On the other hand, when the temperature exceeds 500 ° C., There is a risk of it becoming dangerous. If the surface coverage of the low-melting-point metal nanoparticles is excessively small or excessive as described above, the total sectional area ratio of the nanostructures on the semiconductor substrate may be excessively small or excessive, and the effect of reducing the reflectance may be deteriorated.
When the low melting point metal is used in the texturing process of the semiconductor substrate as in the present invention, the size and surface density of the metal nanoparticles can be easily controlled over a wide range compared with the case of using noble metals such as Ag and Au , And the process cost can also be reduced.
(4) Etching step
This step is a step of forming a texture structure on the semiconductor substrate by using the low melting point metal nanoparticles remaining on the substrate as a mask. Referring to FIG. 5, an SEM image of the semiconductor substrate through the etching step is shown.
As the etching method, dry etching is used, and preferably, the dry etching may be reactive ion etching (RIE). When the dry etching is used as described above, the problems due to the conventional wet etching, in which the etching result is sensitive to the etching solution environment and the large-scale process is difficult, can be solved.
The portion of the semiconductor substrate covered with the low-melting-point metal nano-particles by the etching process remains as a convex portion, and the remaining portion is etched as a concave portion to form a semiconductor substrate having a surface texture. The height of the texture structure formed on the substrate (hereinafter referred to as " nanostructure ") can be controlled by adjusting the time of the etching process. Specifically, in the case where tin (Sn) nanoparticles are deposited on a silicon wafer, a lateral SEM image of the silicon nanostructure according to the RIE etching time is shown in FIG. 6, and the height variation of the silicon nanostructure with respect to the RIE etching time The graph showing is shown in Fig.
6 and 7, it can be seen that the height of the nanostructure can be controlled to 100 to 500 nm by adjusting the etching time to 3 minutes to 15 minutes. When the height of the nanostructure falls within the above range, It is more preferable to obtain an excellent reflectance reduction effect in the band.
At this time, the etching gas used in the dry etching is CF 4, CHF 3, SF 6, Ar, Cl 2 and O may be a second one or more than one gas mixture selected from the group consisting of, preferably CF 4 / O 2 mixed gas, SF 6 / O 2 mixed gas and Cl 2 / O 2 mixed gas.
The shape of the nanostructure can be controlled by adjusting the degree of anisotropy through control of plasma process parameters during the dry etching process. That is, as shown in the etching step (4) of FIG. 1, the shape of the nanostructure may be anisotropic etching (left), isotropic etching (right), or a mixture thereof, depending on processing conditions at the etching step .
(5) Metal removal step
This step is a step of removing the low-melting-point metal from the semiconductor substrate through the etching step, in which the buffer layer can be removed together.
As a method for removing the low melting point metal, a conventional metal etch method can be used without limitation, and a method of using an ultrasonic washing machine in an acid solution can be used. The acid solution used herein may be any one or two or more selected from the group consisting of hydrochloric acid, nitric acid, sulfuric acid, and hydrofluoric acid.
By performing steps (1) to (5) as described above, a nanostructure is formed on the semiconductor substrate, and the nanostructure strongly scatters the incident light forward, thereby greatly increasing the light absorption of the semiconductor substrate.
In addition, in the present invention, in order to reduce the reflectance, the method may further include the step of depositing any one selected from SiO 2 , SiN x, and a mixed layer thereof on the semiconductor substrate from which the low melting point metal has been removed.
When the semiconductor substrate is subjected to the nanotexturing according to the above manufacturing process, it is possible to reduce the process cost compared to the nanolithography process such as nanoimprint, laser interference lithography, and EUV-based photolithography, which have conventionally required expensive equipment.
The present invention also provides a semiconductor substrate manufactured according to the above-described method.
The semiconductor substrate includes a texture structure (hereinafter, referred to as a 'nanostructure') randomly arranged on the surface of the semiconductor substrate, and the nanostructure has a height of 100 to 1000 nm and a diameter of 100 to 1000 nm do.
FIG. 8 schematically shows a cross-sectional structure of an example of a texture structure formed on a semiconductor substrate according to the present invention. When incident light is incident on a semiconductor substrate, for example, a high refractive index wafer such as silicon, incident light is scattered by a submicron scale nano structure located on the surface due to Mie scattering effect, and most of the scattered light is guided toward the substrate do. At this time, the scattering cross-sectional area of the nanostructure is affected by the diameter, the height, and the type of the substrate.
As described above, the height of the nanostructure is 100 to 1000 nm. When the height is less than 100 nm, the effect of reducing the reflectance of the semiconductor substrate including the nanostructure can not be sufficiently exhibited. On the other hand, when the height of the nanostructure is more than 1000 nm, the loss of the semiconductor substrate is excessive relative to the texturing efficiency. Also, due to the increase in the surface area of the semiconductor substrate, electrical loss increases when applied to a photoelectric device such as a solar cell or a photodiode do. When the height of the nanostructure is 100 to 200 nm, excellent reflectance reduction effect can be obtained in a wide wavelength band.
When the diameter is less than 100 nm, the scattering cross-sectional area does not show a high value over a wide band. On the other hand, when the diameter is more than 1000 nm, the nanostructure includes a nanostructure- There is a problem that the effect of reducing the reflectance of the substrate is deteriorated. When the diameter of the nanostructure is 300 to 500 nm, a high scattering cross-sectional area can be obtained in a wide wavelength band.
In particular, when the height of the nanostructure is 100 to 200 nm and the diameter is 1 micron or less, it is effective to maximize the light absorption of the ultra-thin silicon solar cell.
Further, according to the present invention, there is provided a solar cell including the semiconductor substrate.
The semiconductor substrate having the texturing method and the texturing structure of the semiconductor substrate as described above can be used not only as the solar cell but also as a photovoltaic device, an optical and electrochemical detector / sensor, a biodetector / biosensor, a catalyst, And other devices that reduce the reflection of incident light to improve the efficiency of the device.
Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited to these embodiments.
Example One
The silicon wafers were washed thoroughly for 30 minutes each using the standard cleaning process RCA-1 (H 2 O 2 -NH 4 OH-H 2 O) and RCA-2 (H 2 O 2 -HCl-H 2 O) .
SiO 2 was vacuum deposited to a thickness of 50 nm on the silicon wafer from which the impurities were removed using an electron beam evaporation deposition equipment (Korea KV-2004)
Tin (Sn) was vacuum deposited on the silicon wafer on which the SiO 2 was deposited using a thermal evaporation apparatus (Korea KV-2004) to a thickness of 100 nm.
The silicon wafer on which the tin is vacuum-deposited is heat-treated at 500 DEG C for 10 minutes.
The silicon wafer subjected to the heat treatment is referred to as dry type using an RIE equipment (Advanced Vacuum & STS, Advanced RIE). A silicon wafer having a height of 75 nm, a silicon wafer having a thickness of 150 nm, a silicon wafer having a thickness of 230 nm, a silicon wafer having a thickness of 320 nm, and a silicon wafer having a thickness of 500 nm were prepared by controlling the etching time to 3 minutes, 5 minutes, 7 minutes, 10 minutes, .
Then, the tin particles are removed from each silicon wafer subjected to the etching process using an ultrasonic cleaner in a 1M HCl solution.
Finally, a SiNx layer was deposited to a thickness of 70 nm on each of the silicon wafers on which the nanostructures were formed using a CVD (Chemical Vapor Deposition) process, and the texturing process was completed.
Example 2
The texturing process was carried out in the same manner as in Example 1, except that the tin (Sn) deposition thickness and the RIE etching time were controlled. Specifically, silicon wafers having an average diameter of 150 nm, silicon wafers having a diameter of 340 nm, silicon wafers having a diameter of 600 nm, and silicon wafers having a diameter of 900 nm were prepared by controlling the deposition thickness of the tin (Sn) to 50 nm, 100 nm, 150 nm and 200 nm , Where the RIE etch time was fixed at 5 minutes and the height of the nanostructures on each wafer was 150 nm.
<Evaluation method>
1. Reflectance (%)
The reflectivities of the textured silicon wafers according to Examples 1 and 2 were measured and their average reflectivities were compared in Figures 9 and 10. In this case, the reflectance is a value obtained by measuring the total reflectance, which is the sum of mirror reflection and scattering reflection, using an integrating sphere at a wavelength of 300 to 1100 nm, and the average reflectance is a value calculated according to the following equation.
In this formula,
? min : 300 nm,? max : 1100 nm
I solar (λ): Standard photovoltaic spectrum Photoluminescence intensity according to wavelength under AM 1.5G
R (?): Reflectance according to wavelength
FIG. 9 is a graph showing average reflectance according to height of a textured nanostructure according to Example 1, and FIG. 10 is a graph showing average reflectance according to an average diameter of textured nanostructures according to Example 2. FIG. .
Referring to FIGS. 9 and 10, it can be seen that the silicon wafers textured into nanostructures according to Examples 1 and 2 of the present invention all have a low reflectance with an average reflectance of less than 10%. In particular, when the height of the nanostructure is 150 nm and the average diameter is 340 nm, the lowest average reflectance of 3.6% can be obtained.
2. Surface area increase rate (%)
The rate of increase of the surface area of the textured silicon wafers while controlling the deposition thicknesses (50 nm, 100 nm, 150 nm and 200 nm) of tin (Sn) according to Example 2 was calculated according to the following equation and the heat treatment temperature FIG. 11 is a graph showing the surface area increase rate according to the present invention.
Surface area increase rate (%) = (wafer surface area after texturing / flat wafer surface area)
× 100
Referring to FIG. 12, an increased surface area is shown schematically as a nanostructure is formed on a semiconductor substrate after texturing. When the surface area is increased, the e-h (electron-hole) recombination loss increases in proportion to the surface area increase, and the photovoltaic efficiency is decreased because the absorption ratio of the incident light increases in the emitter layer having a low charge collection efficiency. Therefore, the lower the rate of surface area increase, the better the charge collection efficiency.
Referring to FIG. 11, it can be seen that the surface area increase rate is changed according to the deposition thickness of tin (Sn), which is a low melting point metal, and when the heat treatment is performed at 500 ° C, the surface area increase rate is less than 300% . Particularly, in the case of a silicon wafer which was textured by depositing tin (Sn) having a minimum reflectance to a thickness of 100 nm, the surface area increase rate was 187%, which was close to the surface area increase rate of the pyramid structure.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the scope of the present invention is not limited to the disclosed exemplary embodiments but is to be construed as being limited only by the appended claims. Should be construed as being included in the scope of the present invention.
Claims (18)
Heat treating the substrate having the low melting point metal deposited thereon;
Dry etching the substrate on which the low melting point metal is deposited; And
Removing the metal from the dry etched substrate to form a nanostructure,
Further comprising the step of depositing a layer selected from the group consisting of silicon oxide, silicon nitride and a mixed layer thereof on the substrate having been subjected to the step of removing the metal,
The height of the nanostructure is 100 to 200 nm, the diameter is 300 to 500 nm,
Wherein the semiconductor substrate is crystalline silicon,
Wherein the low melting point metal includes one or more selected from the group consisting of Sn, In, Pb, In-Sn alloy, Sn-Pb alloy and In-Pb alloy.
And the melting point of the low-melting-point metal is 100 to 350 ° C.
Wherein the deposition of the low melting point metal is 50 nm to 200 nm in the step of depositing the low melting point metal.
Wherein the dry etching is reactive ion etching (RIE).
Wherein the etching gas used for the dry etching is any one or two or more mixed gases selected from the group consisting of CF 4 , CHF 3 , SF 6 , Ar, Cl 2 and O 2 .
Further comprising depositing a buffer layer on the semiconductor substrate prior to depositing the low melting point metal,
Wherein the buffer layer is a metal oxide thin film.
Wherein the metal oxide thin film comprises at least one selected from the group consisting of silicon oxide and silicon nitride.
Further comprising depositing a buffer layer on the semiconductor substrate prior to depositing the low melting point metal,
Wherein the thickness of the buffer layer is 10 to 500 nm.
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| NO346994B1 (en) * | 2021-07-07 | 2023-03-27 | Univ Of South Eastern Norway | Combined use of tin (Sn) thin film as the Solid-Liquid-InterDiffusion top layer metal layer for silicon chip and wafer stack bonding and as the masking film during silicon micromachining |
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