KR101682420B1 - Self-aligned heterojunction tunnel field-effect transistor using selective germanium condensation and sidewall processes - Google Patents
Self-aligned heterojunction tunnel field-effect transistor using selective germanium condensation and sidewall processes Download PDFInfo
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- KR101682420B1 KR101682420B1 KR1020150088792A KR20150088792A KR101682420B1 KR 101682420 B1 KR101682420 B1 KR 101682420B1 KR 1020150088792 A KR1020150088792 A KR 1020150088792A KR 20150088792 A KR20150088792 A KR 20150088792A KR 101682420 B1 KR101682420 B1 KR 101682420B1
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- sidewall
- silicon oxide
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 229910052732 germanium Inorganic materials 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000009833 condensation Methods 0.000 title claims abstract description 10
- 230000005494 condensation Effects 0.000 title claims abstract description 10
- 230000005669 field effect Effects 0.000 title abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- 230000005641 tunneling Effects 0.000 claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 40
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 34
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 31
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 28
- 239000012535 impurity Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7311—Tunnel transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
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- Condensed Matter Physics & Semiconductors (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
The present invention relates to a tunneling field effect transistor, and more particularly, to a method of manufacturing a self-aligned hetero-junction tunneling field effect transistor using selective germanium condensation and sidewall processes.
In general, the power consumption of a semiconductor device is closely related to the driving voltage. For low-power operation, reduction of the driving voltage is essential. However, in the case of conventional MOSFETs, there is a physical limitation that the subthreshold swing (SS) can not be lowered below 60 mV / dec at room temperature. Therefore, if the driving voltage is lowered, the performance degradation due to the increase of the leakage current or the decrease of the driving current is inevitable. To solve these problems, companies, research institutes and universities in advanced countries are concentrating their research efforts on the development of new high energy efficiency semiconductor devices as next generation devices.
One of the devices that are being developed as a next generation device is a tunneling field effect transistor (hereinafter referred to as " tunneling field effect transistor ") having a structure in which an
In the case of the conventional N-channel TFET, the
2, when a positive (+) driving voltage is applied to the
Due to the structure and operational characteristics of the TFET described above, the TFET can control the flow of electrons or holes (holes) by a tunneling method, which is different from the thermoelectron emission of the conventional MOSFET, so that the rapid ON / OFF state can be changed. Therefore, the tunneling field effect transistor is expected to show high performance even under very low driving voltage of 0.5V or less.
However, TFETs have not yet demonstrated comparable performance to MOSFETs. Important factors for a variety of reasons are low drive current and high leakage current due to ambipolar operation. Tunneling efficiency is very sensitive to the energy gap of semiconductor materials. Typical homo-junction tunneling field effect transistors include silicon (Si) junction tunneling field effect transistors and germanium (Ge) junction tunneling field effect transistors. The former is due to the homogeneous junction of silicon (Si) in the source (2) / channel region (3) / drain (4) in FIG. 1 and since the band gap energy of silicon is as large as 1.12 eV, tunneling efficiency The latter is due to the homojunction of germanium (Ge) in both the source (2) / channel region (3) / drain (4) in FIG. 1 and conversely the band gap energy of germanium is as small as 0.66 eV High drive current is guaranteed, but high leakage current due to ambipolar operation is a problem.
In order to solve the above problems, the inventors of the present invention have proposed a method of forming a high-permittivity film in a tunneling junction region between a source (2) and a channel region (3) instead of the gate insulating film (5) 1, the
However, when a germanium (Ge) -silicon (Si) heterojunction is formed between the
3, a hetero-junction tunneling field effect transistor having a germanium (62) -silicon (22) heterojunction structure beneath a
US Patent No. 8,828,812 discloses that a germanium 62-
The present invention provides a method of manufacturing a hetero-junction tunneling field effect transistor self-aligned so that hetero-junction is located under a sidewall gate or sidewall insulation film using selective germanium condensation and sidewall processes. .
According to another aspect of the present invention, there is provided a method of fabricating a hetero-junction tunneling field effect transistor, comprising: forming a hard mask having a silicon oxide film and an etching selectivity on one side of a silicon substrate; A second step of forming a silicon germanium layer on the silicon substrate exposed to the periphery of the hard mask; A third step of forming the silicon germanium layer into a silicon oxide layer and simultaneously forming a silicon substrate region covered with the silicon germanium layer with a germanium layer by a germanium condensation technique through a thermal oxidation reaction; A fourth step of removing the silicon oxide film; Depositing and etching a gate insulating layer and a gate material on the substrate to form a sidewall gate on one side of the hard mask; A sixth step of implanting the first conductivity type impurity ions using the side wall gate and the hard mask as an ion implantation mask; Depositing a silicon oxide film on the substrate and planarizing the silicon oxide film; And an eighth step of removing the hard mask and implanting ions of second conductivity type impurities opposite to the first conductivity type.
In the eighth step, after the hard mask is removed, an insulating material is deposited and etched to form a sidewall insulating film on one side of the sidewall gate, and the second conductive impurity ions can be implanted.
Further comprising the step of forming a side wall on one side of the hard mask by depositing and etching a material ensuring an etch selectivity with the hard mask on the substrate between the first step and the second step, The silicon germanium layer may be formed on the silicon substrate exposed to the periphery of the sidewall, and the fourth step may be performed by removing the sidewall.
The formation of the silicon germanium layer in the second step may be selectively grown on the exposed silicon substrate, or may be formed by depositing the silicon germanium layer on the entire surface of the substrate to a predetermined thickness. In the latter case, the silicon germanium layer remaining on the sidewall gate and the hard mask is removed before removing the silicon oxide layer and the sidewall in the fourth step.
The material securing the etch selectivity with the hard mask may be a silicon oxide film, and the side walls may be formed as sidewalls of a silicon oxide film.
In the present invention, a hard mask is formed first on a silicon substrate, a silicon germanium layer is formed on a silicon substrate exposed around the hard mask, and the germanium is condensed through a thermal oxidation reaction and a process of forming a sidewall gate on the sidewall of the hard mask , A hetero-junction of germanium and silicon is formed at a position distant from the source under the gate of the sidewall, thereby producing a self-aligned hetero-junction tunneling field effect transistor.
Further, when a side wall is formed on one side of the hard mask such as a silicon oxide film to form a silicon germanium layer, or a side wall of an insulating film is formed on one side of the side wall gate and the impurity ion implantation process is performed, Or the position of the heterojunction formed under the side wall of the insulating film can be finely adjusted or the channel direction length of germanium and silicon doped less heavily than the source or drain can be easily controlled.
1 is a cross-sectional view showing the basic structure of a conventional tunneling field effect transistor (N-channel TFET).
FIG. 2 illustrates a tunneling current (ON CURRENT: I ON) tunneling junction between a P + region and a channel region adjacent to a P + region when a reverse bias is applied to the source / drain and a positive ) Is generated.
3 is a cross-sectional view conceptually illustrating the structure of a heterojunction tunneling field effect transistor proposed in US Patent No. 8,828,812.
FIGS. 4 to 6 are process cross-sectional views illustrating some process steps in a method of manufacturing a hetero-junction tunneling field effect transistor according to an embodiment of the present invention.
7 to 15 are cross-sectional views illustrating a method of manufacturing a hetero-junction tunneling field-effect transistor according to another embodiment of the present invention.
FIGS. 16 and 17 are cross-sectional views illustrating a method for fabricating a hetero-junction tunneling field-effect transistor according to another embodiment of the present invention, which can be performed in place of FIGS. 8 and 9, respectively.
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
FIGS. 4 to 6 are cross-sectional views illustrating a process step of a hetero-junction tunneling field-effect transistor according to an embodiment of the present invention. Referring to FIGS. 4 to 6, 16 and 17, which illustrate that some steps can be performed differently from those of FIG.
First, as shown in FIG. 4, a
Here, the
Next, as shown in FIG. 5, a silicon germanium layer (SiGe) 40 is formed on the
As shown in FIG. 5, the silicon germanium layer (SiGe) 40 may be formed around the
When the
The formation of the silicon germanium layer (SiGe) 40 can also be effected selectively on the silicon substrate exposed around the
Next, as shown in FIG. 5, FIG. 8, or FIG. 16, in the state where the
Next, as shown in FIG. 10, the
11, a
11, when the
Next, as shown in FIG. 12, a
Subsequently, a
Then, as shown in FIG. 13, the
13, after the
As described above, the
10: buried oxide film 20: silicon substrate
22: intrinsic or low concentration silicon layer 24: drain
30: hard mask 32: side wall
34: Material mask for hard mask etching 36: Insulating film side wall
40, 42, 44: silicon germanium layer 50: silicon oxide film
60: germanium layer 62: intrinsic or low concentration germanium layer
64: source 70: gate insulating film
80: Side wall gate
Claims (6)
A second step of forming a silicon germanium layer on the silicon substrate exposed to the periphery of the hard mask;
A third step of forming the silicon germanium layer into a silicon oxide layer and simultaneously forming a silicon substrate region covered with the silicon germanium layer with a germanium layer by a germanium condensation technique through a thermal oxidation reaction;
A fourth step of removing the silicon oxide film;
Depositing and etching a gate insulating layer and a gate material on the substrate to form a sidewall gate on one side of the hard mask;
A sixth step of implanting the first conductivity type impurity ions using the side wall gate and the hard mask as an ion implantation mask;
Depositing a silicon oxide film on the substrate and planarizing the silicon oxide film; And
And removing the hard mask and implanting ions of a second conductivity type impurity opposite to the first conductivity type. [5] The method of claim 1,
Wherein the step of forming the heterojunction tunneling electric field comprises the steps of: removing the hard mask, depositing and etching an insulating material to further form sidewalls of the insulating film on one side of the sidewall gate, and implanting the second conductive impurity ions A method of manufacturing an effect transistor.
Further comprising the step of forming a side wall on one side of the hard mask by depositing and etching a material ensuring an etch selectivity with the hard mask on the substrate between the first step and the second step,
The second step includes forming the silicon germanium layer on the silicon substrate exposed around the sidewall,
Wherein the fourth step further comprises removing the sidewalls. ≪ RTI ID = 0.0 > 11. < / RTI >
Wherein the formation of the silicon germanium layer in the second step is selectively grown on the exposed silicon substrate. ≪ RTI ID = 0.0 > 11. < / RTI >
Wherein the silicon germanium layer of the second step is deposited on the entire surface of the substrate to a predetermined thickness,
Wherein the silicon germanium layer remaining on the sidewall gate and the hard mask is removed prior to removing the silicon oxide layer and the sidewall in the fourth step.
The material that secures the etch selectivity with the hard mask is a silicon oxide film,
Wherein the sidewalls are silicon oxide sidewalls. ≪ Desc / Clms Page number 20 >
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10236364B1 (en) | 2018-06-22 | 2019-03-19 | International Busines Machines Corporation | Tunnel transistor |
US10249755B1 (en) | 2018-06-22 | 2019-04-02 | International Business Machines Corporation | Transistor with asymmetric source/drain overlap |
US10347731B2 (en) | 2017-11-09 | 2019-07-09 | International Business Machines Corporation | Transistor with asymmetric spacers |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8368127B2 (en) * | 2009-10-08 | 2013-02-05 | Globalfoundries Singapore Pte., Ltd. | Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current |
US20140199825A1 (en) * | 2011-09-20 | 2014-07-17 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof |
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2015
- 2015-06-23 KR KR1020150088792A patent/KR101682420B1/en active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8368127B2 (en) * | 2009-10-08 | 2013-02-05 | Globalfoundries Singapore Pte., Ltd. | Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current |
US20140199825A1 (en) * | 2011-09-20 | 2014-07-17 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10347731B2 (en) | 2017-11-09 | 2019-07-09 | International Business Machines Corporation | Transistor with asymmetric spacers |
US10516028B2 (en) | 2017-11-09 | 2019-12-24 | International Business Machines Corporation | Transistor with asymmetric spacers |
US10236364B1 (en) | 2018-06-22 | 2019-03-19 | International Busines Machines Corporation | Tunnel transistor |
US10249755B1 (en) | 2018-06-22 | 2019-04-02 | International Business Machines Corporation | Transistor with asymmetric source/drain overlap |
US10483382B1 (en) | 2018-06-22 | 2019-11-19 | International Business Machines Corporation | Tunnel transistor |
US10510885B1 (en) | 2018-06-22 | 2019-12-17 | International Business Machines Corporation | Transistor with asymmetric source/drain overlap |
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