CN104465377B - Pmos transistor and forming method thereof - Google Patents
Pmos transistor and forming method thereof Download PDFInfo
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- CN104465377B CN104465377B CN201310425758.5A CN201310425758A CN104465377B CN 104465377 B CN104465377 B CN 104465377B CN 201310425758 A CN201310425758 A CN 201310425758A CN 104465377 B CN104465377 B CN 104465377B
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- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 16
- 238000002347 injection Methods 0.000 claims description 14
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A kind of PMOS transistor and forming method thereof, the forming method of the PMOS transistor includes：Semiconductor substrate is provided；The first semiconductor layer is formed in semiconductor substrate surface；Patterned masking layer, the first semiconductor layer of covering part are formed in the first semiconductor layer surface；Using Patterned masking layer as mask, the first semiconductor layer is etched, forms the first groove, the first groove exposes the surface of part semiconductor substrate；The second semiconductor layer is formed in the first groove, the energy gap of the second semiconductor layer material is more than the energy gap of the first semiconductor layer material；Dielectric layer is formed in the second semiconductor layer surface, the surface of the dielectric layer is flushed with the surface of Patterned masking layer；Patterned masking layer is removed, the second groove is formed；Gate structure is formed in the second groove；The dielectric layer for removing gate structure both sides, source electrode and drain electrode is formed in the second semiconductor layer.The forming method of above-mentioned PMOS transistor can improve the performance of PMOS transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of PMOS transistor and forming method thereof.Background technology
MOS transistor is most basic electronic component in integrated circuit, the performance of the performance of MOS transistor to entire chip
There is tremendous influence.
Referring to FIG. 1, the structural schematic diagram of the MOS transistor for the prior art.
The MOS transistor includes：Semiconductor substrate 10；Gate structure 20 positioned at 10 surface of semiconductor substrate, it is described
Gate structure 20 includes the grid positioned at the gate dielectric layer 21 on 10 surface of semiconductor substrate and positioned at 21 surface of the gate dielectric layer
22；Positioned at the side wall 30 of 20 both sides sidewall surfaces of gate structure；In the semiconductor substrate 10 of 20 both sides of the gate structure
Source electrode and drain electrode 40.It is different according to MOS transistor carriers types, the metal-oxide-semiconductor can be NMOS transistor or
The carrier of PMOS transistor, the NMOS transistor is electronics, and the carrier of PMOS transistor is hole.
The material of the semiconductor substrate 10 used in the prior art is generally silicon, i.e., the gate structure of the described MOS transistor
The channel region material of 20 lower sections is silicon.
And since in NMOS transistor, carrier is electronics, mobility is larger in silicon, and NMOS transistor has higher
Saturation current；And in PMOS transistor, carrier is hole, and mobility of the hole in silicon is relatively low, leads to PMOS transistor
Saturation current is relatively low, and the performance of the PMOS transistor needs further to be improved.
Invention content
Problems solved by the invention is to provide a kind of forming method of transistor, improves the performance of PMOS transistor.
To solve the above problems, the present invention provides a kind of forming method of PMOS transistor, including：Semiconductor lining is provided
Bottom；The first semiconductor layer is formed in the semiconductor substrate surface；Pattern mask is formed in first semiconductor layer surface
Layer, first semiconductor layer of Patterned masking layer covering part；Using the Patterned masking layer as mask, etching described first
Semiconductor layer, forms the first groove, and first groove exposes the surface of part semiconductor substrate；In first groove
The second semiconductor layer is formed, the energy gap of the material of second semiconductor layer is more than the forbidden band of the material of the first semiconductor layer
Width；Dielectric layer is formed in second semiconductor layer surface, the surface of the dielectric layer and the surface of Patterned masking layer are neat
It is flat；The Patterned masking layer is removed, the second groove is formed；Gate structure is formed in second groove；Remove the grid
The dielectric layer of pole structure both sides forms source electrode and drain electrode in second semiconductor layer of gate structure both sides.
Optionally, the material of first semiconductor layer is SiGe.
Optionally, the thickness of first semiconductor layer is 2nm~200nm.
Optionally, the Patterned masking layer includes positioned at the silicon oxide layer of first semiconductor layer surface and positioned at institute
State the silicon nitride layer on silicon oxide layer surface.
Optionally, the material of second semiconductor layer is silicon.
Optionally, the technique that the second semiconductor layer is formed in first groove is selective deposition technique.
Optionally, the surface of second semiconductor layer is flushed with the surface of the first semiconductor layer.
Optionally, the method for forming the dielectric layer includes：The filled media material in first groove, the medium
The surface of full first groove of material filling and cover graphics mask layer；Using the surface of the Patterned masking layer as stop-layer,
The dielectric material is planarized using chemical machinery masking process, forms the dielectric layer.
Optionally, the material of the dielectric layer is silica.
Optionally, it after the dielectric layer for removing the gate structure both sides, is formed before the source electrode and drain electrode, described
It carries out that ion implanting and pocket ion implanting is lightly doped in second semiconductor layer of gate structure both sides, is respectively formed lightly doped district
And pocket region, the pocket region surround the lightly doped district.
Optionally, the ionic type that ion implanting is lightly doped and the ionic type of pocket ion implanting differ.
Optionally, the method for forming the source electrode and drain electrode includes：In the gate structure both sides, sidewall surfaces form side
Wall, using the gate structure and side wall as mask, in the second semiconductor layer of the gate structure both sides carry out heavy doping from
Son injection.
Optionally, the ionic type of the heavy doping ion injection is identical as the ionic type that ion implanting is lightly doped.
Optionally, part source electrode and drain electrode is located in semiconductor substrate.
To solve the above problems, the present invention also provides a kind of transistors formed using the above method, including：Semiconductor serves as a contrast
Bottom；First semiconductor layer of covering part semiconductor substrate surface；Semiconductor substrate positioned at first semiconductor layer both sides
Second semiconductor layer on surface, the energy gap of the material of second semiconductor layer are more than the taboo of the material of the first semiconductor layer
Bandwidth；Positioned at the gate structure of first semiconductor layer surface；The second semiconductor layer positioned at the gate structure both sides
Interior source electrode and drain electrode.
Optionally, the material of first semiconductor layer is germanium silicon, and the material of the second semiconductor layer is silicon.
The surface of optional volume, second semiconductor layer is flushed with the surface of the first semiconductor layer.
Optionally, further include positioned at gate structure both sides the second semiconductor layer in lightly doped district and pocket region, it is described
Pocket region surrounds the lightly doped district, and the Doped ions type in Doped ions type and pocket region in the lightly doped district is not
It is identical.
Optionally, the Doped ions type in the source electrode and drain electrode is identical as the Doped ions type in lightly doped district.
Optionally, part source electrode and drain electrode is located in semiconductor substrate.
Compared with prior art, technical scheme of the present invention has the following advantages：
Technical scheme of the present invention is formed on a semiconductor substrate after the first semiconductor layer, and the first semiconductor of part is removed
Layer forms the first groove, forms the second semiconductor layer, the forbidden band of the material of second semiconductor layer in first groove
Width is more than the energy gap of the material of the first semiconductor layer, and PMOS transistor is formed subsequently in second semiconductor layer
Source electrode and drain electrode.Compared with forming source electrode and drain electrode directly in first semiconductor layer, due to the material of the second semiconductor layer
Expect that energy gap is more than the energy gap of the material of the first semiconductor layer, can reduce between source electrode and drain electrode and semiconductor substrate
The leakage current of the PN junction of formation, so as to improve the performance of transistor.Also, since the carrier of PMOS transistor is sky
Cave, the energy gap of source electrode and drain electrode material are more than the energy gap of the material of channel region, can't influence holoe carrier
Migration between source electrode, drain electrode and channel region, to not interfere with the performance of PMOS transistor.
Further, in technical scheme of the present invention, the material of first semiconductor layer is SiGe, the second semiconductor layer
Material be silicon, the energy gap of the silicon is more than the energy gap of SiGe.Transistor is formed in the first semiconductor layer surface
Gate structure can improve the mobility in hole, to improve the PMOS of formation since the material of the first semiconductor layer is SiGe
The carrier mobility of transistor improves the performance of PMOS transistor.
Further, it in technical scheme of the present invention, before forming the source electrode and drain electrode, is carried out in the silicon layer light
Doped ions inject and pocket ion implanting, form lightly doped district and pocket region.The lightly doped district can reduce short channel effect
It answers, the pocket region can stop that the Doped ions in the source electrode and drain electrode being subsequently formed are spread into channel region, avoid source
Punchthrough effect is leaked, to improve the performance of transistor.
Description of the drawings
Fig. 1 is the structural schematic diagram of the PMOS transistor of the prior art of the present invention；
Fig. 2 to Figure 14 is the structural schematic diagram of the forming process of the PMOS transistor of the embodiment of the present invention.
Specific implementation mode
As described in the background art, the performance needs of the PMOS transistor formed in the prior art further increase.
The study found that migration rate of the carrier hole of PMOS transistor in SiGe is more than the migration speed in silicon
Rate can improve the hole mobility of PMOS transistor using silicon germanium material as the channel material of transistor, to improve
The saturation current of PMOS transistor.But directly formed in the germanium-silicon layer source electrode and drain electrode of the PMOS transistor with
And channel region, it can make have larger junction leakage between the PN junction formed between source electrode and drain electrode and substrate, influence PMOS crystalline substances
The performance of body pipe.Further study show that so that the larger reason of the junction leakage is the energy gap due to silicon germanium material
It is smaller, caused by electronics is easy to happen transition.
Technical scheme of the present invention, the channel region material using the first semiconductor layer as PMOS transistor, using second
The energy gap of material of the semiconductor layer as source electrode and drain electrode, the material of second semiconductor layer is more than the first semiconductor layer
Material energy gap, the leakage current between source electrode and drain electrode and semiconductor substrate can be reduced, so as to improve PMOS
The performance of transistor.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Referring to FIG. 2, providing semiconductor substrate 100.
The material of the semiconductor substrate 100 includes the semi-conducting materials such as silicon, germanium, SiGe, GaAs, the semiconductor
Substrate 100 can be that body silicon materials can also be composite construction such as silicon-on-insulator.Those skilled in the art can be according to half
The semiconductor devices formed on conductor substrate 100 selects the type of the semiconductor substrate 100, therefore the semiconductor substrate
Type should not limit the scope of the invention.In the present embodiment, the semiconductor substrate 100 is crystalline silicon.Subsequently described
PMOS transistor is formed in semiconductor substrate 100.
Referring to FIG. 3, forming the first semiconductor layer 200 on 100 surface of the semiconductor substrate.
In the present embodiment, the material of first semiconductor layer 200 is SiGe, in other embodiments of the invention, institute
State the material material with higher hole mobility that can also be other of the first semiconductor layer 200.
Specifically, in the present embodiment, first semiconductor layer 200 is formed using epitaxy technique.The epitaxy technique
Temperature is 600 DEG C~1100 DEG C, and pressure is the support of 1 support~500, and the silicon source gas used is SiH4Or SiH2Cl2, ge source gas is
GeH4, further include HCl gases and hydrogen, wherein silicon source gas, ge source gas, HCl flow be 1sccm~
The flow of 1000sccm, hydrogen are 0.1slm~50slm.
Use the thickness for first semiconductor layer 200 that epitaxy technique formed for 2nm~200nm, subsequently described the
200 surface of semi-conductor layer forms gate structure so that the channel region of the PMOS transistor of formation, which is located at described the first half, leads
In body layer 200, due to first semiconductor layer 200 material be SiGe or other materials with higher hole mobility,
So the mobility in hole in PMOS transistor can be improved, to improve the performance of PMOS transistor.
Referring to FIG. 4, forming mask layer 300 on 200 surface of the first semiconductor layer.
In the present embodiment, the mask layer 300 includes the silicon oxide layer 301 positioned at 200 surface of the first semiconductor layer
With the silicon nitride layer 302 positioned at 301 surface of the silicon oxide layer.The silicon oxide layer 301 can reduce silicon nitride layer 302 and
Stress caused by being mismatched due to lattice between semi-conductor layer 200.
In other embodiments of the invention, the mask layer 300 can also be the silicon oxide layer or silicon nitride layer of single layer,
It can also be NON（Silicon-nitride and silicon oxide-silicon nitride）Three level stack structure.
The mask layer 300 is subsequently used for forming Patterned masking layer, defines the position of gate structure.
Referring to FIG. 5, etching the mask layer 300（It please refers to Fig.4）, Patterned masking layer 310 is formed, it is described graphical
310 the first semiconductor layer of covering part silicon 200 of mask layer.
The method for specifically forming the Patterned masking layer 310 includes：Photoresist is formed on 300 surface of the mask layer
Layer, is exposed development to the photoresist layer, defines the positions and dimensions for the Patterned masking layer being subsequently formed；With described
Photoresist layer is mask, etches the mask layer 300 using dry etch process, forms Patterned masking layer 310, the figure
Changing mask layer 310 includes：Positioned at the partial oxidation silicon layer 311 on 200 surface of the first semiconductor layer and positioned at the part oxygen
The partial nitridation silicon layer 312 on 311 surface of SiClx layer.The Patterned masking layer 310 defines the PMOS transistor being subsequently formed
Gate structure size and position.
Referring to FIG. 6, being mask with the Patterned masking layer 310, first semiconductor layer 200 is etched（It please refers to
Fig. 5）, the first groove 201 is formed, first groove 201 exposes the surface of part semiconductor substrate 100.
In the present embodiment, first semiconductor layer 200 is etched using dry etch process（Please refer to Fig. 5）, form position
The first semiconductor layer of part 210 in 310 lower section of Patterned masking layer, and it is located at 200 liang of the first semiconductor layer of the part
First groove 201 of side.
First groove 201 exposes the surface of part semiconductor substrate 100, subsequently in first groove 201
Filling semiconductor material forms source electrode and drain electrode.
Referring to FIG. 7, forming the second semiconductor layer 202 in first groove.
In the present embodiment, the material of second semiconductor layer 202 is silicon, and the energy gap of silicon is wide more than the forbidden band of SiGe
Degree.It in other embodiments of the invention, can be according to suitable second semiconductor layer of material selection of the first semiconductor layer 200
Material, make the material of the second semiconductor layer energy gap be more than the first semiconductor layer material energy gap.
In the present embodiment, second semiconductor layer 202 is formed using epitaxy technique, the temperature of the epitaxy technique is
600 DEG C~1100 DEG C, pressure is the support of 1 support~500, and silicon source gas is SiH4Or SiH2Cl2, further include HCl gases and hydrogen,
Wherein silicon source gas, HCl flow be 1sccm~1000sccm, the flow of hydrogen is 0.1slm~50slm.
The epitaxy technique can preferably control the thickness of the second semiconductor layer 202 of formation, described in the present embodiment
The consistency of thickness of the thickness and the first semiconductor layer of part 210 of second semiconductor layer 202, the table of second semiconductor layer 202
Face is flushed with the surface of the first semiconductor layer of part 210.
In other embodiments of the invention, the surface of second semiconductor layer 202 can also be slightly below the part
The surface of first semiconductor layer 210.If the surface of second semiconductor layer 202 is higher than the first semiconductor layer of the part
210 surface, second semiconductor layer 202 and subsequently 210 surface of germanium-silicon layer formed gate structure between can connect
It connects, influences the performance of transistor being subsequently formed.
Referring to FIG. 8, forming dielectric layer 400, the surface of the dielectric layer 400 on 202 surface of the second semiconductor layer
It is flushed with the surface of Patterned masking layer 310.
The material of the dielectric layer 400 is silica or silicon oxynitride, the material and pattern mask of the dielectric layer 400
The material of layer 310 differs, convenient for removing the Patterned masking layer 310 in subsequent technique.In the present embodiment, the dielectric layer
400 material is silica.
Specifically, the method for forming the dielectric layer 400 in the present embodiment includes：Using chemical vapor deposition method in institute
Filled media material in the first groove 201 is stated, the dielectric material filling completely first groove 201 simultaneously covers described graphical
The surface of mask layer 310；Using the top surface of the Patterned masking layer 310 as stop-layer, using chemical machinery masking process
The dielectric material is planarized, the dielectric layer 400 is formed, makes surface and the pattern mask of the dielectric layer 400
The top surface of layer 310 flushes.
Referring to FIG. 9, removing the Patterned masking layer 310（Please refer to Fig. 8）, form the second groove 401.
Wet etching may be used or dry etch process removes the Patterned masking layer 310, form the second groove
401.Second groove 401 exposes the surface of the first semiconductor layer of part 210, subsequently the shape in second groove 401
At the gate structure positioned at 210 surface of the first semiconductor layer of the part.
Referring to FIG. 10, in second groove 401（Please refer to Fig. 9）Bottom surface forms gate dielectric layer 501 and position
Full second groove 401, and the gate material layers 500 of blanket dielectric layer 400 are filled in 501 surface of the gate dielectric layer.
The material of the gate dielectric layer 501 is silica, and thickness is 1nm~100nm.The gate dielectric layer 501 uses oxygen
Chemical industry skill is formed, and the oxidation technology can be thermal oxidation technology or wet process oxidation technology, and the grid are formed using oxidation technology
Dielectric layer 501, can repair first semiconductor layer surface due to damage caused by etching technics, described in oxidation technology
The synthesis speed of gate dielectric layer is relatively low, can preferably control the thickness of the finally formed gate dielectric layer 501.
The material of the gate material layers 500 is polysilicon, and the gate material layers are formed using chemical deposition process
500。
In other embodiments of the invention, the material of the gate dielectric layer 501 can also be HfO2、La2O3、HfSiON
Or other high K dielectric materials, the gate dielectric layer 501 can also be formed using atom layer deposition process.The gate material layers
500 material can be one kind or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi
Kind.
1 is please referred to Fig.1, is stop-layer with the dielectric layer 400, to the gate material layers 500（Please refer to Fig.1 0）Into
Row planarization forms grid 502.
The surface of the grid 502 is flushed with the surface of dielectric layer 400.After the gate dielectric layer 501 is used as with grid 502
The gate structure of the continuous PMOS transistor formed.The gate structure is located at the top of the first semiconductor layer of part 210.Positioned at grid
The first semiconductor layer of part 210 below the structure of pole is used as channel region, can improve the mobility in hole, follow-up to improve
The performance of the PMOS transistor of formation.
2 are please referred to Fig.1, the dielectric layer of the gate dielectric layer 501 and gate structure both sides is removed, exposes the second semiconductor
The surface of layer 202.
Wet etching may be used or dry etch process removes the dielectric layer 400.In the present embodiment, using wet method
Etching technics removes the dielectric layer 400, and the solution of the wet etching is hydrofluoric acid solution.
Source electrode and drain electrode is subsequently formed in second semiconductor layer 202.
Please refer to Fig.1 3, carry out being lightly doped in the second semiconductor layer 202 of the gate structure both sides ion implanting and
Pocket ion implanting, is respectively formed lightly doped district 601 and pocket region 602, and the pocket region 602 surrounds the lightly doped district.
The ionic type that ion implanting injection is lightly doped is p-type ion, include at least in B, Ga or In it is a kind of from
Son.The ion implanting that is lightly doped forms lightly doped district 601, can improve short-channel effect, improve the performance of transistor.
The ionic type of the pocket ion implanting injection is N-type ion, includes at least one kind in P, As, Sb.It is described
Pocket ion implanting forms pocket region 602, and the depth of the pocket region 602 is more than the depth of lightly doped district 601.The present embodiment
In, the pocket region 602 surrounds the lightly doped district 601.The pocket ion implanting, which forms pocket region 602, can stop subsequently
Doped ions in the source electrode and drain electrode of formation are spread into channel region, avoid Punchthrough effect.
In the present embodiment, ion implanting is first lightly doped described in progress and forms lightly doped district 601.It is described that ion implanting is lightly doped
Ion be B, the dosage of the ion implanting is 1E14atom/cm2~3E15atom/cm2, the energy range of injection is
The range of tilt angles of 0.5KeV~10KeV, injection are 0 degree~15 degree.
After forming the lightly doped district 601, using the gate structure be mask to the progress pocket of the silicon layer 202 from
The ion of son injection, the pocket ion implanting is P, and ion energy is 15KeV~60KeV, dosage 3E13atom/cm2~
3E14atom/cm2, ion implantation angle is 25 degree~35 degree.The Doped ions of the pocket region 602 and the doping of lightly doped district
Ion electrically on the contrary, so that the lightly doped district 601 narrows in the depletion region below the gate structure, alleviates short channel effect
It answers.
4 are please referred to Fig.1, side wall 503 is formed in the sidewall surfaces of the gate dielectric layer 501 and grid 502, with the side wall
503 and grid 502 and mask, to carrying out heavy doping ion injection, shape in the second semiconductor layer 202 of 502 both sides of the grid
At source electrode 603 and drain electrode 604.
The ionic type of the heavy doping ion injection is p-type ion, includes at least one kind in B, Ga, In.To described
Second semiconductor layer 202 carries out heavy doping ion injection, forms source electrode 603 and drain electrode 604, the source electrode 603 and drain electrode 604
In in silicon layer 202.In other embodiments of the invention, part source electrode 603 and drain electrode 604 are also located in semiconductor substrate 100.
In the present embodiment, after carrying out the heavy doping ion injection, is also made annealing treatment, be lightly doped described in activation
Doped ions in area 601, pocket region 602 and source electrode 603 and drain electrode 604.
In other embodiments of the invention, can also be lightly doped described in progress ion implanting, pocket ion implanting, in
After Doped ions injection, is made annealing treatment respectively, activate the lightly doped district 601, pocket region 602 and source electrode 603 respectively
With the Doped ions in drain electrode 604.
In the present embodiment, since the source electrode 603 and the material of drain electrode 604 are silicon, the energy gap of silicon is more than SiGe
Energy gap, so more difficult generation electron transition, thus compared with directly using silicon germanium material as source electrode and drain electrode material, it can
To reduce the junction leakage of the PN junction formed between source electrode 603 and drain electrode 604 and substrate, to improve the saturation electricity of transistor
Stream.Also, since the carrier of PMOS transistor is hole, the energy gap of 604 materials of source electrode 603 and drain electrode is more than channel region
The energy gap of the material in domain can't influence migration of the holoe carrier between source electrode, drain electrode and channel region, to not
Influence whether the performance of PMOS transistor.
And the channel region material of the PMOS transistor for using the above method to be formed can improve raceway groove for SiGe
The mobility in interior hole, to improve the performance of transistor.
The embodiment of the present invention additionally provides a kind of transistor formed using the above method.
4 are please referred to Fig.1, the transistor includes：Semiconductor substrate 100；The of 100 surface of covering part semiconductor substrate
Semi-conductor layer 210；The second semiconductor layer positioned at 100 surface of semiconductor substrate of 210 both sides of the first semiconductor layer
202；Gate structure positioned at 210 surface of the first semiconductor layer, the gate structure include being located at the first semiconductor layer 210
The gate dielectric layer 501 on surface and grid 502 positioned at 501 surface of the gate dielectric layer；Positioned at the gate structure both sides
Source electrode and drain electrode 603 in two semiconductor layers 202.
In the present embodiment, the surface of second semiconductor layer 202 is flushed with 210 surface of the first semiconductor layer.
It is also formed with lightly doped district 601 and pocket region 602, institute in second semiconductor layer 202 of the gate structure both sides
It states pocket region 602 and surrounds the lightly doped district 601, the not phase of the Doped ions type in the lightly doped district 601 and pocket region 602
Together.
The source electrode 603 and the Doped ions type of drain electrode 604 are identical as the Doped ions type in lightly doped district 601.
Gate structure both sides sidewall surfaces are also formed with side wall 503.
In other embodiments of the invention, the part source electrode 603 and drain electrode 604 may be located on semiconductor substrate
In 100.
Channel region below the gate structure of above-mentioned PMOS transistor is the first semiconductor layer 210, in the present embodiment, institute
The material for stating the first semiconductor layer 210 is SiGe, the mobility in hole in PMOS transistor can be improved, to improve formation
The performance of PMOS transistor.And the material of the second semiconductor layer 202 is silicon so that the source electrode 603 of the PMOS transistor and leakage
The material of pole 604 is silicon, and the silicon has larger energy gap so that the more difficult generation transition of electronics, so as to the source of reducing
The junction leakage of PN junction between pole 603 and drain electrode 604 and semiconductor substrate, to improve the performance of transistor.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (12)
1. a kind of forming method of PMOS transistor, which is characterized in that including：
Semiconductor substrate is provided；
The first semiconductor layer is formed in the semiconductor substrate surface；
Patterned masking layer, first semiconductor of Patterned masking layer covering part are formed in first semiconductor layer surface
Layer；
Using the Patterned masking layer as mask, first semiconductor layer is etched, forms the first groove, first groove is sudden and violent
The surface of exposed portion semiconductor substrate；
The second semiconductor layer is formed in first groove, the energy gap of the material of second semiconductor layer is more than first
The energy gap of the material of semiconductor layer；
Dielectric layer is formed in second semiconductor layer surface, the surface of the dielectric layer and the surface of Patterned masking layer are neat
It is flat；
The Patterned masking layer is removed, the second groove is formed；
Gate structure is formed in second groove；
The dielectric layer for removing the gate structure both sides, in the second semiconductor layer of the gate structure both sides formed source electrode and
Drain electrode；
The Patterned masking layer includes positioned at the silicon oxide layer of first semiconductor layer surface and positioned at the silicon oxide layer
The silicon nitride layer on surface；
The method for forming the dielectric layer includes：The filled media material in first groove, the dielectric material filling are full
The surface of first groove and cover graphics mask layer；Using the surface of the Patterned masking layer as stop-layer, using chemical machine
Tool masking process planarizes the dielectric material, forms the dielectric layer.
2. the forming method of PMOS transistor according to claim 1, which is characterized in that the material of first semiconductor layer
Material is SiGe.
3. the forming method of PMOS transistor according to claim 2, which is characterized in that the thickness of first semiconductor layer
Degree is 2nm~200nm.
4. the forming method of PMOS transistor according to claim 2, which is characterized in that the material of second semiconductor layer
Material is silicon.
5. the forming method of PMOS transistor according to claim 4, which is characterized in that formed in first groove
The technique of second semiconductor layer is selective deposition technique.
6. the forming method of PMOS transistor according to claim 1, which is characterized in that the table of second semiconductor layer
Face is flushed with the first semiconductor layer surface.
7. the forming method of PMOS transistor according to claim 1, which is characterized in that the material of the dielectric layer is oxygen
SiClx.
8. the forming method of PMOS transistor according to claim 4, which is characterized in that remove the gate structure both sides
Dielectric layer after, formed before the source electrode and drain electrode, carried out in the second semiconductor layer of the gate structure both sides light
Doped ions inject and pocket ion implanting, are respectively formed lightly doped district and pocket region, are lightly doped described in the pocket region encirclement
Area.
9. the forming method of PMOS transistor according to claim 8, which is characterized in that the ion implanting that is lightly doped
Ionic type and the ionic type of pocket ion implanting differ.
10. the forming method of PMOS transistor according to claim 9, which is characterized in that form the source electrode and drain electrode
Method include：In the gate structure both sides, sidewall surfaces form side wall, using the gate structure and side wall as mask, to institute
It states and carries out heavy doping ion injection in the second semiconductor layer of gate structure both sides.
11. the forming method of PMOS transistor according to claim 10, which is characterized in that the heavy doping ion injection
Ionic type it is identical as the ionic type that ion implanting is lightly doped.
12. the forming method of PMOS transistor according to claim 11, which is characterized in that part source electrode and drain electrode is located at
In semiconductor substrate.
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| CN102368501A (en) * | 2011-10-20 | 2012-03-07 | 中山大学 | GaN based enhanced MOSHFET device and preparation method thereof |
| CN103155123A (en) * | 2010-10-15 | 2013-06-12 | 国际商业机器公司 | Method and structure for pFET junction profile with SiGe channel |
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| US7517741B2 (en) * | 2005-06-30 | 2009-04-14 | Freescale Semiconductor, Inc. | Single transistor memory cell with reduced recombination rates |
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| CN103155123A (en) * | 2010-10-15 | 2013-06-12 | 国际商业机器公司 | Method and structure for pFET junction profile with SiGe channel |
| CN102368501A (en) * | 2011-10-20 | 2012-03-07 | 中山大学 | GaN based enhanced MOSHFET device and preparation method thereof |
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