KR100922714B1 - 솔더 레지스트 댐이 형성된 비오씨 반도체 패키지 기판 및그 제조방법 - Google Patents
솔더 레지스트 댐이 형성된 비오씨 반도체 패키지 기판 및그 제조방법 Download PDFInfo
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- KR100922714B1 KR100922714B1 KR1020070116424A KR20070116424A KR100922714B1 KR 100922714 B1 KR100922714 B1 KR 100922714B1 KR 1020070116424 A KR1020070116424 A KR 1020070116424A KR 20070116424 A KR20070116424 A KR 20070116424A KR 100922714 B1 KR100922714 B1 KR 100922714B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Wire Bonding (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
Claims (5)
- 동 적층판(CCL) 상에 드릴을 이용하여 복수의 도통홀을 형성하고, 베이스 기판의 전면을 동도금하여, 상기 기판상에 드라이 필름을 적층하고 현상한 뒤 식각에 의해 동박을 제거하여 회로패턴을 형성하는 비오씨 반도체 패키지 기판의 제조방법에 있어서,상기 회로패턴의 소정부위에 솔더 레지스트를 도포한 후 노광, 현상 및 건조시키며, 상기 기판의 중앙부에 형성될 윈도우에 접하도록 솔더 레지스트 댐을 형성하는 1단계;상기 1단계에서 건조를 통해 와이어 본딩 패드 및 솔더볼 패드를 노출시키는 2단계;상기 2단계에서 노출된 솔더볼 패드 및 와이어 본딩 패드를 니켈ㆍ 금도금하는 3단계;상기 3단계 후, 기판 중앙부위의 상기 윈도우를 라우터 또는 펀칭으로 가공하는 4단계;를 포함하되, 상기 솔더 레지스트댐은 상기 윈도우 절단면으로부터 50~500um 폭을 갖되 상기 윈도우를 중심으로 양쪽에 직선형태로 형성하는 것을 특징으로 하는 솔더레지스트 댐이 형성된 비오씨 반도체 패키지 기판 제조방법.
- 제 1항에 있어서,상기 솔더레지스트 댐은 상기 윈도우를 중심으로 테두리 형태로 형성되는 것을 특징으로 하는 솔더레지스트 댐이 형성된 비오씨 반도체 패키지 기판 제조방법.
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Priority Applications (1)
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KR1020070116424A KR100922714B1 (ko) | 2007-11-15 | 2007-11-15 | 솔더 레지스트 댐이 형성된 비오씨 반도체 패키지 기판 및그 제조방법 |
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KR1020070116424A KR100922714B1 (ko) | 2007-11-15 | 2007-11-15 | 솔더 레지스트 댐이 형성된 비오씨 반도체 패키지 기판 및그 제조방법 |
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KR20090050149A KR20090050149A (ko) | 2009-05-20 |
KR100922714B1 true KR100922714B1 (ko) | 2009-10-22 |
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Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101641527B1 (ko) * | 2009-10-09 | 2016-07-21 | 해성디에스 주식회사 | 센서용 칩 패키지, 이를 구비한 카메라 모듈 및 센서용 칩 패키지 제조방법 |
KR101036441B1 (ko) | 2010-12-21 | 2011-05-25 | 한국기계연구원 | 반도체 칩 적층 패키지 및 그 제조 방법 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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KR19980020726A (ko) * | 1996-09-11 | 1998-06-25 | 김광호 | 칩 스케일의 볼 그리드 어레이 패키지 및 그의 제조 방법 |
JP2001358258A (ja) | 2000-06-12 | 2001-12-26 | Hitachi Cable Ltd | Bga型半導体装置 |
KR20040076165A (ko) * | 2003-02-24 | 2004-08-31 | 삼성전기주식회사 | 도금 인입선을 사용하지 않는 패키지 기판 및 그 제조 방법 |
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- 2007-11-15 KR KR1020070116424A patent/KR100922714B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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KR19980020726A (ko) * | 1996-09-11 | 1998-06-25 | 김광호 | 칩 스케일의 볼 그리드 어레이 패키지 및 그의 제조 방법 |
JP2001358258A (ja) | 2000-06-12 | 2001-12-26 | Hitachi Cable Ltd | Bga型半導体装置 |
KR20040076165A (ko) * | 2003-02-24 | 2004-08-31 | 삼성전기주식회사 | 도금 인입선을 사용하지 않는 패키지 기판 및 그 제조 방법 |
KR100584966B1 (ko) | 2003-02-24 | 2006-05-29 | 삼성전기주식회사 | 패키지 기판 및 그 제조 방법 |
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