KR100899567B1 - Method for fabricating semiconductor device with gate-electrode including tungsten - Google Patents

Method for fabricating semiconductor device with gate-electrode including tungsten Download PDF

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KR100899567B1
KR100899567B1 KR1020020086255A KR20020086255A KR100899567B1 KR 100899567 B1 KR100899567 B1 KR 100899567B1 KR 1020020086255 A KR1020020086255 A KR 1020020086255A KR 20020086255 A KR20020086255 A KR 20020086255A KR 100899567 B1 KR100899567 B1 KR 100899567B1
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nitride film
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홍병섭
오재근
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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Abstract

본 발명은 텅스텐막을 포함하는 게이트전극 형성후에 진행하는 선택산화 공정시 텅스텐 오염이 발생되는 것을 방지하는데 적합한 반도체 소자의 제조 방법을 제공하기 위한 것으로, 본 발명은 반도체 기판 상에 게이트산화막, 폴리실리콘막, 텅스텐막 및 하드마스크의 순서로 적층된 적층막을 형성하는 단계, 상기 적층막을 포함한 상기 반도체 기판 상에 상기 적층막의 상면부에 형성되는 두께가 상기 적층막의 측면부 및 상기 반도체 기판 상에 형성되는 두께보다 두꺼운 실리콘질화막을 저온 플라즈마화학기상증착법을 이용하여 형성하는 단계, 상기 반도체 기판의 표면이 노출될때까지 상기 실리콘질화막을 선택적으로 제거하여 상기 적층막의 상면부 및 측면부를 덮는 스페이서를 형성하는 단계, 상기 적층막 중에서 상기 폴리실리콘막만을 선택적으로 산화시키는 선택산화 단계, 및 상기 스페이서를 포함한 전면에 게이트실링질화막을 형성하는 단계를 포함하므로써, 선택산화 공정전에 미리 PE-실리콘질화막을 형성하여 텅스텐 오염을 근본적으로 차단한다.The present invention provides a method of manufacturing a semiconductor device suitable for preventing tungsten contamination from occurring during the selective oxidation process that proceeds after the formation of a gate electrode including a tungsten film. The present invention provides a gate oxide and polysilicon film on a semiconductor substrate. Forming a laminated film in the order of a tungsten film and a hard mask, wherein a thickness formed on an upper surface of the laminated film on the semiconductor substrate including the laminated film is greater than a thickness formed on the side surface of the laminated film and the semiconductor substrate. Forming a thick silicon nitride film using a low temperature plasma chemical vapor deposition method, selectively removing the silicon nitride film until the surface of the semiconductor substrate is exposed to form a spacer covering the top and side portions of the laminated film; Only the polysilicon film is selected among the films By previously forming a silicon nitride film PE- choice for oxidizing the oxidation step, and by including the step of forming a nitride film on the front gate seals, including the spacers, before the selective oxidation step will be essentially blocked by the tungsten contamination.

선택산화, 텅스텐 증기, 텅스텐 오염, 저온 플라즈마화학기상증착법, 실리콘질화막, 이상산화, 게이트 버드빅Selective Oxidation, Tungsten Vapor, Tungsten Contamination, Low Temperature Plasma Chemical Vapor Deposition, Silicon Nitride, Ideal Oxidation, Gate Budvik

Description

텅스텐막을 포함하는 게이트전극을 구비한 반도체 소자의 제조 방법{Method for fabricating semiconductor device with gate-electrode including tungsten} Method for fabricating a semiconductor device having a gate electrode including a tungsten film {Method for fabricating semiconductor device with gate-electrode including tungsten}             

도 1은 종래 기술에 따른 텅스텐막을 포함하는 게이트전극을 구비한 반도체 소자의 제조 방법을 간략히 도시한 도면,1 is a view schematically illustrating a method of manufacturing a semiconductor device having a gate electrode including a tungsten film according to the prior art;

도 2는 종래 기술에 따른 텅스텐 오염도를 나타낸 도면,2 is a view showing a tungsten pollution degree according to the prior art,

도 3a 내지 도 3e는 본 발명의 실시예에 따른 텅스텐막을 포함하는 게이트전극을 구비한 반도체 소자의 제조 방법을 도시한 공정 단면도이다.3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device having a gate electrode including a tungsten film according to an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 게이트산화막21 semiconductor substrate 22 gate oxide film

23 : 폴리실리콘막 24 : 텅스텐질화막23 polysilicon film 24 tungsten nitride film

25 : 텅스텐막 26 : 하드마스크25 tungsten film 26 hard mask

27 : PE-실리콘질화막 27a : PE-실리콘질화막스페이서27: PE-silicon nitride film 27a: PE-silicon nitride film spacer

28 : 게이트 버드빅 29a, 29b : 실리콘산화막28: gate Budvik 29a, 29b: silicon oxide film

30 : 게이트실링질화막
30: gate sealing nitride film

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 텅스텐막을 포함하는 게이트전극을 구비한 반도체소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a gate electrode comprising a tungsten film.

최근에 반도체소자가 고집적화됨에 따라 소스 및 드레인영역으로 이용되는 불순물영역과 게이트전극의 폭이 감소되고 있다. 이에 따라, 반도체소자는 불순물영역의 접촉 저항 및 게이트전극의 시트저항(Sheet resistance; Rs)이 증가하여 동작 속도가 저하되는 문제점이 발생되었다.Recently, as semiconductor devices have been highly integrated, the widths of impurity regions and gate electrodes used as source and drain regions have decreased. Accordingly, the semiconductor device has a problem in that an operating speed decreases due to an increase in contact resistance of an impurity region and sheet resistance (Rs) of a gate electrode.

그러므로, 반도체소자 내의 소자들의 배선을 알루미늄 합금 및 텅스텐 등의 저저항 물질로 형성하거나, 또는, 게이트전극과 같이 다결정실리콘으로 형성하는 경우에 실리사이드층(silicide)을 형성하여 저항을 감소시킨다. Therefore, in the case where the wirings of the elements in the semiconductor element are formed of low-resistance materials such as aluminum alloy and tungsten, or formed of polycrystalline silicon such as the gate electrode, a silicide layer is formed to reduce the resistance.

한편, 게이트전극으로 폴리실리콘막을 적용하는 반도체소자 제조에서는 폴리실리콘막 식각시에 드러나는 게이트산화막이 손상되므로, 게이트전극의 저항은 그대로 유지하면서 손상된 게이트산화막을 회복하기 위해 폴리실리콘막의 측면을 선택적으로 산화시키는 재산화(Re-oxidation) 공정이 수반된다.On the other hand, in the semiconductor device fabrication using the polysilicon film as the gate electrode, since the gate oxide film exposed during the polysilicon film etching is damaged, the side surface of the polysilicon film is selectively oxidized to recover the damaged gate oxide film while maintaining the resistance of the gate electrode. Re-oxidation is involved.

여기서, 게이트산화막의 재산화 공정은 게이트전극 식각시 게이트산화막에 발생된 마이크로트렌치(microtrench) 및 손실을 회복시켜 주며, 실리콘기판에 잔류하는 폴리실리콘막 잔막을 산화시키며, 게이트전극의 에지에 있는 게이트산화막의 두께를 증가시켜서 신뢰성을 향상시키기 위한 목적으로 진행되고 있다.Here, the reoxidation process of the gate oxide film recovers the microtrench and loss generated in the gate oxide film during etching of the gate electrode, oxidizes the remaining polysilicon film remaining on the silicon substrate, and gates at the edge of the gate electrode. In order to improve the reliability by increasing the thickness of the oxide film, progress is being made.

특히, 게이트전극의 에지쪽에 있는 산화막은 그 두께 및 막의 품질에 의해 핫캐리어 특성, 서브 문턱전압(sub-threshold voltage) 특성[누설전류, 게이트유도드레인누설(GIDL)], 펀치쓰루(punchthrough) 특성, 소자 동작 속도에 많은 영향을 미친다.In particular, the oxide film on the edge of the gate electrode has hot carrier characteristics, sub-threshold voltage characteristics (leakage current, gate induced drain leakage (GIDL)), and punchthrough characteristics depending on the thickness and film quality. This greatly affects the speed of device operation.

그렇기 때문에 재산화공정은 필수적으로 진행되어야 한다.For this reason, the reprocessing process must be indispensable.

최근에는 게이트전극의 저항을 낮추기 위해 폴리실리콘막, 텅스텐질화막 및 텅스텐막의 적층 게이트 구조(W/WN/Polysilicon)를 사용하고 있다.Recently, in order to lower the resistance of the gate electrode, a laminated gate structure (W / WN / Polysilicon) of a polysilicon film, a tungsten nitride film, and a tungsten film is used.

그러나, 폴리실리콘막, 텅스텐질화막 및 텅스텐막의 적층 게이트 구조는 후속 H2O 또는 O2를 이용한 높은 온도의 재산화 공정시 폴리실리콘막, 텅스텐질화막 및 텅스텐막의 계면반응 및 텅스텐막의 산화에 따른 급격한 부피 팽창, 파티클 발생 등의 문제가 발생한다. However, the laminated gate structure of the polysilicon film, tungsten nitride film and tungsten film has a sudden volume due to the interfacial reaction of the polysilicon film, tungsten nitride film and tungsten film and the oxidation of the tungsten film during the high temperature reoxidation process using H 2 O or O 2 . Problems such as swelling and particle generation occur.

이를 극복하기 위해 개발된 공정이 선택 산화(Selective oxidation) 공정이다. 즉, 수소 부화(H2 rich)의 산화 분위기(H2O, H2)에서 텅스텐막과 텅스텐질화막(W/WN)은 산화시키지 않고, 폴리실리콘막 및 실리콘기판만을 산화시키는 공정이다.The process developed to overcome this is a selective oxidation process. That is, the tungsten film and the tungsten nitride film (W / WN) are not oxidized in the hydrogen atmosphere (H 2 rich) in the oxidizing atmosphere (H 2 O, H 2 ), and only the polysilicon film and the silicon substrate are oxidized.

이와 같은 선택산화 공정은 GIDL(Gate Induced Drain Leakage) 특성을 확보하기 위하여 반드시 필요한 게이트 버드빅(gate bird's beak)을 형성하기 위한 것이다.This selective oxidation process is to form a gate bird's beak, which is necessary to secure the gate induced drain leakage (GIDL) characteristics.

도 1은 종래 기술에 따른 텅스텐막을 포함하는 게이트전극을 구비한 반도체 소자의 제조 방법을 간략히 도시한 공정 단면도이다. 1 is a cross-sectional view briefly illustrating a method of manufacturing a semiconductor device having a gate electrode including a tungsten film according to the prior art.                         

도 1에 도시된 바와 같이, 필드산화막(FOX)이 형성된 반도체 기판(11) 상에 게이트산화막(12)을 성장시키고, 게이트산화막(12) 상에 폴리실리콘막(13), 텅스텐질화막(14), 텅스텐막(15) 및 하드마스크(16)를 차례로 증착한다. 다음에, 하드마스크(16), 텅스텐막(15), 텅스텐질화막(14) 및 폴리실리콘막(13)을 순차적으로 식각하여 게이트전극을 정의한다.As shown in FIG. 1, the gate oxide film 12 is grown on the semiconductor substrate 11 on which the field oxide film FOX is formed, and the polysilicon film 13 and the tungsten nitride film 14 are formed on the gate oxide film 12. , The tungsten film 15 and the hard mask 16 are deposited in this order. Next, the hard mask 16, the tungsten film 15, the tungsten nitride film 14 and the polysilicon film 13 are sequentially etched to define a gate electrode.

다음에, 게이트 버드빅(17)을 형성하기 위하여 H2O 분위기에서 선택 산화 공정을 실시한다. 이때, 폴리실리콘막(13)의 측면만 선택적으로 산화시켜 폴리실리콘막(13)의 양측벽에 실리콘산화막(18a)을 형성시키며, 아울러 반도체 기판(11)에도 실리콘산화막(18b)이 형성된다.Next, a selective oxidation process is performed in an H 2 O atmosphere to form the gate budic 17. At this time, only the side surface of the polysilicon film 13 is selectively oxidized to form the silicon oxide film 18a on both side walls of the polysilicon film 13, and the silicon oxide film 18b is also formed on the semiconductor substrate 11.

다음에, 텅스텐막이 후속 열공정에서 산화되는 것을 방지하기 위하여 게이트전극을 포함한 전면에 게이트실링질화막(gate sealing nitride, 19)을 형성한다.Next, a gate sealing nitride 19 is formed on the entire surface including the gate electrode in order to prevent the tungsten film from being oxidized in a subsequent thermal process.

그러나, 종래기술과 같이, 폴리실리콘막, 텅스텐질화막 및 텅스텐막의 삼중막(W/WN/Polysilicon)의 게이트전극을 채용하는 DRAM 반도체소자에서 데이터 리텐션 타임(Data retention time) 특성 저하의 문제점이 나타나고 있다. 이와 같은 문제점은 GIDL 특성을 확보하기 위하여 반드시 필요한 게이트 버드빅(19)을 형성하기 위하여 선택 산화 공정을 실시하는데, 이 선택적 산화 공정 진행시 텅스텐막(15)과 H2O의 반응으로 WH2O4라는 텅스텐 증기(W vapor)가 발생하고 이 텅스텐 증기에 의하여 선택산화 장비와 웨이퍼의 표면을 오염시키기 때문에 발생한다. 이로써, 게이트전극 모서리부나 실리콘 기판에 텅스텐 오염을 야기하여 채널이나 셀접합에 트랩 사이트(trap site)나 텅스텐실리사이드 같은 결함 등을 생성시키고, 이들을 통한 접합 누설(junction leakage)이 커져서 반도체 소자의 리프레시 특성을 저하시키는 결과를 가져온다.However, as in the prior art, a problem of deterioration of data retention time characteristics appears in DRAM semiconductor devices employing polysilicon, tungsten nitride, and tungsten triple electrode (W / WN / Polysilicon) gate electrodes. have. This problem is performed by the selective oxidation process to form the gate Budvik (19), which is essential to ensure the GIDL characteristics, WH 2 O by the reaction of the tungsten film 15 and H 2 O during the selective oxidation process 4 the steam tungsten (W vapor) occurs and that occurs due to contamination of the surface of the selective oxidation device and a wafer, by a tungsten vapor. As a result, tungsten contamination may be caused on the edges of the gate electrode and the silicon substrate, thereby causing defects such as trap sites and tungsten silicides in the channel and cell junctions. Results in deterioration.

현재, 0.13㎛ 이하 기술 제품에서의 게이트전극 이후 공정 절차에서는 이 선택 산화 공정 전후에 텅스텐 오염을 제거하기 위하여 황산계 화학용액이나 불산계열 용액으로 후세정 처리를 하여 텅스텐막을 녹여내는 방법으로 텅스텐 오염수치를 2 오더 정도 낮추고 있으나, 오염되지 않은 경우에 비하여 여전히 2오더 정도 높은 수치를 유지하고 있다.Currently, in the post-gate electrode processing procedure for technology products below 0.13㎛, the tungsten contamination level is melted by post-treatment with sulfuric acid chemical solution or hydrofluoric acid solution to remove tungsten contamination before and after this selective oxidation process. It is lowered by 2 orders, but still maintains 2 orders higher than uncontaminated.

도 2는 종래 기술에 따른 텅스텐 오염도를 나타낸 도면이다. 가로좌표는 후세정처리조건이고, 세로좌표는 텅스텐오염도이다.2 is a view showing a tungsten pollution degree according to the prior art. The abscissa is post-cleaning treatment conditions, and the ordinate is tungsten contamination.

도 2에 도시된 바와 같이, 텅스텐오염이 없다고 가정한 기준치(ref)에 비해 비록 불산(HF)을 이용하여 후세정한다고 하더라도 텅스텐오염이 발생함을 알 수 있다. As shown in FIG. 2, it can be seen that tungsten contamination occurs even after post-cleaning using hydrofluoric acid (HF) compared to a reference value (ref) that assumes no tungsten contamination.

또한, 후속 공정에서 텅스텐막의 이상산화를 방지하기 위하여 증착되는 게이트실링질화막 증착공정중에서도 증착전 열이력에 의하여 추가 오염이 진행되고 있으나 바로 게이트실링질화막이 증착되므로써 오염된 텅스텐이 그대로 표면에 잔존하게 되어 후속 고온 열공정시 텅스텐에 의한 채널이나 접합에서의 문제를 야기시키고 있다. In addition, during the gate sealing nitride film deposition process which is deposited to prevent abnormal oxidation of the tungsten film in the subsequent process, further contamination is progressed by the thermal history before deposition, but immediately after the gate sealing nitride film is deposited, the contaminated tungsten remains on the surface. Subsequent high temperature thermal processes cause problems in channels or junctions by tungsten.

따라서 텅스텐 오염을 방지하기 위하여 근본적으로 텅스텐과 H2O의 반응을 피할 수 있는 방법이 필요하다.
Therefore, in order to prevent tungsten contamination, there is a need for a method that can essentially avoid the reaction of tungsten with H 2 O.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로, 텅스텐막을 포함하는 게이트전극 형성후에 진행하는 선택산화 공정시 텅스텐 오염이 발생되는 것을 방지하는데 적합한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.
The present invention has been made to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor device suitable for preventing the occurrence of tungsten contamination during the selective oxidation process proceeds after the formation of the gate electrode including the tungsten film. There is this.

상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 반도체 기판 상에 게이트산화막, 폴리실리콘막, 텅스텐막 및 하드마스크의 순서로 적층된 적층막을 형성하는 단계, 상기 적층막을 포함한 상기 반도체 기판 상에 상기 적층막의 상면부에 형성되는 두께가 상기 적층막의 측면부 및 상기 반도체 기판 상에 형성되는 두께보다 두꺼운 실리콘질화막을 형성하는 단계, 상기 반도체 기판의 표면이 노출될때까지 상기 실리콘질화막을 선택적으로 제거하여 상기 적층막의 상면부 및 측면부를 덮는 스페이서를 형성하는 단계, 상기 적층막 중에서 상기 폴리실리콘막만을 선택적으로 산화시키는 선택산화 단계, 및 상기 스페이서를 포함한 전면에 게이트실링질화막을 형성하는 단계를 포함하는 것을 특징으로 하고, 상기 실리콘질화막을 형성하는 단계는, 플라즈마화학기상증착법을 이용하고, 증착 단차피복성을 10%∼60%로 하여 이루어지고, 상기 실리콘질화막은 200℃∼550℃의 저온에서 30Å ∼500Å의 두께로 형성하는 것을 특징으로 한다.Method of manufacturing a semiconductor device of the present invention for achieving the above object is to form a laminated film laminated on the semiconductor substrate in the order of a gate oxide film, a polysilicon film, a tungsten film and a hard mask, on the semiconductor substrate including the laminated film Forming a silicon nitride film having a thickness formed on an upper surface portion of the laminated film greater than a thickness formed on the side portion of the laminated film and the semiconductor substrate, and selectively removing the silicon nitride film until the surface of the semiconductor substrate is exposed. Forming a spacer covering an upper surface portion and a side portion of the laminated film, a selective oxidation step of selectively oxidizing only the polysilicon film among the laminated films, and forming a gate sealing nitride film on the entire surface including the spacer; Characterized in that, to form the silicon nitride film The step is carried out by using a plasma chemical vapor deposition method, the deposition step coverage of 10% to 60%, characterized in that the silicon nitride film is formed to a thickness of 30 ~ 500Å at a low temperature of 200 ℃ to 550 ℃. .

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

도 3a 내지 도 3e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 공정 단면도이다.3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a에 도시된 바와 같이, 필드산화막(FOX)이 형성된 반도체 기판(21) 상에 게이트절연막으로 작용하는 실리콘산화막(SiO2, 22)을 증착한 후, 실리콘산화막(22) 상에 도전성을 갖기 위한 불순물이 도핑된 폴리실리콘막(23)을 증착한다. As shown in FIG. 3A, after depositing the silicon oxide films SiO 2 and 22 serving as the gate insulating film on the semiconductor substrate 21 on which the field oxide film FOX is formed, the silicon oxide film 22 has conductivity. A polysilicon film 23 doped with impurities is deposited.

다음으로, 폴리실리콘막(23) 형성시 생성된 자연산화막을 제거하기 위해 HF를 포함한 용액을 이용한 세정을 실시하고, 폴리실리콘막(23) 상에 반응방지막으로 작용하는 텅스텐질화막(24)을 형성한다. 다음에, 텅스텐질화막(24) 상에 텅스텐막(25)을 증착한 후, 텅스텐막(25) 상에 하드마스크(26)를 증착한다. 이때, 하드마스크(26)는 플라즈마화학기상증착법(PECVD) 또는 저압화학기상증착법(LPCVD)을 이용하여 증착한 실리콘질화막이며, 하드마스크(26) 상에 반사방지막(Anti Reflective Coating lyaer)인은 실리콘옥시나이트라이드막(SiON)을 추가로 형성할 수도 있다.Next, in order to remove the natural oxide film generated when the polysilicon film 23 is formed, washing is performed using a solution containing HF, and a tungsten nitride film 24 serving as a reaction prevention film is formed on the polysilicon film 23. do. Next, after the tungsten film 25 is deposited on the tungsten nitride film 24, the hard mask 26 is deposited on the tungsten film 25. At this time, the hard mask 26 is a silicon nitride film deposited using plasma chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), the anti-reflective coating (Anti Reflective Coating lyaer) on the hard mask 26 is silicon. An oxynitride film (SiON) may be further formed.

다음에, 포토리소그래피 과정을 통해 하드마스크(26)를 먼저 식각하고, 감광막 스트립 및 후세정을 실시한 후 식각처리된 하드마스크(26)를 식각마스크로 텅스 텐막(25), 텅스텐질화막(24) 및 폴리실리콘막(23)을 순차적으로 식각하여 게이트전극을 형성한다.Next, the hard mask 26 is first etched through the photolithography process, the photoresist strip and the post-cleaning are performed, and the etched hard mask 26 is etched using the tungsten film 25, the tungsten nitride film 24, and the like. The polysilicon film 23 is sequentially etched to form a gate electrode.

도 3b에 도시된 바와 같이, 게이트전극을 포함한 전면에 저온 플라즈마화학기상증착법(PECVD)을 이용하여 실리콘질화막(이하 'PE-실리콘질화막'이라고 약칭함)( 27)을 증착한다. 이때, 저온 플라즈마화학기상증착법을 이용하여 PE-실리콘질화막(27)을 증착하면, 저온 플라즈마화학기상증착법 특성상 단차피복성(step coverage)이 매우 나쁘다. 즉, 게이트전극의 측면부에 증착되는 두께(d1)에 비해 게이트전극의 상면부에 증착되는 두께(d2)가 더 두껍고, 특히 게이트전극의 모서리 상부에 증착되는 두께가 두껍다.As shown in FIG. 3B, a silicon nitride film (hereinafter abbreviated as 'PE-silicon nitride film') 27 is deposited on the entire surface including the gate electrode by using low temperature plasma chemical vapor deposition (PECVD). At this time, when the PE-silicon nitride film 27 is deposited using a low temperature plasma chemical vapor deposition method, step coverage is very poor due to the low temperature plasma chemical vapor deposition method characteristics. That is, the thickness d 2 deposited on the upper surface of the gate electrode is thicker than the thickness d 1 deposited on the side surface of the gate electrode, and in particular, the thickness deposited on the edge of the gate electrode is thicker.

이와 같이 PE-실리콘질화막(27)을 단차피복성이 나쁜 저온 플라즈마화학기상증착법을 이용하여 증착하면, 게이트전극 형성을 위한 식각시 손실된 하드마스크(26)의 두께를 보상해줄 수 있어 후속 랜딩플러그(Landing plug)를 위한 자기정렬콘택(Self Aligned Contact) 공정의 공정여유도를 증대시킬 수 있다. 따라서, PE-실리콘질화막(27)의 증착 단차피복성을 10%∼60%로 한다. 여기서, 증착 단차피복성 100%는 게이트전극 측면부 증착두께와 게이트전극의 상부 증착두께가 동일한 것을 의미하며, 증착 단차피복성 60%는 게이트전극 측면부 증착두께에 비해 게이트전극의 상부 증착두께가 더 두꺼워 단차피복성이 나빠지는 것을 의미한다.As such, when the PE-silicon nitride layer 27 is deposited using a low temperature plasma chemical vapor deposition method having poor step coverage, the thickness of the hard mask 26 lost during etching for forming the gate electrode can be compensated for, and thus the subsequent landing plugs. The process margin of the self-aligned contact process for the landing plug can be increased. Therefore, the deposition step coverage of the PE-silicon nitride film 27 is 10% to 60%. Here, 100% of the deposition step coverage means that the gate electrode side deposition thickness is the same as the top deposition thickness of the gate electrode, and 60% of the deposition step deposition thickness is higher than the gate electrode side deposition thickness. It means that the step coverage is worsened.

한편, PE-실리콘질화막(27)의 증착 조건에 대해 살펴보면, 텅스텐 증기의 발생을 차단하기 위하여 200℃∼550℃의 저온에서 30Å∼500Å의 두께로 증착하며, 적어도 10-2torr보다 낮은 진공분위기에서 증착한다. On the other hand, the deposition conditions of the PE-silicon nitride film 27, in order to block the generation of tungsten vapor deposited at a thickness of 30 ~ 500Å at a low temperature of 200 ℃ to 550 ℃, at least 10 -2 torr vacuum atmosphere Deposition at

도 3c에 도시된 바와 같이, 반도체 기판(21)의 표면이 드러날때까지 PE-실리콘질화막(27)을 에치백하여 게이트전극의 양측벽 및 게이트전극의 상부를 감싸는 PE-실리콘질화막스페이서(27a)를 형성한다. 이때, PE-실리콘질화막(27)이 단차피복성이 나쁘게 증착되어 있으므로, 에치백후에 게이트전극의 상부에도 잔류하는 것이다.As shown in FIG. 3C, the PE-silicon nitride film spacer 27a encapsulating the PE-silicon nitride film 27 until the surface of the semiconductor substrate 21 is exposed to surround both sidewalls of the gate electrode and the top of the gate electrode. To form. At this time, since the PE-silicon nitride film 27 is deposited with poor step coverage, the PE-silicon nitride film 27 remains on the upper portion of the gate electrode after the etch back.

도 3d에 도시된 바와 같이, 게이트전극 형성을 위한 식각공정으로 인하여 받은 게이트전극 모서리의 손실을 회복시켜주기 위한 선택산화 공정을 진행하여 게이트 버드빅(28)을 형성한다. 이때, 폴리실리콘막(23)만 선택적으로 산화되어 폴리실리콘막(23) 양측벽에 실리콘산화막(29a)이 형성되고, 아울러 스페이서(27a) 형성후 드러난 반도체 기판(21)도 산화되어 실리콘산화막(29b)이 형성된다.As shown in FIG. 3D, the gate bud 28 is formed by performing a selective oxidation process to recover the loss of the edge of the gate electrode received due to the etching process for forming the gate electrode. At this time, only the polysilicon film 23 is selectively oxidized to form a silicon oxide film 29a on both side walls of the polysilicon film 23, and the semiconductor substrate 21 exposed after the formation of the spacer 27a is also oxidized to form a silicon oxide film ( 29b) is formed.

이와 같은 선택산화 공정은 습식 증기 발생 장치가 장착된 급속열처리 방식의 챔버에서 실시하며, 습식증기(H2O vapor)와 수소(H2) 가스의 적절한 혼합비율로 챔버안으로 넣어 텅스텐막(25)은 산화되지 않고 폴리실리콘막(23)과 반도체기판(21)만 선택적으로 산화시킨다. 바람직하게, 선택산화 공정은 800℃∼1000℃의 온도범위에서 H2O:H2의 혼합가스 비율을 0.01:1∼0.5:1의 범위에서 1초∼600초동안 실시한다. 이때, 형성되는 실리콘산화막(29a,29b)은 1Å∼100Å이다.This selective oxidation process is carried out in a rapid heat treatment chamber equipped with a wet steam generator, and put into the chamber at an appropriate mixing ratio of wet steam (H 2 O vapor) and hydrogen (H 2 ) gas tungsten film (25) The silver is not oxidized and only the polysilicon film 23 and the semiconductor substrate 21 are selectively oxidized. Preferably, the selective oxidation process is carried out in a mixed gas ratio of H 2 O: H 2 in the temperature range of 800 ℃ to 1000 ℃ for 1 second to 600 seconds in the range of 0.01: 1 to 0.5: 1. At this time, the silicon oxide films 29a and 29b formed are 1 to 100 microseconds.

한편, 선택산화 공정시 게이트전극의 양측벽 및 상부를 덮는 PE-실리콘질화 막스페이서(27a)가 미리 형성되어 있으므로 텅스텐막(25)과 선택산화시 분위기 가스인 H2O의 직접적인 반응을 방지한다. 즉, 선택산화 공정시 PE-실리콘질화막스페이서(27a)가 텅스텐막(25)내 텅스텐의 아웃개싱(outgassing)을 차단한다.On the other hand, since the PE-silicon nitride spacer 27a is formed in advance to cover both sidewalls and the upper portion of the gate electrode during the selective oxidation process, it prevents direct reaction between the tungsten film 25 and H 2 O, an atmospheric gas during selective oxidation. . That is, during the selective oxidation process, the PE-silicon nitride film spacer 27a blocks outgassing of tungsten in the tungsten film 25.

또한, PE-실리콘질화막스페이서(27a)를 형성한 후 선택산화를 진행하므로써 선택산화시 텅스텐 증기에 의하여 발생하는 웨이퍼내 두께 균일도를 개선시킬 수 있다.In addition, since the selective oxidation is performed after the PE-silicon nitride film spacer 27a is formed, thickness uniformity in the wafer generated by tungsten vapor during selective oxidation can be improved.

도 3e에 도시된 바와 같이, 선택산화 공정후 전면에 텅스텐막(25)의 이상산화를 방지하기 위하여 화학기상증착법(CVD)을 이용하여 게이트실링질화막(30)을 30Å∼500Å의 두께로 증착한다. 이때, 게이트실링질화막(30)은 화학기상증착법(CVD)을 이용하여 증착하므로 단차피복성이 우수하다.As shown in FIG. 3E, in order to prevent abnormal oxidation of the tungsten film 25 on the entire surface after the selective oxidation process, the gate sealing nitride film 30 is deposited to have a thickness of 30 kPa to 500 kPa using chemical vapor deposition (CVD). . In this case, the gate sealing nitride film 30 is deposited using chemical vapor deposition (CVD), so the step coverage is excellent.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같은 본 발명은 선택산화 공정전에 미리 PE-실리콘질화막을 형성하여 텅스텐 오염을 근본적으로 차단하고, 이로써 GOI(Gate Oxide Integrity) 열화와 접합누설을 제거하므로 소자의 데이터리텐션 능력을 극대화하고 리프레시 타 임을 향상시켜 소자의 특성 및 수율을 증대시킬 수 있는 효과가 있다.As described above, the present invention forms a PE-silicon nitride film in advance before the selective oxidation process to fundamentally block tungsten contamination, thereby eliminating GOI (Gate Oxide Integrity) degradation and junction leakage, thereby maximizing the data retention capability of the device. By improving the refresh time, it is possible to increase the characteristics and yield of the device.

또한, PE-실리콘질화막스페이서를 형성한 후 선택산화를 진행하므로써 선택산화시 텅스텐 증기에 의하여 발생하는 웨이퍼내 두께 균일도를 개선시킬 수 있는 효과가 있다.In addition, since the selective oxidation is performed after the PE-silicon nitride film spacer is formed, the thickness uniformity in the wafer generated by the tungsten vapor during the selective oxidation can be improved.

또한, 단차피복성이 나쁜 플라즈마화학기상증착법을 이용하여 PE-실리콘질화막을 형성하므로써, 게이트식각시 손실된 하드마스크의 두께를 보상하여 후속 콘택 공정의 여유도를 증대시킬 수 있는 효과가 있다.


In addition, since the PE-silicon nitride film is formed using the plasma chemical vapor deposition method having poor step coverage, the thickness of the hard mask lost during the gate etching may be compensated to increase the margin of the subsequent contact process.


Claims (7)

반도체 기판 상에 게이트산화막, 폴리실리콘막, 텅스텐막 및 하드마스크의 순서로 적층된 적층막을 형성하는 단계;Forming a laminated film stacked on the semiconductor substrate in the order of a gate oxide film, a polysilicon film, a tungsten film, and a hard mask; 상기 적층막을 포함한 상기 반도체 기판 상에 상기 적층막의 상면부에 형성되는 두께가 상기 적층막의 측면부 및 상기 반도체 기판 상에 형성되는 두께보다 두꺼운 실리콘질화막을 형성하는 단계;Forming a silicon nitride film on the semiconductor substrate including the laminated film, wherein a thickness formed on an upper surface portion of the laminated film is thicker than a side portion of the laminated film and a thickness formed on the semiconductor substrate; 상기 반도체 기판의 표면이 노출될때까지 상기 실리콘질화막을 선택적으로 제거하여 상기 적층막의 상면부 및 측면부를 덮는 스페이서를 형성하는 단계;Selectively removing the silicon nitride film until the surface of the semiconductor substrate is exposed to form a spacer covering the top and side portions of the laminated film; 상기 적층막 중에서 상기 폴리실리콘막만을 선택적으로 산화시키는 선택산화 단계; 및A selective oxidation step of selectively oxidizing only the polysilicon film among the laminated films; And 상기 스페이서를 포함한 전면에 게이트실링질화막을 형성하는 단계Forming a gate sealing nitride film on the entire surface including the spacers 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 실리콘질화막을 형성하는 단계는,Forming the silicon nitride film, 플라즈마화학기상증착법을 이용하는 것을 특징으로 하는 반도체 소자의 제조 방법.A method for manufacturing a semiconductor device, characterized by using a plasma chemical vapor deposition method. 제1항에 있어서,The method of claim 1, 상기 실리콘질화막을 형성하는 단계는,Forming the silicon nitride film, 상기 실리콘질화막의 증착 단차피복성을 10%∼60%로 하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조 방법.A method for manufacturing a semiconductor device, characterized in that the deposition step coverage of the silicon nitride film is 10% to 60%. 제1항에 있어서,The method of claim 1, 상기 실리콘질화막은, 200℃∼550℃의 저온에서 30Å∼500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The silicon nitride film is formed at a thickness of 30 kPa to 500 kPa at a low temperature of 200 ° C to 550 ° C. 제1항에 있어서,The method of claim 1, 상기 게이트실링질화막을 형성하는 단계는,Forming the gate sealing nitride film, 화학기상증착법을 이용하는 것을 특징으로 하는 반도체 소자의 제조 방법.A method for producing a semiconductor device, characterized by using a chemical vapor deposition method. 제1항에 있어서,The method of claim 1, 상기 스페이서를 형성하는 단계는,Forming the spacers, 상기 반도체 기판이 표면이 드러날때까지 상기 실리콘질화막을 에치백하는 것을 특징으로 하는 반도체 소자의 제조 방법.And etching the silicon nitride film until the surface of the semiconductor substrate is exposed. 제1항에 있어서,The method of claim 1, 상기 선택 산화 단계는,The selective oxidation step, 800℃∼1000℃의 온도범위에서 H2O:H2의 혼합가스를 이용하여 습식 증기 발생 장치가 장착된 급속열처리 방식의 챔버에서 이루어지는 것을 특징으로 하는 반도체 소자의 제조 방법.A method for manufacturing a semiconductor device, characterized in that it is carried out in a chamber of a rapid heat treatment method equipped with a wet steam generator using a mixed gas of H 2 O: H 2 in a temperature range of 800 ° C to 1000 ° C.
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