KR100873800B1 - Silicide Forming Method of Semiconductor Device Using Carbon Nanotubes - Google Patents

Silicide Forming Method of Semiconductor Device Using Carbon Nanotubes Download PDF

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KR100873800B1
KR100873800B1 KR1020020042321A KR20020042321A KR100873800B1 KR 100873800 B1 KR100873800 B1 KR 100873800B1 KR 1020020042321 A KR1020020042321 A KR 1020020042321A KR 20020042321 A KR20020042321 A KR 20020042321A KR 100873800 B1 KR100873800 B1 KR 100873800B1
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forming
metal film
gate electrode
catalyst metal
film
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KR20040008653A (en
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문봉웅
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides

Abstract

본 발명은 특히 실리콘 상에 구현되는 MOS트랜지스터의 단위소자의 살리사이드(salicide) 형성 방법에 관한 것으로, 반도체기판의 선택된 영역상에 게이트산화막을 형성하는 단계, 상기 게이트산화막상에 게이트전극을 형성하는 단계, 상기 게이트전극 양측의 상기 반도체기판내에 소스/드레인영역을 형성하는 단계, 상기 게이트전극의 상면과 상기 소스/드레인영역의 상면에 촉매금속막을 형성하는 단계, 상기 촉매금속막 상에 탄소나노튜브층을 형성하는 단계, 및 열처리 과정을 수행하여 상기 촉매금속막과 상기 게이트전극의 계면 및 상기 촉매금속막과 상기 소스/드레인영역의 계면에 실리사이드막을 형성하는 단계를 포함한다.In particular, the present invention relates to a method of forming a salicide of a unit device of a MOS transistor implemented on silicon, the method comprising forming a gate oxide film on a selected region of a semiconductor substrate, and forming a gate electrode on the gate oxide film. Forming a source / drain region in the semiconductor substrate on both sides of the gate electrode; forming a catalyst metal film on an upper surface of the gate electrode and on an upper surface of the source / drain region; carbon nanotubes on the catalyst metal film Forming a layer and forming a silicide film at an interface between the catalyst metal film and the gate electrode and at an interface between the catalyst metal film and the source / drain region by performing a heat treatment process.

Description

탄소나노튜브를 이용한 반도체 소자의 실리사이드 형성방법{Method for manufacturing silicide layer using CNT} Method for forming silicide of semiconductor device using carbon nanotubes {Method for manufacturing silicide layer using CNT}             

도 1은 종래기술에 따른 반도체소자의 제조 방법을 개략적으로 도시한 도면,1 is a view schematically showing a method for manufacturing a semiconductor device according to the prior art;

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도.
2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

28 : 촉매금속막 29 : 탄소나노튜브층28 catalyst metal film 29 carbon nanotube layer

30 : 실리사이드막
30: silicide film

본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 실리사이드를 구비한 반도체소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having silicide.

최근에 고집적, 고속화가 요구되는 반도체소자의 제조에 있어서, 기생 저항 을 감소시키기 위한 배선 물질의 저저항화 연구가 활발하다.In recent years, in the manufacture of semiconductor devices that require high integration and high speed, studies on lowering resistance of wiring materials for reducing parasitic resistance have been actively conducted.

예를 들어, 다층 배선의 경우, 금속배선을 구성하는 알루미늄(Al)의 고신뢰성 확보를 위해 알루미늄(Al)의 그레인 사이즈(Grain size)를 대형화, 고배향화하고 있는 한편, 높은 신뢰성을 확보하고 저저항화를 실현하기 위해 구리(Cu)로의 물질 변환이 검토되고 있다. 그리고, 게이트 전극(Gate electrode) 및 비트라인(Bitline)과 같은 도전층 배선의 경우에는 집적화에 따른 공정의 저온화를 위해 몰리브덴(Mo), 텅스텐(W)을 이용한 실리사이드에서 티타늄(Ti), 코발트(Co), 니켈(Ni) 등을 이용한 실리사이드로의 물질 변환이 함께 검토되고 있다.For example, in the case of multi-layered wiring, in order to secure high reliability of aluminum (Al) constituting the metal wiring, the grain size of aluminum (Al) is increased and aligned, while ensuring high reliability and low Material conversion to copper (Cu) has been studied to realize resistance. In the case of conductive layer wiring such as a gate electrode and a bitline, titanium (Ti) and cobalt in silicide using molybdenum (Mo) and tungsten (W) to lower the process due to integration. Substance conversion into silicide using (Co), nickel (Ni), and the like has been studied together.

도 1은 종래기술에 따른 반도체소자의 제조 방법을 개략적으로 도시한 도면이다.1 is a view schematically showing a method for manufacturing a semiconductor device according to the prior art.

도 1을 참조하면, 반도체기판(11)에 소자간 격리를 위한 필드산화막(12)을 형성하고, 반도체기판(11)상에 게이트산화막(13), 게이트전극(14)을 순차적으로 형성한다. 이 때, 게이트전극(14)은 폴리실리콘, 금속 또는 폴리실리콘과 금속의 적층막일 수 있는데, 바람직하게는 폴리실리콘을 이용한다.Referring to FIG. 1, a field oxide film 12 for isolation between devices is formed on a semiconductor substrate 11, and a gate oxide film 13 and a gate electrode 14 are sequentially formed on the semiconductor substrate 11. In this case, the gate electrode 14 may be a polysilicon, a metal, or a laminated film of polysilicon and a metal, preferably polysilicon.

계속해서, 게이트전극(14)을 마스크로 이용한 저농도 불순물 이온주입으로 반도체기판(11)에 LDD(Lightly Doped Drain) 영역(15)을 형성한 후, 전면에 절연막을 증착 및 전면식각하여 게이트전극(14)의 양측벽에 접하는 측벽스페이서(16)를 형성한다. Subsequently, the LDD (Lightly Doped Drain) region 15 is formed on the semiconductor substrate 11 by implanting low-concentration impurity ions using the gate electrode 14 as a mask, and then an insulating film is deposited on the entire surface and the surface is etched. A side wall spacer 16 is formed in contact with both side walls of the substrate 14).

그리고, 게이트전극(14) 및 스페이서(16)를 마스크로 이용한 고농도 불순물 이온주입으로 LDD 영역(15)에 접속되는 소스/드레인영역(17)을 형성한다. A source / drain region 17 connected to the LDD region 15 is formed by implanting highly-concentrated impurity ions using the gate electrode 14 and the spacer 16 as a mask.                         

다음으로, 전면에 전이금속막을 증착한 후, 열처리하여 게이트전극(14)의 상면 및 소스/드레인영역(17)의 상면에 실리사이드막(18)을 형성한다.Next, after depositing a transition metal film on the entire surface, the silicide film 18 is formed on the top surface of the gate electrode 14 and the top surface of the source / drain region 17.

그러나, 상기 종래의 전이금속막의 사용은 더욱 축소되는 딥 서브마이크론 (deep submicron) 영역에서는 콘택저항을 감소시키가 어렵고 또한 금속배선간의 기생 캐패시턴스를 줄이는데 그 한계점이 있었다.
However, the use of the conventional transition metal film is difficult to reduce contact resistance in the deep submicron region, which is further reduced, and has a limitation in reducing parasitic capacitance between metal wirings.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여 안출한 것으로, 딥 서브마이크론 영역에서의 콘택저항을 감소시키고, 금속배선간 기생 캐패시턴스를 줄이는데 적합한 반도체소자의 제조 방법을 제공함에 그 목적이 있다.
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device suitable for reducing contact resistance in a deep submicron region and reducing parasitic capacitance between metal lines.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 반도체기판의 선택된 영역상에 게이트산화막을 형성하는 단계, 상기 게이트산화막상에 게이트전극을 형성하는 단계, 상기 게이트전극 양측의 상기 반도체기판내에 소스/드레인영역을 형성하는 단계, 상기 게이트전극의 상면과 상기 소스/드레인영역의 상면에 촉매금속막을 형성하는 단계, 상기 촉매금속막 상에 탄소나노튜브층을 형성하는 단계, 및 열처리 과정을 수행하여 상기 촉매금속막과 상기 게이트전극의 계면 및 상기 촉매금속막과 상기 소스/드레인영역의 계면에 실리사이드막을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention for achieving the above technical problem, forming a gate oxide film on a selected region of the semiconductor substrate, forming a gate electrode on the gate oxide film, the semiconductor substrate on both sides of the gate electrode Forming a source / drain region therein, forming a catalyst metal film on the top surface of the gate electrode and the top surface of the source / drain region, forming a carbon nanotube layer on the catalyst metal film, and heat treatment And forming a silicide film at an interface between the catalyst metal film and the gate electrode and at the interface between the catalyst metal film and the source / drain region.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

후술할 탄소나노튜브(Carbon nano tube)는 2차원 구조의 SWNT(single wall nano tube) 또는 MWNT(multi wall nano tube) 물질로 나뉘어 질 수 있는데 이들의 전자전도 특성은 통상의 CNT(carbon nano tube)와 동일하다. 하지만, 길이방향, 원주방향으로 주기적으로 경계조건에 의하여 운동량이 양자화되는 특성을 가진다. 이러한 양자적인 수송효과로 인하여 탄소나노튜브는 초전도 수준의 놀라운 전도체 역할을 하게 된다. 나노튜브는 중시계에서 평균자유행로(L), 드브로이 파장에 해당하는 페르미 파장(K), 그리고 전자의 위상가간섭거리(M)에 영향을 받는데, 그 중에서도 평균자유행로(L)와 위상가간섭거리(M)가 시료의 길이보다 크면 탄성전도를 일으킨다.Carbon nanotubes (carbon nanotubes) to be described later may be divided into single-walled nanotubes (SWNTs) or multi-walled nanotubes (MWNTs) of a two-dimensional structure. Is the same as However, it has a characteristic that the momentum is quantized periodically by the boundary condition in the longitudinal direction and the circumferential direction. Due to this quantum transport effect, carbon nanotubes act as incredible conductors at the superconducting level. The nanotubes are influenced by the mean free path (L), the Fermi wavelength (K) corresponding to the DeBroW wavelength, and the phase of the electron interference distance (M), among which the mean free path (L) and phase interference If the distance M is greater than the length of the sample, elastic conduction occurs.

즉, 이러한 탄성전도 전자가 갇혀서 산란되지 않고 전도에 참여할 수 있으므로 높은 전도성을 띄게된다. 또한, CNT는 구조적 결합이거의 없는 상태로 제조가 가능한 장점이 있다. 탄소와 탄소간의 결합은 진공에서 2800℃, 대기중에 700℃ 정도로 내열성이 강하여 열전도율 또한 탁월한 성능을 보이고 있다.In other words, since the elastically conductive electrons can participate in conduction without being trapped and scattered, they exhibit high conductivity. In addition, CNTs are advantageous in that they can be manufactured with little structural bond. The carbon-to-carbon bond has a high heat resistance of about 2800 ° C. in vacuum and 700 ° C. in the air, and has excellent thermal conductivity.

본 발명은 실리사이드를 시키는 물질로 탄소나노튜브를 사용함으로 인하여 금속배선과 확산층(소스/드레인영역)간에 접촉면적을 증가시키고, 콘택저항을 감소시켜 트랜지스터의 기생저항을 감소시키고 게이트 지연의 엑섹스 시간을 빨라지게 하여 90nm 이하의 딥 서브마이크론 영역의 소자를 만드는데 적합하다. 또한, 종래 의 실리사이드 공정에서 사용하는 전이금속(또는 촉매금속이라고도 함)을 증착시킨 후 후속 열처리 공정없이 화학기상증착법(chemical vapor deposition; CVD)로 직접 탄소나노튜브를 성장시킬 수 있다. The present invention increases the contact area between the metallization and the diffusion layer (source / drain region) by using carbon nanotubes as a material for silicide, decreases the contact resistance, reduces the parasitic resistance of the transistor, and extrudes the gate delay. It is suitable for making devices in the deep submicron region below 90nm. In addition, carbon nanotubes may be grown directly by chemical vapor deposition (CVD) without depositing a transition metal (or catalytic metal) used in a conventional silicide process without subsequent heat treatment.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도이다.2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체기판(21)상에 소자간 격리를 위한 필드산화막(22)을 형성한 후, 반도체기판(21)상에 게이트산화막(23), 게이트전극(24)을 순차적으로 형성한다. 이 때, 게이트전극(24)은 폴리실리콘, 금속 또는 폴리실리콘과 금속의 적층막일 수 있는데, 바람직하게는 폴리실리콘을 이용한다.As shown in FIG. 2A, after forming the field oxide film 22 for isolation between devices on the semiconductor substrate 21, the gate oxide film 23 and the gate electrode 24 are sequentially formed on the semiconductor substrate 21. To form. In this case, the gate electrode 24 may be polysilicon, a metal, or a laminated film of polysilicon and a metal, and preferably polysilicon is used.

다음으로, 게이트전극(24)을 마스크로 이용한 저농도 불순물 이온주입으로 반도체기판(21)에 LDD 영역(25)을 형성한 후, 전면에 절연막을 증착하고 전면식각하여 게이트전극(24)의 양측벽에 접하는 측벽스페이서(26)를 형성한다. Next, after the LDD region 25 is formed on the semiconductor substrate 21 by the low concentration impurity ion implantation using the gate electrode 24 as a mask, an insulating film is deposited on the entire surface and the surface is etched to form both side walls of the gate electrode 24. A sidewall spacer 26 is formed in contact therewith.

그리고, 게이트전극(24) 및 측벽스페이서(26)를 마스크로 이용한 고농도 불순물 이온주입으로 LDD 영역(25)에 접하는 소스/드레인영역(27)을 형성한다. A source / drain region 27 in contact with the LDD region 25 is formed by implanting high concentration impurity ions using the gate electrode 24 and the sidewall spacers 26 as a mask.

계속해서, 게이트전극(24)을 포함한 반도체기판(21)의 전면에 촉매금속막(28)을 증착한 후, 선택적으로 제거하여 게이트전극(24)의 상면, 소스/드레인영역(27)의 상면에만 촉매금속막(28)을 잔류시킨다. 이때, 촉매금속막(28)은 Fe, Co 또는 Ni 중에서 선택된 전이금속막을 이용한다.Subsequently, the catalytic metal film 28 is deposited on the entire surface of the semiconductor substrate 21 including the gate electrode 24, and then selectively removed to remove the upper surface of the gate electrode 24 and the upper surface of the source / drain region 27. Only the catalytic metal film 28 is left. In this case, the catalyst metal film 28 uses a transition metal film selected from Fe, Co or Ni.

도 2b에 도시된 바와 같이, 잔류하는 촉매금속막(28)상에 선택적으로 탄소나노튜브층(29)을 형성한다. 이때, 탄소나노튜브층(29)은 화학기상증착법(CVD)을 이 용하되 750℃∼900℃의 석영반응로에서 이루어진다. 다른 방법으로는 레이저 어브리에이션(Laser abliation)법을 이용할 수 있다.As shown in FIG. 2B, a carbon nanotube layer 29 is selectively formed on the remaining catalytic metal film 28. At this time, the carbon nanotube layer 29 is made by using a chemical vapor deposition (CVD) in a quartz reaction furnace of 750 ℃ to 900 ℃. Alternatively, a laser abliation method may be used.

그리고, 탄소나노튜브층(29) 형성은 촉매금속막(28)의 종류 및 탄소나노튜브층(29)의 형성 온도에 의해 좌우된다.The formation of the carbon nanotube layer 29 depends on the type of the catalytic metal film 28 and the formation temperature of the carbon nanotube layer 29.

이와 같이, 본 발명은 반도체 소자의 활성영역 및 게이트전극상에 형성되는 종래의 전이금속 실리사이드막을 대신하여 탄소나노튜브층(29)을 사용한다. As described above, the present invention uses the carbon nanotube layer 29 instead of the conventional transition metal silicide film formed on the active region and the gate electrode of the semiconductor device.

따라서, 촉매금속막(28) 위에만 선택적으로 탄소나노튜브층(29)을 형성하면 낮은 접촉저항을 가지는 살리사이드 공정이 수행될 수 있다. 이는 도 2c에 도시되어 있다.Therefore, if the carbon nanotube layer 29 is selectively formed only on the catalytic metal film 28, the salicide process having a low contact resistance may be performed. This is shown in Figure 2c.

도 2c에 도시된 바와 같이, 탄소나노튜브층(29)을 증착한 상태에서 후속 열처리를 실시하여 촉매금속막(28)과 소스/드레인영역(27) 또는 게이트전극(24)의 실리콘간 반응에 의한 실리사이드막(30)이 추가로 형성된다. 즉, 촉매금속막(28)과 게이트전극(24)의 계면 및 촉매금속막(28)과 소스/드레인영역(27)의 계면에 실리사이드막(30)을 형성한다.As shown in FIG. 2C, a subsequent heat treatment is performed while the carbon nanotube layer 29 is deposited to react with the silicon between the catalytic metal film 28 and the source / drain region 27 or the gate electrode 24. The silicide film 30 is further formed. That is, the silicide film 30 is formed at the interface between the catalyst metal film 28 and the gate electrode 24 and at the interface between the catalyst metal film 28 and the source / drain region 27.

더욱이 탄소나노튜브층(29)이 주기율표상에서 실리콘과 같은 족이기 때문에 이온 주입을 통해 소자의 동작속도를 더 한층 증가시킬 수 있다.In addition, since the carbon nanotube layer 29 is the same group as silicon on the periodic table, the operation speed of the device may be further increased through ion implantation.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. Will be evident to those of ordinary knowledge

상기와 같이 이루어지는 본 발명은 배선이 서브미크론 영역으로 줄어들면서 나타나는 기생저항을 억제하므로써 소자의 신뢰성을 향상시키며, 딥서브미크론영역에서도 기생저항이 억제된 소자를 구현할 수 있는 효과가 있다.
The present invention made as described above improves the reliability of the device by suppressing the parasitic resistance that appears as the wiring is reduced to the sub-micron region, there is an effect that can implement a device in which the parasitic resistance is suppressed in the deep sub-micron region.

Claims (6)

반도체기판의 선택된 영역상에 게이트산화막을 형성하는 단계;Forming a gate oxide film on a selected region of the semiconductor substrate; 상기 게이트산화막상에 게이트전극을 형성하는 단계;Forming a gate electrode on the gate oxide film; 상기 게이트전극 양측의 상기 반도체기판내에 소스/드레인영역을 형성하는 단계;Forming source / drain regions in the semiconductor substrate on both sides of the gate electrode; 상기 게이트전극의 상면과 상기 소스/드레인영역의 상면에 촉매금속막을 형성하는 단계; Forming a catalyst metal film on an upper surface of the gate electrode and an upper surface of the source / drain region; 상기 촉매금속막 상에 탄소나노튜브층을 형성하는 단계; 및Forming a carbon nanotube layer on the catalyst metal film; And 열처리 과정을 수행하여 상기 촉매금속막과 상기 게이트전극의 계면 및 상기 촉매금속막과 상기 소스/드레인영역의 계면에 실리사이드막을 형성하는 단계를 포함하고, Performing a heat treatment process to form a silicide film at an interface between the catalyst metal film and the gate electrode and at an interface between the catalyst metal film and the source / drain region; 상기 탄소나노튜브층은 SWNT 또는 MWNT인 반도체 소자의 제조 방법.The carbon nanotube layer is a method of manufacturing a semiconductor device is SWNT or MWNT. 삭제delete 제1항에 있어서,The method of claim 1, 상기 촉매 금속막은 Fe, Co 또는 Ni 중에서 선택된 전이금속막인 것을 특징 으로 하는 반도체 소자 제조 방법.The catalyst metal film is a semiconductor device manufacturing method, characterized in that the transition metal film selected from Fe, Co or Ni. 제1항에 있어서,The method of claim 1, 상기 실리사이드이드막을 형성한 후,After forming the silicideide film, 상기 탄소나노튜브층에 불순물을 주입하는 단계를 더 포함하는 것을 특징으로하는 반도체 소자의 제조 방법.And injecting impurities into the carbon nanotube layer. 제1항에 있어서,The method of claim 1, 상기 촉매금속막을 형성하는 단계는,Forming the catalyst metal film, 상기 게이트전극을 포함한 상기 반도체기판상에 촉매금속막을 증착하는 단계; 및Depositing a catalytic metal film on the semiconductor substrate including the gate electrode; And 상기 촉매금속막을 선택적으로 습식식각하는 단계Selectively wet etching the catalytic metal film 를 포함함을 특징으로 하는 반도체소자의 제조 방법.Method of manufacturing a semiconductor device, characterized in that it comprises a. 제1항에 있어서,The method of claim 1, 상기 탄소나노튜브층을 형성하는 단계는,Forming the carbon nanotube layer, 화학기상증착법 또는 레이저 어브리에이션법을 통해 이루어짐을 특징으로 하 는 반도체소자의 제조 방법.A method of manufacturing a semiconductor device, characterized in that it is made through chemical vapor deposition or laser ablation.
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