KR100849821B1 - Method for fabricating semiconductor devices - Google Patents

Method for fabricating semiconductor devices Download PDF

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KR100849821B1
KR100849821B1 KR1020020008481A KR20020008481A KR100849821B1 KR 100849821 B1 KR100849821 B1 KR 100849821B1 KR 1020020008481 A KR1020020008481 A KR 1020020008481A KR 20020008481 A KR20020008481 A KR 20020008481A KR 100849821 B1 KR100849821 B1 KR 100849821B1
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oxide film
film
wiring layer
semiconductor device
present
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KR1020020008481A
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Korean (ko)
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KR20030068836A (en
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박영배
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating

Abstract

본 발명은 배선에서의 힐락(Hillock) 오류를 방지하기 위한 반도체 장치의 제조 방법에 관한 것이다. 본 발명은 기판 또는 하부 막질 위에 배선층을 형성한 후 패터닝을 실시하고, 패터닝된 상기 배선층 위에 전면적으로 제 1 산화막을 형성한다. 그리고, 상기 제 1 산화막을 전면 식각하여 식각된 막질이 상기 배선층의 측벽을 커버하도록 한 후에 전면적으로 저유전율의 제 2 산화막을 증착하는 공정을 갖게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for preventing a hilelock error in wiring. According to the present invention, after forming a wiring layer on a substrate or a lower film, patterning is performed, and a first oxide film is formed on the entire surface of the patterned wiring layer. Then, the first oxide film is etched entirely so that the etched film covers the sidewall of the wiring layer, and then the second oxide film having the low dielectric constant is deposited on the entire surface.

따라서, 본 발명에 의하면, 고온 또는 고전류의 구동조건에서도 도전막 패턴간의 전류 누설이 발생되지 않아서 설계된 반도체 장치의 특성을 얻을 수 있는 효과가 있다.Therefore, according to the present invention, the current leakage between the conductive film patterns does not occur even under the driving conditions of high temperature or high current, so that the characteristics of the designed semiconductor device can be obtained.

힐락, 배선, 산화막, 화학기상증착, 전면식각, 반도체Hillock, Wiring, Oxide, Chemical Vapor Deposition, Full Etch, Semiconductor

Description

반도체 장치의 제조 방법{Method for fabricating semiconductor devices}Method for fabricating a semiconductor device

도 1a 내지 도 1c는 종래의 반도체 장치의 제조 방법을 설명하기 위한 공정 단면도이다.1A to 1C are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.

도 2a 내지 도 2d는 본 발명에 따른 반도체 장치의 제조 방법을 순차적으로 나타내는 공정 단면도이다.2A to 2D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10, 20 : 반도체 기판 12, 22 : 금속하부막10, 20: semiconductor substrate 12, 22: metal underlayer

14, 24 : 금속배선층 16, 26 : 금속상부막14, 24: metal wiring layer 16, 26: metal upper layer

18, 28, 30, 32, 34 : 산화막18, 28, 30, 32, 34: oxide film

본 발명은 반도체 장치의 제조 방법에 관한 것으로, 보다 상세하게는, 높은 전류가 흐르는 배선의 측벽의 힐락 오류에 의해 누설전류가 발생되는 것을 방지하도록 하는 반도체 장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to prevent leakage current from being generated by a hill lock error of a side wall of a wiring through which a high current flows.

고집적 반도체 장치를 제조하는 기술이 발달함에 따라 배선 사이를 채우는 산화막으로 저유전율(Low-K)막을 채용하고 있는데, 그 미세구조가 포러스(Porous) 하기 때문에 강도가 매우 약하다. 따라서, 고온에서 높은 전류가 흐르는 경우 배선층에 보이드(Void)와 함께 배선물질의 측면을 통해 산화막을 뚫고 나가는 힐락(Hillock) 오류가 발생되는 문제가 있다.As a technology for manufacturing a highly integrated semiconductor device is developed, a low dielectric constant (Low-K) film is used as an oxide film filling between wirings, and its strength is very weak because its microstructure is porous. Therefore, when a high current flows at a high temperature, there is a problem in that a Hilar error (Hillock) that penetrates the oxide film through the side of the wiring material together with the voids occurs in the wiring layer.

이러한 예로서 도 1a 내지 도 1c에 도시된 종래의 반도체 장치의 제조 방법의 예를 들 수 있다.As such an example, the example of the manufacturing method of the conventional semiconductor device shown to FIG. 1A-FIG. 1C is mentioned.

도 1a를 참조하면, 반도체 기판(10) 상에 그의 하부에는 티타늄(Ti) 또는 티타늄 나이트라이드(TiN) 등의 하부막(12)이 형성되고, 상부에는 티타늄 나이트라이드 등의 상부막(16)이 형성된 금속배선층(14) 패턴을 형성한다. 여기서, 금속배선층(14) 패턴은 알루미늄(Al) 또는 구리(Cu) 재질의 패턴일 수 있다. 또한, 상부막(16)은 이후 형성되는 패턴과 금속배선층(14) 패턴과의 단락(Short)을 방지한다. 그런 다음, 하부막(12), 금속배선층(14) 패턴 및 상부막(16)을 패터닝(Patterning) 하여 기판(10)의 표면이 노출되도록 식각하여 홀(Hole)을 형성한다.Referring to FIG. 1A, a lower layer 12 such as titanium (Ti) or titanium nitride (TiN) is formed on a semiconductor substrate 10, and an upper layer 16 such as titanium nitride is formed on an upper portion thereof. The formed metal wiring layer 14 pattern is formed. Here, the metal wiring layer 14 pattern may be a pattern made of aluminum (Al) or copper (Cu). In addition, the upper layer 16 prevents a short between the pattern formed thereafter and the pattern of the metallization layer 14. Thereafter, the lower layer 12, the metallization layer 14 pattern, and the upper layer 16 are patterned to form holes by etching to expose the surface of the substrate 10.

그리고, 도 1b 및 도 1c를 참조하면, 그 위에 절연막(18)을 증착하여 각 금속배선층(14) 패턴간의 절연이 이루어지도록 하며, 그 후 평탄화 공정을 수행하여 절연막(18)을 평탄화한 후에 후속공정을 실시하게 된다.1B and 1C, an insulating film 18 is deposited thereon to insulate each metal wiring layer 14 pattern, and then a planarization process is performed to planarize the insulating film 18. The process will be carried out.

그런데, 이와 같이 형성된 배선들에 고온에서 높은 전류가 흐를 때 각 배선의 측면(A 및 B)을 통해 산화막을 뚫고 나가는 힐락이 발생하였다.However, when a high current flows at high temperatures in the wirings formed as described above, hillocks that penetrate the oxide film through the side surfaces A and B of the respective wirings are generated.

이와 같은 문제점을 해결하기 위한 본 발명의 목적은, 어떤 구동조건에서도 도전막 패턴간의 전류 누설이 발생되지 않도록 하기 위한 반도체 장치의 제조 방법을 제공하는 것이다.An object of the present invention for solving such a problem is to provide a method for manufacturing a semiconductor device for preventing current leakage between conductive film patterns under any driving conditions.

본 발명의 다른 목적은, 도전막 패턴의 측벽에 강도가 높은 절연막을 형성함으로써 힐락 발생을 억제하도록 하는 반도체 장치의 제조 방법을 제공하는 것이다.Another object of the present invention is to provide a method of manufacturing a semiconductor device, which suppresses the occurrence of hillock by forming an insulating film having a high strength on the sidewall of the conductive film pattern.

상기 목적을 달성하기 위한 본 발명에 의한 반도체 장치의 제조 방법은, 기판 또는 하부 막질 위에 배선층을 형성한 후 패터닝을 실시하는 단계와, 패터닝된 상기 배선층 위에 제 1 산화막을 전면적으로 형성하는 단계와, 상기 제 1 산화막을 전면 식각하여 식각된 막질이 상기 배선층의 측벽을 커버하도록 하는 단계, 그리고, 전면적으로 저유전율의 제 2 산화막을 증착하는 단계를 포함하는 것을 특징으로 한다.A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of performing a patterning after forming a wiring layer on the substrate or the lower film quality, forming a first oxide film on the patterned wiring layer entirely; Etching the entire surface of the first oxide film to cover the sidewalls of the interconnection layer; and depositing a second dielectric film having a low dielectric constant on the entire surface.

상기 제 1 산화막은, 스핀 코팅 또는 화학기상증착 중 어느 하나의 방법에 의해 형성되며, 상기 제 2 산화막보다 강도가 더 크게 형성되는 것이 바람직하다.The first oxide film is formed by any one of spin coating or chemical vapor deposition, and is preferably formed to have a higher strength than the second oxide film.

이하, 본 발명의 실시예에 대한 설명은 첨부된 도면을 참조하여 더욱 상세하게 설명한다. 아래에 기재된 본 발명의 실시예는 본 발명의 기술적 사상을 예시적으로 설명하기 위한 것에 불과한 것으로, 본 발명의 권리범위가 여기에 한정되는 것으로 이해되어서는 안될 것이다. 아래의 실시예로부터 다양한 변형, 변경 및 수정이 가능함은 이 분야의 통상의 지식을 가진 자에게 있어서 명백한 것이다.Hereinafter, an embodiment of the present invention will be described in more detail with reference to the accompanying drawings. The embodiments of the present invention described below are merely for illustrating the technical idea of the present invention by way of example, it should not be understood that the scope of the present invention is limited thereto. Various modifications, changes and variations are possible in the following examples which will be apparent to those of ordinary skill in the art.

도 2a를 참조하면, 종래와 같이 반도체 기판(20) 상에 하부막(22)이 형성되고, 그 위에는 금속배선층(24)을 형성한 후 상부에는 상부막(26)을 형성한다. 그런 다음, 하부막(22), 금속배선층(24) 및 상부막(26)을 패터닝 하여 기판(20)의 표면이 노출되도록 식각에 의해 홀이 형성되어 있는 것을 볼 수 있다.Referring to FIG. 2A, a lower layer 22 is formed on a semiconductor substrate 20 as in the related art, a metal wiring layer 24 is formed thereon, and an upper layer 26 is formed thereon. Thereafter, the lower layer 22, the metallization layer 24, and the upper layer 26 may be patterned to show that holes are formed by etching to expose the surface of the substrate 20.

그 후 도 2b를 참조하면, 홀이 형성되어 있는 기판에 전면적으로 절연막(28)이 증착된다. 상기 절연막(28)은 화학기상증착에 의해 형성되며, 그 재질은 산화막이 될 수 있다. 또한 상기 산화막은 화학기상증착에 의한 방법 외에 스핀 코팅(Spin Coating)에 의해서도 형성될 수 있다.Thereafter, referring to FIG. 2B, an insulating film 28 is deposited on the entire surface of the substrate on which the holes are formed. The insulating film 28 is formed by chemical vapor deposition, and the material may be an oxide film. In addition, the oxide film may be formed by spin coating in addition to the method by chemical vapor deposition.

이와 같이 형성된 절연막(28)은 전면 식각(Blanket Etch or Etch Back)에 의해 전체적으로 식각되는데, 상기 금속배선층(24)이 형성된 패턴의 측면에는 일정 두께의 절연막이 형성될 정도로 식각을 진행한다. 즉, 도 2c와 같은 패턴이 형성되도록 식각공정을 진행하는 것이다.The insulating layer 28 formed as described above is etched by the entire etching (Blanket Etch or Etch Back), and the etching is performed to form an insulating layer having a predetermined thickness on the side surface of the pattern on which the metal wiring layer 24 is formed. That is, the etching process is performed to form a pattern as shown in FIG.

그리고, 그 위에 또 다른 절연막(32)을 증착하게 되는데, 도 2d를 참조하면, 절연막(30)이 형성된 부분을 포함하는 전면에 걸쳐서 절연막(32)이 증착된다. 상기 절연막(32)은 유전율이 3.5 이하인 저유전율의 산화막이 될 수 있다.Then, another insulating film 32 is deposited thereon. Referring to FIG. 2D, the insulating film 32 is deposited over the entire surface including the portion where the insulating film 30 is formed. The insulating layer 32 may be an oxide film having a low dielectric constant of 3.5 or less.

여기서, 절연막(30)과 절연막(32)은 강도면에서 차이가 있는데, 저유전율의 절연막(32)에 비해 절연막(30)이 더 큰 강도를 갖게 형성된다. 이로써 유전율 손실을 최소로 하면서 저유전율의 막질을 사용하면서도 배선 신뢰성을 확보할 수 있게 되는 것이다.Here, the insulating film 30 and the insulating film 32 have a difference in strength, and the insulating film 30 is formed to have a greater strength than the insulating film 32 having a low dielectric constant. As a result, it is possible to secure wiring reliability while using a film having a low dielectric constant while minimizing dielectric loss.

마지막으로, 상기 절연막(32) 위에 또 다른 절연막(34)을 증착하여 필요에 따라 패터닝하여 후속공정에 연계하여 사용되도록 한다.Finally, another insulating film 34 is deposited on the insulating film 32 to be patterned as necessary to be used in connection with subsequent processes.

이상과 같이 본 발명에 의한 실시예에 의하면, 도전층의 측면에 강도가 큰 산화막을 형성함으로써 이후 공급되는 전류의 누설이 발생되지 않게 되는 이점이 있다.According to the embodiment according to the present invention as described above, there is an advantage that the leakage of the current to be supplied subsequently does not occur by forming a high-strength oxide film on the side of the conductive layer.

따라서, 본 발명에 의하면, 고온 또는 고전류의 구동조건에서도 도전막 패턴간의 전류 누설이 발생되지 않아서 설계된 반도체 장치의 특성을 얻을 수 있는 효과가 있다.Therefore, according to the present invention, the current leakage between the conductive film patterns does not occur even under the driving conditions of high temperature or high current, so that the characteristics of the designed semiconductor device can be obtained.

그리고, 도전막 패턴의 측벽에 강도가 높은 절연막을 형성함으로써 유전율이 높은 절연막으로의 힐락 발생이 예방되는 효과가 있다.In addition, by forming an insulating film having a high strength on the sidewall of the conductive film pattern, there is an effect of preventing the occurrence of hillock to the insulating film having a high dielectric constant.

Claims (3)

기판 또는 하부 막질 위에 배선층을 형성한 후 패터닝을 실시하는 단계;Forming a wiring layer on the substrate or the lower film and then patterning the wiring layer; 패터닝된 상기 배선층 위에 제 1 산화막을 전면적으로 형성하는 단계;Forming an entire first oxide film over the patterned wiring layer; 상기 제 1 산화막을 전면 식각하여 식각된 막질이 상기 배선층의 측벽을 커버하도록 하는 단계; 및Etching the entire first oxide film so that the etched film covers the sidewall of the wiring layer; And 전면적으로 저유전율의 제 2 산화막을 증착하는 단계를 포함하고,Depositing a second dielectric film of low dielectric constant over the entire surface, 상기 제 1 산화막은 상기 제 2 산화막보다 강도가 더 크게 형성되는 것을 특징으로 하는 반도체 장치의 제조 방법.And the first oxide film is formed to have a greater strength than the second oxide film. 제 1 항에 있어서,The method of claim 1, 상기 제 1 산화막은,The first oxide film, 스핀 코팅 또는 화학기상증착 중 어느 하나에 의해 형성되는 것을 특징으로 하는 반도체 장치의 제조 방법.A method of manufacturing a semiconductor device, characterized in that formed by either spin coating or chemical vapor deposition. 삭제delete
KR1020020008481A 2002-02-18 2002-02-18 Method for fabricating semiconductor devices KR100849821B1 (en)

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KR19980043234A (en) * 1996-12-02 1998-09-05 양승택 How to increase the life of metal wiring in semiconductor manufacturing process
KR19990062445A (en) * 1997-12-10 1999-07-26 다니구찌 이찌로오, 기타오카 다카시 Semiconductor device and manufacturing method thereof
KR20000042668A (en) * 1998-12-26 2000-07-15 김영환 Method for forming metal wirings of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980043234A (en) * 1996-12-02 1998-09-05 양승택 How to increase the life of metal wiring in semiconductor manufacturing process
KR19990062445A (en) * 1997-12-10 1999-07-26 다니구찌 이찌로오, 기타오카 다카시 Semiconductor device and manufacturing method thereof
KR20000042668A (en) * 1998-12-26 2000-07-15 김영환 Method for forming metal wirings of semiconductor device

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