KR100826787B1 - Fabrication method of semiconductor device - Google Patents

Fabrication method of semiconductor device Download PDF

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KR100826787B1
KR100826787B1 KR1020020019941A KR20020019941A KR100826787B1 KR 100826787 B1 KR100826787 B1 KR 100826787B1 KR 1020020019941 A KR1020020019941 A KR 1020020019941A KR 20020019941 A KR20020019941 A KR 20020019941A KR 100826787 B1 KR100826787 B1 KR 100826787B1
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oxide film
impurity
gas
hydrogen
semiconductor device
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KR20030081618A (en
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조경수
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

반도체 소자 제조 방법에 관한 것으로, 그 목적은 불순물 함유 산화막에서 불순물의 이동으로 인한 디라미네이션, 금속 박막의 부식, 및 금속물질의 접착력 저하 등을 방지하는 데 있다. 이를 위해 본 발명에서는, 하부 금속 배선을 포함한 반도체 구조물 상부에 불순물 함유 산화막을 형성하는 단계; 불순물 함유 산화막 상에 상부 산화막을 증착하고 평탄화하는 단계; 상부 산화막과 불순물 함유 산화막을 선택적으로 식각하여 하부 금속 배선의 일부가 드러나도록 비아를 형성하는 단계; 비아를 포함한 구조물 상부 전면에 수소를 포함하는 가스 한 종류 이상을 흘려주어, 비아와 인접한 불순물 함유 산화막의 소정 영역에 불순물 함량이 상대적으로 낮은 불순물 비함유 영역을 형성하는 단계; 비아를 금속물질로 매립하는 단계를 순차적으로 수행하여 불순물로 인한 금속 배선의 디라미네이션, 금속 박막의 부식, 비아 저항의 증가를 방지한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and an object thereof is to prevent delamination due to the movement of impurities in an oxide film containing impurities, corrosion of a metal thin film, and deterioration of adhesion of metal materials. To this end, in the present invention, forming an impurity-containing oxide film on the semiconductor structure including the lower metal wiring; Depositing and planarizing an upper oxide film on the impurity containing oxide film; Selectively etching the upper oxide film and the impurity-containing oxide film to form vias to expose a portion of the lower metal wiring; Flowing at least one kind of hydrogen-containing gas over the entire surface of the structure including the via to form an impurity-free region having a relatively low impurity content in a predetermined region of the impurity-containing oxide film adjacent to the via; The step of filling the via with metal is sequentially performed to prevent the delamination of the metal wiring, the corrosion of the metal thin film, and the increase of the via resistance due to impurities.

불순물, 디라미네이션, 비아 Impurities, Delamination, Vias

Description

반도체 소자 제조 방법 {Fabrication method of semiconductor device}Fabrication method of semiconductor device

도 1a 내지 1d는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 금속 배선층 상부에 불순물 함유 산화막을 사용하여 절연체층을 형성하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming an insulator layer using an impurity-containing oxide film on a metal wiring layer.

반도체 소자가 점차 고집적화, 다층화됨에 따라 중요한 기술의 하나로 다층 배선 기술이 등장하게 되었는데, 이와 같은 다층 배선 기술은 금속 배선층과 절연막층을 회로 소자가 형성된 반도체 기판 상부에 교대로 형성하며, 절연막에 의해 분리된 금속 배선층 사이를 비아를 통해 전기적으로 접속함으로써 회로 동작이 이루어지도록 하는 것이다.As semiconductor devices have been increasingly integrated and multilayered, multilayer wiring has emerged as one of the important technologies. The multilayer wiring technology alternately forms a metal wiring layer and an insulating film layer on the semiconductor substrate on which the circuit elements are formed, and is separated by an insulating film. The circuit operation is performed by electrically connecting the interconnected metal wiring layers through vias.

최근 금속 배선층 상에 형성하는 절연체층으로서, 불소 또는 탄소와 같은 불순물을 함유하는 산화막을 선호하고 있으며, 이는 불순물 함유 산화막이 낮은 유전상수를 나타내기 때문이다. Recently, as an insulator layer formed on the metal wiring layer, an oxide film containing an impurity such as fluorine or carbon is preferred because an oxide film containing an impurity exhibits a low dielectric constant.                         

그러나, 불순물 함유 산화막에서는 불소 또는 탄소와 같은 불순물이 상부로 이동하여 금속 배선과 산화막 사이의 계면에 축적됨으로써 열공정 진행시 금속배선을 들뜨게 하는 현상인 디라미네이션(delamination)을 유발하는 문제점이 있으며, 불순물이 금속 박막 내로 침투할 경우 금속 박막의 부식을 유발하는 문제점이 있었다.However, in the impurity-containing oxide film, impurities such as fluorine or carbon move upwards and accumulate at the interface between the metal wiring and the oxide film, thereby causing delamination, which is a phenomenon of lifting the metal wiring during the thermal process. When impurities penetrate into the metal thin film, there was a problem of causing corrosion of the metal thin film.

특히, 비아 등을 금속물질로 충진하면 불순물 함유 산화막과 금속이 상호 접촉하게 되는데, 이 때 불순물이, 금속물질이 비아 측면으로 접착하는 것을 방해하고 이로 인해 비아 저항이 증가하는 문제점이 있었다. In particular, when the via is filled with a metal material, the impurity-containing oxide film and the metal come into contact with each other. At this time, the impurity prevents the metal material from adhering to the via side, thereby increasing the via resistance.

본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 불순물 함유 산화막에서 불순물의 이동으로 인한 디라미네이션, 금속 박막의 부식, 및 금속물질의 접착력 저하 등을 방지하는 데 있다.The present invention is to solve the problems as described above, the object is to prevent the delamination due to the movement of impurities in the impurity-containing oxide film, corrosion of the metal thin film, deterioration of adhesion of the metal material.

상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는, 하부 금속 배선을 포함한 반도체 구조물 상부에 불순물 함유 산화막을 형성하는 단계; 불순물 함유 산화막 상에 상부 산화막을 증착하고 평탄화하는 단계; 상부 산화막과 불순물 함유 산화막을 선택적으로 식각하여 하부 금속 배선의 일부가 드러나도록 비아를 형성하는 단계; 비아를 포함한 구조물 상부 전면에 수소를 포함하는 가스 한 종류 이상을 흘려주어, 비아와 인접한 불순물 함유 산화막의 소정 영역에 불순물 함량이 상대적으로 낮은 불순물 비함유 영역을 형성하는 단계; 비아를 금속물질로 매립하 는 단계를 포함하여 반도체 소자를 제조한다.In order to achieve the above object, in the present invention, forming an impurity-containing oxide film on the semiconductor structure including the lower metal wiring; Depositing and planarizing an upper oxide film on the impurity containing oxide film; Selectively etching the upper oxide film and the impurity-containing oxide film to form vias to expose a portion of the lower metal wiring; Flowing at least one kind of hydrogen-containing gas over the entire surface of the structure including the via to form an impurity-free region having a relatively low impurity content in a predetermined region of the impurity-containing oxide film adjacent to the via; A semiconductor device is manufactured by filling a via with a metal material.

이하, 본 발명에 따른 반도체 소자 제조 방법에 대해 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail.

도 1a 내지 1d는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

먼저, 도 1a에 도시된 바와 같이, 반도체 기판(1)의 구조물, 즉 개별 소자가 형성된 반도체 기판 또는 금속 배선층 상부에 산화막 등으로 이루어진 하부절연막(2)을 형성하고, 하부절연막(2) 상에 금속배선막을 형성하고 패터닝하여 하부 금속 배선(3)을 형성한다. First, as shown in FIG. 1A, a lower insulating film 2 made of an oxide film or the like is formed on a structure of the semiconductor substrate 1, that is, a semiconductor substrate or a metal wiring layer on which individual elements are formed, and then formed on the lower insulating film 2. The metal wiring film is formed and patterned to form the lower metal wiring 3.

이어서, 하부 금속 배선(3)을 포함한 상부 전면에 하부 산화막(4)을 얇게 증착하고, 하부 산화막(4) 상에 불순물 함유 산화막(5)을 3000Å 내지 6000Å의 두께로 증착한 후, 불순물 함유 산화막(5) 상에 불순물을 함유하지 않은 일반 산화막(6)을 1000Å 이상의 두께로 증착하고 화학기계적 연마하여 상면을 평탄화한다. 평탄화된 일반 산화막(6) 상에는 감광막을 도포하고 노광 및 현상하여 비아로 예정된 영역의 상부에 해당하는 일부분이 제거된 감광막 패턴(7)을 형성한다.Subsequently, the lower oxide film 4 is thinly deposited on the entire upper surface including the lower metal wiring 3, and the impurity-containing oxide film 5 is deposited on the lower oxide film 4 to a thickness of 3000 kV to 6000 kV. A general oxide film 6 containing no impurity on (5) is deposited to a thickness of 1000 kPa or more and subjected to chemical mechanical polishing to planarize the top surface. On the flattened common oxide film 6, a photosensitive film is applied, exposed and developed to form a photosensitive film pattern 7 from which a portion corresponding to the upper portion of the region intended as a via is removed.

이 때, 불순물 함유 산화막(5)으로는 불소를 함유하는 산화막, 일예로 SiOxFy, 또는 탄소를 함유하는 산화막, 일예로 SiOxCy, 또는 불소와 탄소를 동시에 함유하는 산화막, 또는 불소, 탄소 및 질소를 동시에 함유하는 산화막 등을 형성할 수 있으며, 이러한 불순물 함유 산화막에서 불소가 함유된 산화막의 경우 불소 함량이 2 중량% 내지 4 중량%인 것이 바람직하고, 탄소가 함유된 산화막의 경우 탄소 함량이 10 중량% 내지 30 중량%인 것이 바람직하다. At this time, as the impurity-containing oxide film 5, an oxide film containing fluorine, for example, SiO x F y , or an oxide film containing carbon, for example, SiO x C y , or an oxide film containing fluorine and carbon simultaneously, or fluorine , An oxide film containing carbon and nitrogen at the same time, and the fluorine-containing oxide film in the impurity-containing oxide film preferably has a fluorine content of 2% by weight to 4% by weight, and an oxide film containing carbon. It is preferred that the carbon content is 10% to 30% by weight.

다음, 도 1b에 도시된 바와 같이, 감광막 패턴(7)을 마스크로 하여 노출된 일반 산화막(6)과, 그 하부의 불순물 함유 산화막(5) 및 하부 산화막(4)을 식각함으로써 하부 금속 배선(3)을 노출시키는 비아(100)를 형성한다.Next, as shown in FIG. 1B, the lower metal wiring (5) is etched by etching the general oxide film 6 exposed using the photosensitive film pattern 7 as a mask, the impurity-containing oxide film 5 and the lower oxide film 4 below. A via 100 is formed to expose 3).

다음, 상부 전면에 H2 가스 단독으로 또는 SiH4와 같이 H2를 포함하는 가스 한 종류 이상을 흘려주면 불순물 함유 산화막(5) 내에 함유된 불순물(X)이 SiH4 또는 H2 가스 등의 반응가스와 상호 반응하여 SiX, HX 등의 형태로 비아(100)를 통해 외부로 빠져나가고, 결과적으로 비아(100)와 인접한 불순물 함유 산화막(5)의 소정 영역은 불순물 함량이 상대적으로 낮은 불순물 비함유 영역(8)이 된다.Next, when H 2 gas alone or one or more kinds of gas containing H 2 , such as SiH 4 , is flowed to the upper surface, impurities X contained in the impurity-containing oxide film 5 react with SiH 4 or H 2 gas. Reacts with the gas and exits through the via 100 in the form of SiX, HX, etc. As a result, a predetermined region of the impurity-containing oxide film 5 adjacent to the via 100 is relatively free of impurities. Area 8.

SiH4 또는 H2 가스 등의 반응가스를 흘려줄 때에는 기판의 온도를 50℃ 내지 250℃로 일정하게 유지해야 하며, 이는 온도가 너무 낮을 경우에는 반응이 활발히 이루어지지 않으므로 충분한 양의 불순물이 반응하지 못하게 되며, 이와 반대로 온도가 너무 높을 경우에는 불순물의 확산이 활발해져 불순물 비함유 영역(8)에까지 불소가 계속적으로 확산되고 결과적으로 불소 함량이 감소하지 못하여 불순물 비함유 영역이 형성되지 못하기 때문이다.When flowing a reaction gas such as SiH 4 or H 2 gas, the temperature of the substrate should be kept constant at 50 ° C to 250 ° C. If the temperature is too low, a sufficient amount of impurities do not react since the reaction is not actively performed. On the contrary, if the temperature is too high, diffusion of impurities becomes active, and fluorine continuously diffuses to the impurity-free region 8, and consequently, the fluorine content cannot be reduced, thereby forming an impurity-free region.

또한, 비아 형성 후 비아 바닥에서 일정 두께로 성장할 가능성이 높은 자연 산화막을 제거하기 위해 He 또는 Ar과 같은 불활성 기체를 이용한 플라즈마 처리를 수행한 후에, 상기한 반응가스를 흘려줄 수도 있다. In addition, after the via formation, the reaction gas may be flowed after the plasma treatment using an inert gas such as He or Ar to remove the natural oxide film that is likely to grow to a certain thickness at the bottom of the via.                     

또 다른 방법으로서, SiH4 또는 H2 가스 등의 반응가스를 흘려준 후 전력을 인가하여 반응가스로 플라즈마를 형성하고 이러한 플라즈마 상태에서 불순물이 반응하도록 하여 불순물 비함유 영역을 형성할 수도 있다. As another method, after flowing a reaction gas such as SiH 4 or H 2 gas, power may be applied to form a plasma with the reaction gas, and impurities may be reacted in such a plasma state to form an impurity-free region.

다음, 비아(100) 내벽에 베리어 금속막(9)을 200Å 내지 500Å의 두께로 형성하고 베리어 금속막(9) 상에 텅스텐(10)을 형성하여 비아(100) 내부를 충진한 후, 일반 산화막(6) 상에 형성된 베리어 금속막(9) 및 텅스텐(10)을 화학기계적 연마하여 제거하고, 평탄화된 상면에 베리어 금속막(11, 12) 및 금속물질(13)을 증착하고 부분적으로 식각하여 비아(100)를 통해 하부 금속 배선(3)과 연결되는 상부 금속 배선(13)을 형성한다.Next, a barrier metal film 9 is formed on the inner wall of the via 100 to a thickness of 200 to 500 mm, and tungsten 10 is formed on the barrier metal film 9 to fill the via 100, and then a general oxide film. The barrier metal film 9 and tungsten 10 formed on the substrate 6 are removed by chemical mechanical polishing, and the barrier metal films 11 and 12 and the metal material 13 are deposited and partially etched on the planarized top surface. An upper metal interconnection 13 connected to the lower metal interconnection 3 is formed through the via 100.

이 때, 베리어 금속막(9)으로는 CoN, TaN, TiN, WN, CoCN, TaCN, TiCN, WCN 등의 금속을 증착할 수 있으며, 증착시 기판의 온도를 SiH4 또는 H2 가스 등의 반응가스를 흘려줄 때의 온도와 같거나 낮게 해야 한다. At this time, the barrier metal film 9 may be deposited with a metal such as CoN, TaN, TiN, WN, CoCN, TaCN, TiCN, WCN, and the like during the deposition reaction temperature of the substrate, such as SiH 4 or H 2 gas It should be equal to or lower than the temperature at which the gas flows.

텅스텐 대신에 불순물을 함유하는 알루미늄 또는 99.9% 이상 순도의 구리를 사용하여 비아를 매립할 수도 있다.Instead of tungsten, vias may be embedded using aluminum containing impurities or copper of at least 99.9% purity.

상술한 바와 같이, 본 발명에서는 비아 형성 후 SiH4 또는 H2 가스 등의 반응가스를 훌려주어 비아와 인접한 불순물 함유 산화막의 소정 영역에 불순물 함량이 상대적으로 낮은 불순물 비함유 영역을 형성하기 때문에, 불순물로 인한 금속 배선의 들뜸현상인 디라미네이션을 방지하고 금속 박막의 부식을 방지하는 효과가 있 다.As described above, in the present invention, since the reaction gas, such as SiH 4 or H 2 gas, is formed after via formation, an impurity-free region having a relatively low impurity content is formed in a predetermined region of the oxide-containing oxide film adjacent to the via. This prevents delamination, which is a phenomenon of lifting the metal wiring, and prevents corrosion of the metal thin film.

따라서, 디라미네이션에 기인한 소자의 불량발생률 감소를 방지하여 수율을 향상시키는 효과가 있다.Therefore, there is an effect of improving the yield by preventing the reduction of the defective rate of the device due to the delamination.

또한, 불순물 비함유 영역의 형성으로 인해, 종래 비아를 매립하는 금속물질이 비아 측면으로 접착하는 것을 방해하여 비아 저항을 증가시키던 불순물의 함량을 대폭 낮추기 때문에 안정된 비아 저항을 유지하는 효과가 있다. In addition, due to the formation of the impurity-free region, the metal material filling the via is prevented from adhering to the side of the via, thereby significantly reducing the content of impurities which increased the via resistance, thereby maintaining a stable via resistance.

Claims (7)

하부 금속 배선을 포함한 반도체 구조물 상부에 하부 산화막 및 불순물 함유 산화막을 형성하는 단계;Forming a lower oxide layer and an impurity-containing oxide layer on the semiconductor structure including the lower metal interconnection; 상기 불순물 함유 산화막 상에 상부 산화막을 증착하고 평탄화하는 단계;Depositing and planarizing an upper oxide film on the impurity-containing oxide film; 상기 상부 산화막, 불순물 함유 산화막 및 하부 산화막을 선택적으로 식각하여 상기 하부 금속 배선의 일부가 드러나도록 비아를 형성하는 단계;Selectively etching the upper oxide layer, the impurity-containing oxide layer, and the lower oxide layer to form a via to expose a portion of the lower metal interconnection; 상기 비아를 포함하는 상기 반도체 구조물에 불활성 기체를 이용한 플라즈마 공정을 진행하는 단계;Performing a plasma process using an inert gas on the semiconductor structure including the vias; 상기 비아를 포함한 구조물 상부 전면에 수소를 포함하는 가스 한 종류 이상을 흘려주어, 상기 비아와 인접한 불순물 함유 산화막에 불순물 함량이 상대적으로 낮은 불순물 비함유 영역을 형성하는 단계; 및Flowing at least one kind of hydrogen-containing gas over an entire surface of the structure including the via to form an impurity-free region having a relatively low impurity content in an oxide film containing an impurity adjacent to the via; And 상기 비아를 금속물질로 매립하는 단계를 포함하는 반도체 소자 제조 방법.And filling the via with a metal material. 제 1 항에 있어서, 상기 수소를 포함하는 가스 한 종류 이상으로는, 수소기체 단독, SiH4 가스 단독, 수소 기체와 SiH4 가스의 혼합 중의 어느 하나인 반도체 소자 제조 방법. The method of manufacturing a semiconductor device according to claim 1, wherein at least one kind of gas containing hydrogen is any one of hydrogen gas alone, SiH 4 gas alone, and a mixture of hydrogen gas and SiH 4 gas. 제 1 항에 있어서, 상기 수소를 포함하는 가스 한 종류 이상을 흘려줄 때에는 기판의 온도를 50℃ 내지 250℃로 유지하여 흘려주는 반도체 소자 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein when flowing at least one gas containing hydrogen, the temperature of the substrate is maintained at 50 ° C to 250 ° C. 제 1 항에 있어서, 상기 수소를 포함하는 가스 한 종류 이상을 흘려준 후에는 전력을 인가하여 상기 수소를 포함하는 가스 한 종류 이상으로 플라즈마를 형성하는 반도체 소자 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein after the flow of at least one kind of gas containing hydrogen, plasma is applied to at least one kind of gas containing hydrogen by applying electric power. 제 1 항에 있어서, 상기 불순물 함유 산화막은 불소가 함유된 산화막, 탄소가 함유된 산화막, 불소와 탄소가 동시에 함유된 산화막, 및 불소, 탄소, 질소가 동시에 함유된 산화막 중에서 선택된 어느 한 물질로 형성하는 반도체 소자 제조 방법.The method of claim 1, wherein the impurity-containing oxide film is formed of any one selected from an oxide film containing fluorine, an oxide film containing carbon, an oxide film containing fluorine and carbon at the same time, and an oxide film containing fluorine, carbon and nitrogen at the same time. A semiconductor device manufacturing method. 제 3 항에 있어서, 상기 비아를 금속물질로 매립하기 전에 상기 비아 내벽에 베리어 금속막을 증착하는 단계를 더 포함하는 반도체 소자 제조 방법. The method of claim 3, further comprising depositing a barrier metal film on an inner wall of the via before filling the via with a metal material. 제 6 항에 있어서, 상기 베리어 금속막을 증착할 때에는 기판의 온도를 상기 수소를 포함하는 가스 한 종류 이상을 흘려줄 때의 온도와 같거나 낮게 하는 반도체 소자 제조 방법.The method of claim 6, wherein the deposition of the barrier metal film is performed at a temperature equal to or lower than the temperature at which one or more kinds of the gas containing hydrogen flows.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990023749A (en) * 1997-08-22 1999-03-25 가네꼬 히사시 Semiconductor device and manufacturing method
JP2000012539A (en) * 1998-06-17 2000-01-14 Nec Corp Manufacture of semiconductor device
KR20000045315A (en) * 1998-12-30 2000-07-15 김영환 Method for forming barrier layer of semiconductor device
JP2001085517A (en) * 1999-09-13 2001-03-30 Sony Corp Semiconductor device and manufacture thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990023749A (en) * 1997-08-22 1999-03-25 가네꼬 히사시 Semiconductor device and manufacturing method
JP2000012539A (en) * 1998-06-17 2000-01-14 Nec Corp Manufacture of semiconductor device
KR20000045315A (en) * 1998-12-30 2000-07-15 김영환 Method for forming barrier layer of semiconductor device
JP2001085517A (en) * 1999-09-13 2001-03-30 Sony Corp Semiconductor device and manufacture thereof

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