KR970053548A - Method of forming stacked via holes in semiconductor device - Google Patents

Method of forming stacked via holes in semiconductor device Download PDF

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Publication number
KR970053548A
KR970053548A KR1019950059661A KR19950059661A KR970053548A KR 970053548 A KR970053548 A KR 970053548A KR 1019950059661 A KR1019950059661 A KR 1019950059661A KR 19950059661 A KR19950059661 A KR 19950059661A KR 970053548 A KR970053548 A KR 970053548A
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KR
South Korea
Prior art keywords
forming
interlayer insulating
insulating film
film
via hole
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KR1019950059661A
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Korean (ko)
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KR100336654B1 (en
Inventor
정병현
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김주용
현대전자산업 주식회사
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Priority to KR1019950059661A priority Critical patent/KR100336654B1/en
Publication of KR970053548A publication Critical patent/KR970053548A/en
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Publication of KR100336654B1 publication Critical patent/KR100336654B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 적층 비아홀 형성방법에 관한 것으로, 본 발명은 반도체기판의 상부 표면에 접합층을 형성하고, 상기 반도체기판의 표면에 제1층간절연막을 형성하고, 상기 제1층간절연막의 상부에 제1배선막 패턴을 형성하고, 상기 구조의 전 표면에 제2층간절연막을 형성하고, 제2층간절연막, 금속막 및 제1층간절연막을 식각하여 적층비아홀을 형성하고, 상기 구조의 전 표면에 확산제어막을 형성하고, 적층비아홀을 형성하고, 상기 구조의 전 표면에 확산제어막을 형성하고, 적층비아홀을 충분히 매립되도록 금속층을 형성한 후 식각하되, 제2층간절연막이 노출될 때까지 평탄하게 식각하게 식각하고, 상기 구조의 전 표면에 제2배선막패턴을 형성하므로써, 공정을 단순하게 하고, 소자의 집적도를 향상한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a stacked via hole of a semiconductor device. The present invention provides a bonding layer formed on an upper surface of a semiconductor substrate, a first interlayer insulating film formed on a surface of the semiconductor substrate, and an upper portion of the first interlayer insulating film. A first wiring film pattern is formed on the second layer, a second interlayer insulating film is formed on the entire surface of the structure, the second interlayer insulating film, the metal film and the first interlayer insulating film are etched to form a laminated via hole, and the entire surface of the structure A diffusion control film is formed in the substrate, a stacked via hole is formed, a diffusion control film is formed on the entire surface of the structure, and a metal layer is formed to be sufficiently filled with the laminated via hole and then etched, until the second interlayer insulating film is exposed. By etching etched and forming the second wiring film pattern on the entire surface of the structure, the process is simplified and the degree of integration of the device is improved.

Description

반도체소자의 적층 비아홀 형성방법Method of forming stacked via holes in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2J도는 본 발명의 실시예에 따른 반도체소자의 적층 비아홀 제조 공정도이다.2A to 2J are process charts for manufacturing a stacked via hole of a semiconductor device according to an exemplary embodiment of the present invention.

Claims (8)

반도체기판의 상부 표면에 접합층을 형성하는 단계와, 상기 반도체기판의 표면에 제1층간절연막을 형성하는 단계와, 상기 제1층간절연막의 상부에 제1배선막 패턴을 형성하는 단계와, 상기 구조의 전 표면에 제2층간절연막을 형성하는 단계와, 제2층간절연막, 제1배선막패턴 및 제1층간절연막을 식각하여 적층 비아홀을 형성하는 단계와, 상기 구조의 전 표면에 확산제어막을 형성하는 단계와, 적층비아홀을 충분히 매립되도록 금속층을 형성한 후 식각하되, 제2층간절연막이 노출될 때까지 평탄하게 식각하는 단계와, 상기 구조의 전 표면에 제2배선막패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.Forming a bonding layer on an upper surface of the semiconductor substrate, forming a first interlayer insulating film on the surface of the semiconductor substrate, forming a first wiring layer pattern on the first interlayer insulating film, and Forming a second interlayer insulating film on the entire surface of the structure, etching the second interlayer insulating film, the first wiring film pattern and the first interlayer insulating film to form a stacked via hole, and forming a diffusion control film on the entire surface of the structure Forming a metal layer so as to sufficiently fill the stacked via holes, and etching the same, until the second interlayer insulating film is exposed, and forming a second wiring layer pattern on the entire surface of the structure. Laminated via hole forming method of a semiconductor device comprising a. 제1항에 있어서, 상기 확산제어막은 질화티타늄을 이용하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.The method of claim 1, wherein the diffusion control layer is formed of titanium nitride. 제1항에 있어서, 상기 확산제어막은 화학기상증착법으로 100 내지 300Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.The method of claim 1, wherein the diffusion control layer is formed to have a thickness of 100 to 300 μm by chemical vapor deposition. 제1항에 있어서, 상기 금속층으로 텅스텐을 사용하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.The method of claim 1, wherein tungsten is used as the metal layer. 제1항에 있어서, 상기 제2배선막으로 알루미늄을 사용하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.The method of claim 1, wherein aluminum is used as the second wiring film. 제1항에 있어서, 상기 제2배선막패턴을 스퍼터링방법으로 형성하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.The method of claim 1, wherein the second wiring pattern is formed by a sputtering method. 제1항에 있어서, 상기 적층비아홀이 충분히 메립되도록 금속층을 형성한 후 식각하되, 제2층간절연막이 노출될 때까지 평탄하게 식각하게 식각하는 단계와, 상기 구조의 전 표면에 제2배선막패턴을 형성하는 단계를 포함하는 대신에 화학기상중착법으로 금속층을 상기 적층비아홀에 충분히 메립하고, 계속하여 상기 금속층으로 제2배선막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.The method of claim 1, further comprising etching a metal layer to sufficiently fill the stacked via holes, and etching the same, until the second interlayer insulating layer is exposed, and etching the substrate to the entire surface of the structure. Instead of forming a step of forming a metal layer in the via via hole through the chemical vapor deposition method, and subsequently forming a second wiring film from the metal layer comprising the step of forming a stacked via hole of a semiconductor device. . 제6항에 있어서, 상기 금속층으로 구리 또는 알루미늄을 사용하는 것을 특징으로 하는 반도체소자의 적층 비아홀 형성방법.The method of claim 6, wherein copper or aluminum is used as the metal layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950059661A 1995-12-27 1995-12-27 Method for forming stacked via hole in semiconductor device KR100336654B1 (en)

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KR1019950059661A KR100336654B1 (en) 1995-12-27 1995-12-27 Method for forming stacked via hole in semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100753119B1 (en) * 2001-06-30 2007-08-29 주식회사 하이닉스반도체 Method for fabricating element in memory device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531373B2 (en) 2007-09-19 2009-05-12 Micron Technology, Inc. Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100753119B1 (en) * 2001-06-30 2007-08-29 주식회사 하이닉스반도체 Method for fabricating element in memory device

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