KR100645839B1 - Semiconductor device and method for fabrication of the same - Google Patents

Semiconductor device and method for fabrication of the same Download PDF

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KR100645839B1
KR100645839B1 KR1020050049586A KR20050049586A KR100645839B1 KR 100645839 B1 KR100645839 B1 KR 100645839B1 KR 1020050049586 A KR1020050049586 A KR 1020050049586A KR 20050049586 A KR20050049586 A KR 20050049586A KR 100645839 B1 KR100645839 B1 KR 100645839B1
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contact hole
film
plug
semiconductor device
pad plug
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KR1020050049586A
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Korean (ko)
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이주완
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
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  • Health & Medical Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor device and a manufacturing method thereof are provided to obtain a low resistance from an ohmic contact without the degradation of device characteristics by preventing phosphor ions from diffusing into a gate electrode and a predetermined junction region using an additional As ion implantation. A contact hole for exposing partially a silicon layer to the outside is formed on a substrate structure. A pad plug(208) is partially filled in the contact hole. An additional As ion implantation is performed on the pad plug. Then, a cobalt silicide layer(209), a barrier metal(210) and a cobalt layer(212) are sequentially deposited on the pad plug in the contact hole.

Description

반도체 소자 및 그 제조 방법{SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATION OF THE SAME}Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATION OF THE SAME}

도 1은 종래 기술에 따른 반도체 소자의 제조 공정을 나타낸 단면도.1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 제조 공정을 나타낸 단면도.2A to 2D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

201 : 반도체 기판 202 : 게이트 절연막201: semiconductor substrate 202: gate insulating film

203 : 게이트 전도막 204 : 텅스텐막203: gate conductive film 204: tungsten film

205 : 실리콘 산화막 206 : 실리콘 질화막205: silicon oxide film 206: silicon nitride film

207 : 층간절연막 208 : 패드 플러그207: interlayer insulating film 208: pad plug

209 : 금속실리사이드층 210 : 베리어 메탈209 metal silicide layer 210 barrier metal

212 : 금속막212: metal film

본 발명은 반도체 제조 기술에 관한 것으로 특히, 반도체 소자 제조 공정 중 콘택 플러그의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a contact plug during a semiconductor device manufacturing process.

반도체 소자가 점점 소형화, 고집적화되고 그 크기도 점점 작아지는 추세에 따라, 디램(DRAM)의 경우도 특히 셀 트랜지스터내의 채널 길이(Channel Length)및 콘택 사이즈가 함께 감소하고 있다. 상기 채널 길이의 감소로 내압 설계 마진(Margin)이 감소하여 플러그 농도를 높게 가지 못하는 한계가 나타나고, 콘택 사이즈의 감소로 실제적인 콘택 면적도 감소하게 되며, 이것은 콘택 저항(Contact Resistance)의 증가의 원인이 된다. 또한, 상술과 같은 이유로 동작 전류(Drive Current)가 감소하는 현상이 나타나고 있으며, 이로 인해 반도체 소자의 TWR 불량 및 리프레쉬(refresh) 특성 저하와 같은 소자 열화(Degradation) 현상이 나타나고 있다.As semiconductor devices become smaller, more integrated, and smaller in size, in particular, in the case of DRAM, the channel length and the contact size in the cell transistor are decreasing. Due to the reduction in the channel length, the design resistance (Margin) decreases, so that the plug concentration cannot be increased, and the contact size decreases, thereby reducing the actual contact area, which is the cause of the increase in the contact resistance. Becomes In addition, a phenomenon in which the drive current decreases has been exhibited for the same reason as described above, and as a result, a device degradation phenomenon such as a TWR defect and a decrease in refresh characteristics of a semiconductor device is exhibited.

도 1은 종래 기술에 따른 반도체 소자의 제조 공정을 나타낸 단면도이다.1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the prior art.

도 1을 참조하여, 반도체 기판(101)에 활성영역과 소자분리영역을 정의하는 소자분리막을 형성한다.Referring to FIG. 1, an isolation layer defining an active region and an isolation region is formed on a semiconductor substrate 101.

이어서, 상기 소자분리막이 형성된 기판 상에 게이트 절연막(102), 게이트 전도막(103), 텅스텐막(104)을 순차적으로 증착한 후, 선택적 식각하여 게이트 전극을 형성한다.Subsequently, the gate insulating layer 102, the gate conductive layer 103, and the tungsten layer 104 are sequentially deposited on the substrate on which the device isolation layer is formed, and then selectively etched to form a gate electrode.

이후, 상기 게이트 전극이 형성된 기판에 실리콘 산화막(105)과 실리콘 질화막(106)을 순차적으로 증착한 후, 선택적 식각하여 상기 게이트 전극을 감싸는 절 연층을 형성한다.Subsequently, the silicon oxide layer 105 and the silicon nitride layer 106 are sequentially deposited on the substrate on which the gate electrode is formed, and then selectively etched to form an insulating layer surrounding the gate electrode.

이어서, 상기 기판 상에 층간절연막(107)을 증착한 후, 화학적기계적 연마(CMP) 공정을 수행하여 상기 층간절연막(207)을 평탄화 한후, 콘택홀이 형성될 영역의 상기 층간절연막(207)을 식각하여 상기 기판이 노출되도록 콘택홀을 형성한다.Subsequently, after the interlayer insulating film 107 is deposited on the substrate, a chemical mechanical polishing (CMP) process is performed to planarize the interlayer insulating film 207, and then the interlayer insulating film 207 in the region where the contact hole is to be formed. Etching forms a contact hole to expose the substrate.

이어서, 상기 콘택홀 내의 상기 기판 상에 폴리실리콘막(108)을 매립하고, 화학적기계적연마 공정을 수행하여 콘택 플러그를 형성한다.Subsequently, a polysilicon film 108 is embedded on the substrate in the contact hole, and a chemical mechanical polishing process is performed to form a contact plug.

상기와 같이 폴리실리콘막(108)을 콘택 플러그로 사용하면, 공정이 단순하다는 장점이 있으나 비저항이 높은 폴리실리콘막(108)을 사용함으로 콘택 플러그 및 콘택저항이 높아 고속메모리에 적용할 수 없다는 문제점이 있다.When the polysilicon film 108 is used as a contact plug as described above, the process is simple, but the polysilicon film 108 having a high resistivity cannot be applied to a high speed memory due to the high contact plug and contact resistance. There is this.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 낮은 콘택저항의 콘택 플러그를 갖는 반도체 소자의 제조 방법을 제공하는 것을 그 목적으로 한다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device having a contact plug having a low contact resistance.

상기의 목적을 달성하기 위한 본 발명의 일측면에 따르면, 실리콘층을 일부 노출시키는 콘택홀을 형성하는 단계, 상기 콘택홀 내에 패드 플러그를 일부 매립하는 단계, 상기 패드 플러그에 불순물을 이온주입하는 단계 및 상기 콘택홀 내의 상기 패드 플러그 상에 형성되며, 코발트 실리사이드층과 베리어 메탈 및 금속막이 순차적으로 적층된 금속 플러그를 형성하는 단계를 포함하는 반도체 소자의 제조 방법을 제공한다.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.According to an aspect of the present invention for achieving the above object, forming a contact hole for partially exposing the silicon layer, partially embedding the pad plug in the contact hole, ion implantation of impurities into the pad plug And forming a metal plug formed on the pad plug in the contact hole and having a cobalt silicide layer, a barrier metal, and a metal film sequentially stacked thereon.
Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

삭제delete

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 제조 공정을 나타낸 단면도이다.2A to 2D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present invention.

본 발명에 따른 반도체 소자의 제조 공정은 우선, 도 2a에 도시된 바와 같이, 소자분리막이 형성된 기판(201) 상에 게이트 절연막(202), 게이트 전도막(203), 텅스텐막(204)을 순차적으로 증착한 후, 선택적 식각하여 게이트 전극을 형성한다.In the process of manufacturing a semiconductor device according to the present invention, first, as shown in FIG. 2A, a gate insulating film 202, a gate conductive film 203, and a tungsten film 204 are sequentially formed on a substrate 201 on which a device isolation film is formed. After deposition, the gate electrode is selectively etched to form a gate electrode.

삭제delete

이후, 상기 게이트 전극이 형성된 기판에 실리콘 산화막(205)과 실리콘 질화막(206)을 순차적으로 증착한 후, 선택적 식각하여 상기 게이트 전극을 감싸는 절연층을 형성한다.Thereafter, the silicon oxide layer 205 and the silicon nitride layer 206 are sequentially deposited on the substrate on which the gate electrode is formed, and then selectively etched to form an insulating layer surrounding the gate electrode.

이어서, 상기 기판 상에 층간절연막(207)을 증착한 후, 화학적기계적 연마(CMP) 공정을 수행하여 상기 층간절연막(207)을 평탄화 한후, 콘택홀이 형성될 영역의 상기 층간절연막(207)을 식각하여 상기 기판이 노출되도록 콘택홀을 형성한 다.Subsequently, after the interlayer insulating film 207 is deposited on the substrate, a chemical mechanical polishing (CMP) process is performed to planarize the interlayer insulating film 207, and then the interlayer insulating film 207 in the region where the contact hole is to be formed. Etching forms a contact hole to expose the substrate.

다음으로, 도 2b에 도시된 바와 같이, 상기 층간절연막(207)을 일부 식각하여 형성된 콘택홀 내에 일부 매립되도록 패드 플러그(208)를 형성한다.Next, as shown in FIG. 2B, a pad plug 208 is formed to be partially embedded in a contact hole formed by partially etching the interlayer insulating layer 207.

이때, 상기 패드 플러그(208)는 두께가 50~90nm이고, 2E18~5E18 atom/cm3의 인(P) 도핑 농도를 갖는 SEG막인 것이 바람직하다.In this case, the pad plug 208 is preferably a SEG film having a thickness of 50 to 90 nm and a phosphorus (P) doping concentration of 2E18 to 5E18 atom / cm 3 .

이어서, 상기 패드 플러그(208)에 이온주입 공정을 실시한다.Subsequently, an ion implantation process is performed on the pad plug 208.

이때, 상기 이온주입 공정은 2E14~8E14 atom/cm3의 도핑 농도를 갖는 비소(As)를 5~12kV의 이온주입 에너지로 이온주입하는 것이 바람직하다.In this case, the ion implantation process is preferably ion implanted arsenic (As) having a doping concentration of 2E14 ~ 8E14 atom / cm 3 with an ion implantation energy of 5 ~ 12kV.

그리고, 상기 비소는 상기 패드 플러그(208)내에 이온주입된 인(P)이 후속 열처리 공정시 게이트 전극 및 정션으로 확산되는 것을 방지한다.The arsenic prevents phosphorus (P) implanted into the pad plug 208 from diffusing to the gate electrode and the junction during the subsequent heat treatment process.

다음으로, 도 2c에 도시된 바와 같이, 상기 콘택홀 내에 일부 매립된 패드 플러그(208)를 포함하는 기판 상에 금속실리사이드층을 형성하기 위해 코발트를 증착한다.Next, as shown in FIG. 2C, cobalt is deposited to form a metal silicide layer on the substrate including the pad plug 208 partially embedded in the contact hole.

이때, 상기 코발트의 증착은 화학기상증착법 및 물리기상증착법으로 증착하며, 상기 물리기상증착법으로 증착시, 반응기의 압력은 1E-7~1E-8 Torr이며, 아르곤 분위기에서 형성하고, 공정 온도는 200~300℃에서 증착한다.At this time, the deposition of the cobalt is deposited by chemical vapor deposition and physical vapor deposition method, when the vapor deposition by the physical vapor deposition method, the pressure of the reactor is 1E-7 ~ 1E-8 Torr, formed in an argon atmosphere, the process temperature is 200 Deposit at ˜300 ° C.

이어서, 상기 코발트가 증착된 기판 상에 제1 열처리 공정을 수행하여 상기 패드 플러그(208) 상에 금속실리사이드층(209)를 형성한 후, 상기 코발트 중 미반응 된 코발트를 제거한다. Subsequently, the metal silicide layer 209 is formed on the pad plug 208 by performing a first heat treatment process on the cobalt-deposited substrate, and then unreacted cobalt is removed from the cobalt.

이때, 상기 제1 열처리 공정은 공정 온도가 650~750℃이고, 공정 시간이 20~60초이다.At this time, the first heat treatment step is a process temperature is 650 ~ 750 ℃, the process time is 20 ~ 60 seconds.

이어서, 상기 금속실리사이드층(209)의 재결정을 위한 제2 열처리 공정을 수행한다.Subsequently, a second heat treatment process for recrystallization of the metal silicide layer 209 is performed.

이때, 상기 제2 열처리 공정은 공정 온도가 750~850℃이고, 공정 시간이 20~60초이다.At this time, the second heat treatment step is a process temperature is 750 ~ 850 ℃, the process time is 20 ~ 60 seconds.

다음으로, 도 2d에 도시된 바와 같이, 상기 금속실리사이드층(209)이 형성된 기판 상에 베리어 메탈(210)과 금속막(212)을 순차적으로 증착한다.Next, as shown in FIG. 2D, the barrier metal 210 and the metal film 212 are sequentially deposited on the substrate on which the metal silicide layer 209 is formed.

이때, 상기 베리어 메탈(210)은 티타늄막과 티타늄질화막이 순차적으로 적층된 것으로써, 상기 티타늄막은 두께가 5~20nm인 것이 바람직하고, 상기 티타늄질화막은 10~20nm인 것이 바람직하다.In this case, the barrier metal 210 is a titanium film and a titanium nitride film is sequentially stacked, the titanium film is preferably 5 ~ 20nm in thickness, the titanium nitride film is preferably 10 ~ 20nm.

또한, 상기 금속막(212)은 코발트막으로써 화학기상증착법으로 증착하며, 소스 가스로는 CCTBA(CoCO)3CHC(CH3)3 이고, 환원 가스로는 수소이며, 공정 온도는 100~250℃이다.In addition, the metal film 212 is deposited by chemical vapor deposition as a cobalt film, the source gas is CCTBA (CoCO) 3 CHC (CH 3 ) 3 , the reducing gas is hydrogen, the process temperature is 100 ~ 250 ℃.

이어서, 상기 베리어 메탈(210)과 상기 금속막(212)을 화학적기계적연마 공정을 수행하여 금속 플러그를 형성한다.Subsequently, the barrier metal 210 and the metal film 212 are subjected to a chemical mechanical polishing process to form a metal plug.

즉, 본 발명에서는 종래 기술의 콘택 플러그로 사용된 폴리실리콘막보다 비저항이 훨씬 낮은 코발트를(비저항:6.24uΩcm) 이용함으로 저항을 낮출 수 있고 이는 회로를 흐르는 전류량을 증가시켜 소자의 동작속도를 향상시킬 수 있게 된다. That is, in the present invention, the resistance can be lowered by using cobalt (specific resistance: 6.44 uΩcm), which has a much lower specific resistance than the polysilicon film used as the contact plug of the prior art, which increases the amount of current flowing through the circuit, thereby improving the operation speed of the device. You can do it.

또한, 인이 이온주입된 상기 패드 플러그(208)에 비소를 추가 이온주입함으로 상기 인이 게이트 전극 및 정션으로 확산되는 것을 방지한다.Further, by implanting arsenic into the pad plug 208 implanted with phosphorus ion, the phosphorous is prevented from diffusing to the gate electrode and the junction.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

이상에서 살펴본 바와 같이, 본 발명은 상기 인이 이온주입된 패드 플러그에 비소를 추가 이온주입하여 열처리 공정시 상기 인이 게이트 전극 및 정션으로 확산되는 결함을 해결하여, 소자 특성의 열화 없이 저항이 낮은 오믹 콘택(ohmic contact) 금속 플러그를 형성하여 소자의 콘택 저항을 낮추고, 동작 전류를 향상 시키는 효과를 갖는다.As described above, the present invention solves the defect that the phosphorus is diffused to the gate electrode and the junction during the heat treatment process by additionally implanting arsenic into the pad plug in which the phosphorus ion is implanted, the resistance is low without deterioration of device characteristics Ohmic contact (ohmic contact) has the effect of forming a metal plug to lower the contact resistance of the device, and improve the operating current.

또한, 소자 설계의 마진(margin) 향상 및 소자 특성을 안전하게 유지하는 가운데, 콘택 저항 감소 효과를 얻어 신뢰성 및 수율을 향상시킨다.In addition, while improving the margin of the device design and safely maintaining the device characteristics, the contact resistance reduction effect is obtained to improve the reliability and yield.

그리고, 접촉 저항의 감소는 곧 소자의 동작 속도 증가 및 신뢰성 향상을 가져오게 된다.In addition, the decrease in contact resistance results in an increase in operating speed of the device and an improvement in reliability.

Claims (5)

실리콘층을 일부 노출시키는 콘택홀을 형성하는 단계;Forming a contact hole partially exposing the silicon layer; 상기 콘택홀 내에 패드 플러그를 일부 매립하는 단계;Partially embedding a pad plug in the contact hole; 상기 패드 플러그에 불순물을 이온주입하는 단계; 및Implanting impurities into the pad plug; And 상기 콘택홀 내의 상기 패드 플러그 상에 형성되며, 코발트 실리사이드층과 베리어 메탈 및 코발트막이 순차적으로 적층된 금속 플러그를 형성하는 단계Forming a metal plug formed on the pad plug in the contact hole and having a cobalt silicide layer, a barrier metal, and a cobalt film sequentially stacked thereon; 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 패드 플러그는 두께가 50~90nm이고, 2E18~5E18 atom/cm3의 인(P) 도핑 농도를 갖는 SEG막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The pad plug has a thickness of 50 nm to 90 nm, and is formed of a SEG film having a phosphorus (P) doping concentration of 2E18 to 5E18 atom / cm 3 . 제1항에 있어서,The method of claim 1, 상기 불순물을 이온주입하는 단계는 2E14~8E14 atom/cm3의 도핑 농도를 갖는 비소(As)를 5~12kV의 이온주입 에너지로 이온주입하는 것을 특징으로 하는 반도체 소자의 제조 방법.The ion implantation of the impurity is a method of manufacturing a semiconductor device, characterized in that the ion implantation of arsenic (As) having a doping concentration of 2E14 ~ 8E14 atom / cm 3 with 5 ~ 12kV ion implantation energy. 제1항에 있어서,The method of claim 1, 상기 코발트 실리사이드층은 두께가 5~20nm이고, 상기 베리어 메탈은 두께가 5~20nm인 티타늄막과 두께가 10~20nm인 티타늄질화막을 순차적으로 적층하여 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.The cobalt silicide layer has a thickness of 5 to 20 nm, and the barrier metal is formed by sequentially stacking a titanium film having a thickness of 5 to 20 nm and a titanium nitride film having a thickness of 10 to 20 nm. 제1항에 있어서,The method of claim 1, 상기 실리콘층은 실리콘 기판(substrate)인 것을 특징으로 하는 반도체 소자의 제조 방법.The silicon layer is a method of manufacturing a semiconductor device, characterized in that the silicon substrate (substrate).
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100833430B1 (en) * 2006-04-25 2008-05-29 주식회사 하이닉스반도체 Method of forming a drain contact plug in NAND flash memory device
US7410881B2 (en) 2006-03-02 2008-08-12 Hynix Semiconductor Inc. Method of manufacturing flash memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7410881B2 (en) 2006-03-02 2008-08-12 Hynix Semiconductor Inc. Method of manufacturing flash memory device
KR100833430B1 (en) * 2006-04-25 2008-05-29 주식회사 하이닉스반도체 Method of forming a drain contact plug in NAND flash memory device

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