KR100641952B1 - 반도체 소자의 미세 패턴 형성 방법 - Google Patents
반도체 소자의 미세 패턴 형성 방법 Download PDFInfo
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- KR100641952B1 KR100641952B1 KR1020040007844A KR20040007844A KR100641952B1 KR 100641952 B1 KR100641952 B1 KR 100641952B1 KR 1020040007844 A KR1020040007844 A KR 1020040007844A KR 20040007844 A KR20040007844 A KR 20040007844A KR 100641952 B1 KR100641952 B1 KR 100641952B1
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- 238000000034 method Methods 0.000 title claims abstract description 134
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 81
- 125000001475 halogen functional group Chemical group 0.000 claims abstract description 29
- 238000002513 implantation Methods 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 22
- 238000001312 dry etching Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 6
- 229910052794 bromium Inorganic materials 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 5
- 238000003860 storage Methods 0.000 claims description 5
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 claims description 4
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 150000004767 nitrides Chemical group 0.000 claims description 2
- 230000007261 regionalization Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract description 5
- 238000007796 conventional method Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000001459 lithography Methods 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011799 hole material Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000005843 halogen group Chemical group 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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Abstract
Description
Claims (14)
- 반도체 기판 상부에 피식각층을 형성하는 단계;상기 피식각층 상부에 대하여 제 1 포토레지스트층을 형성하는 단계;비트라인 노드 콘택이 형성될 부분만 오픈 되어 있고, 나머지 광 차단막 부분은 예정된 피식각층 패턴 라인 두 개와 스페이스 하나를 합한 만큼의 폭을 갖는 제 1 노광 마스크를 이용하여 상기 제 1 포토레지스트층에 대한 노광 및 현상 공정을 수행함으로써, 피식각층 패턴 라인 두 개와 스페이스 하나를 포함하는 폭을 가지는 제 1 포토레지스트 패턴을 형성하는 단계;상기 제 1 포토레지스트 패턴을 식각 마스크로 기판이 노출될 때까지 하부 피식각층에 대한 건식 식각 공정을 수행하여 제 1 피식각층 패턴을 형성하는 단계;상기 제 1 피식각층 패턴간의 스페이스에 대하여 C-할로 주입 공정을 수행하여 이온 주입 영역을 형성하는 단계;상기 이온 주입 영역이 형성된 제 1 피식각층 패턴의 전면에 제 2 포토레지스트층을 형성하는 단계;스토리지 노드 콘택이 형성될 부분만 오픈 되어 있고, 나머지 광 차단막 부분은 예정된 피식각층 패턴 라인 두 개와 스페이스 하나를 합한 만큼의 폭을 갖는 제 2 노광 마스크를 이용하여 상기 제 2 포토레지스트층에 대한 노광 및 현상 공정을 수행함으로써, 피식각층 패턴 라인 두 개와 스페이스 하나를 포함하는 폭을 가지는 제 2 포토레지스트 패턴을 형성하는 단계; 및상기 제 2 포토레지스트 패턴을 식각 마스크로 기판이 노출될 때까지 상기 제 1 피식각층 패턴에 대한 건식 식각 공정을 수행하여 제 2 피식각층 패턴을 형성하는 단계를 포함하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 C-할로 임플란트 공정 후 또는 공정 전에 크리닝(cleaning) 공정을 수행하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 1 피식각층 패턴 폭은 30∼450nm이고, 패턴 간의 스페이스 폭은 30∼300nm인 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 1 피식각층 패턴 폭은 90∼300nm이고, 패턴 간의 스페이스 폭은 60∼150nm인 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 2 피식각층 패턴 폭은 10∼150nm이고, 패턴 간의 스페이스 폭은 10∼150nm인 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 건식 식각 공정은 피식각층이 질화막일 경우 CHF3, O2 및 Ar로부터 이루어진 군으로부터 선택된 단독 또는 혼합 가스를 사용하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 건식 식각 공정은 피식각층이 금속층일 경우 SF6, Ar 가스 또는 이들의 혼합 가스를 사용하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 건식 식각 공정은 피식각층이 폴리(poly)층일 경우 Cl2, HBr 및 O2 로부터 이루어진 군으로부터 선택된 단독 또는 혼합 가스를 사용하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 C-할로 주입 공정은 브롬(Br) 또는 이불화 붕소(BF2) 이온을 이용하여 수행되는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 2 피식각층 패턴 형성 후에, 전자 또는 홀(hole) 물질을 기판 전면에 추가로 진행하는 블랭킷(blanket) 주입 공정을 수행하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 1 포토레지스트 패턴 및 제 2 포토레지스트 패턴 형성 후, 120∼300℃ 분위기 하에서 상기 포토레지스트 물질을 팽창시키거나 레지스트 플로우(resist flow) 공정을 수행하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 포토레지스트층은 포지티브(positive)형 또는 네거티브(negative)형 포토레지스트 물질을 사용하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 1 노광 마스크 및 제 2 노광 마스크의 적용 순서는 바꾸어 수행하는 것을 특징으로 하는 반도체 소자의 미세 패턴 형성 방법.
- 반도체 기판 상부에 피식각층을 형성하는 단계;상기 피식각층 상부에 대하여 제 1 포토레지스트층을 형성하는 단계;비트라인 노드 콘택이 형성될 부분만 오픈 되어 있고, 나머지 광 차단막 부분은 예정된 피식각층 패턴 라인 두 개와 스페이스 하나를 합한 만큼의 폭을 갖는 제 1 노광 마스크를 이용하여 상기 제 1 포토레지스트층에 대한 노광 및 현상 공정을 수행함으로써, 피식각층 패턴 라인 두 개와 스페이스 하나를 포함하는 폭을 가지는 제 1 포토레지스트 패턴을 형성하는 단계;상기 제 1 포토레지스트 패턴을 식각 마스크로 기판이 노출될 때까지 하부 피식각층에 대한 건식 식각 공정을 수행하여 제 1 피식각층 패턴을 형성하는 단계;상기 제 1 피식각층 패턴의 전면에 제 2 포토레지스트층을 형성하는 단계;스토리지 노드 콘택이 형성될 부분만 오픈 되어 있고, 나머지 광 차단막 부분은 예정된 피식각층 패턴 라인 두 개와 스페이스 하나를 합한 만큼의 폭을 갖는 제 2 노광 마스크를 이용하여 상기 제 2 포토레지스트층에 대한 노광 및 현상 공정을 수행함으로써, 피식각층 패턴 라인 두 개와 스페이스 하나를 포함하는 폭을 가지는 제 2 포토레지스트 패턴을 형성하는 단계;상기 제 2 포토레지스트 패턴을 식각 마스크로 기판이 노출될 때까지 상기 제 1 피식각층 패턴에 대한 건식 식각 공정을 수행하여 제 2 피식각층 패턴을 형성하는 단계; 및상기 제 2 피식각층 패턴간의 스페이스에 대하여 C-할로 주입 공정을 수행하여 이온 주입 영역을 형성하는 단계를 포함하는 반도체 소자의 미세 패턴 형성 방 법.
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TWI265564B (en) * | 2005-09-16 | 2006-11-01 | Univ Nat Chiao Tung | Method for forming gate pattern for electronic device |
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KR100772819B1 (ko) * | 2006-01-26 | 2007-11-01 | 주식회사 하이닉스반도체 | 반도체 소자의 센스 증폭기 제조 방법 |
US20070212649A1 (en) * | 2006-03-07 | 2007-09-13 | Asml Netherlands B.V. | Method and system for enhanced lithographic patterning |
KR100695438B1 (ko) * | 2006-04-28 | 2007-03-16 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
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JP2008153328A (ja) * | 2006-12-15 | 2008-07-03 | Elpida Memory Inc | 薄膜パターン形成方法及び半導体装置の製造方法 |
US8501395B2 (en) * | 2007-06-04 | 2013-08-06 | Applied Materials, Inc. | Line edge roughness reduction and double patterning |
KR101271174B1 (ko) * | 2007-08-03 | 2013-06-04 | 삼성전자주식회사 | 비트라인 레이아웃의 구조를 개선한 플래시 메모리 장치 및그 레이아웃 방법 |
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JP2010283095A (ja) * | 2009-06-04 | 2010-12-16 | Hitachi Ltd | 半導体装置の製造方法 |
JP5159738B2 (ja) * | 2009-09-24 | 2013-03-13 | 株式会社東芝 | 半導体基板の洗浄方法および半導体基板の洗浄装置 |
JP2016181628A (ja) * | 2015-03-24 | 2016-10-13 | キヤノン株式会社 | 半導体装置の製造方法 |
KR20170016107A (ko) | 2015-08-03 | 2017-02-13 | 삼성전자주식회사 | 반도체 장치 제조 방법 |
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